Abstract: A semiconductor device includes a first semiconductor diffusion region of a first transistor, a second semiconductor diffusion region of a second transistor, and a third semiconductor diffusion region that connects the first and second semiconductor diffusion regions to each other.

Abstract: A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse (93) or resistor (95), in an active substrate region (103) by using heavy ion implantation (30) and annealing (40) to selectively form polycrystalline structures (42, 44) from a monocrystalline active layer (103), while retaining the single crystalline regions in the active layer (103) for use in forming active devices, such as NMOS and/or PMOS transistors (94). As disclosed, fuse structures (93) may be fabricated by forming silicide (90) in an upper region of the polycrystalline structure (42), while resistor structures (95) may be simultaneously formed from polycrystalline structure (44) which is selectively masked during silicide formation.

Abstract: The present disclosure provides an integrated circuit having metal gate stacks. The integrated circuit includes a semiconductor substrate; a gate stack disposed on the semiconductor substrate, wherein the gate stack includes a high k dielectric layer and a first metal layer disposed on the high k dielectric layer; and a raised source/drain region configured on a side of the gate stack and formed by an epitaxy process, wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the raised source/drain region.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A semiconductor device includes a gate electrode. The gate electrode includes a silicide layer obtained by siliciding porous silicon or organic silicon.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A high frequency/high output semiconductor device, which is excellent in heat resistance and by which an uneven operation is suppressed, is provided. A semiconductor device, include a semiconductor substrate, a plurality of unit cells connected in parallel with each other, each of the unit cells include a plurality of electric field effect transistors formed on the semiconductor substrate, a plurality of gate bus wiring each configured to connect each of the gate electrodes of the transistors constituting the unit cell, a plurality of gate pad electrodes having multi-layered structure of conductive layers, each of the gate pad electrodes connected to the gate bus wiring, and a resistive element configured to connect the adjacent gate pad electrodes having formed along at least one side of outer peripheral portion of the gate pad electrode, and formed of at least one conductive layer of the conductive layers constituting the gate pad electrode.

Abstract: The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

Abstract: A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the same conductive type, and the first transistor and the second transistor have the same threshold voltage. A first well is formed in the first element formation region by use of a first mask pattern, and a second well is formed in the second element formation region by use of a second mask pattern. A channel region of the first transistor and a channel region of the second transistor have a shape which is line-symmetrical with respect to a reference line. The first mask pattern has a shape which is line-symmetrical with respect to the reference line.

Abstract: In a CMOS manufacturing process flow, a cap layer formed on top of a gate electrode material may be maintained throughout the entire implantation sequence for defining the drain and source regions and may be removed during an etch process in which the width of a sidewall spacer structure may be reduced so as to reduce a lateral offset of metal silicide regions and of a stressed dielectric material. Thus, overall enhanced transistor performance may be obtained while nevertheless providing a high degree of compatibility with existing CMOS process strategies.

Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.

Abstract: A high-voltage metal oxide semiconductor device comprising a main body of a first conductivity type, a conductive structure, a first well of a second conductivity type, a source region of the first conductivity type, and a second well of the second conductivity type is provided. The conductive structure has a first portion and a second portion. The first portion is extended from an upper surface of the main body into the main body. The second portion is extended along the upper surface of the main body. The first well is located in the main body and below the second portion. The first well is kept away from the first portion with a predetermined distance. The source region is located in the first well. The second well is located in the main body and extends from a bottom of the first portion to a place close to a drain region.

Abstract: An integrated circuit having a gate dielectric layer (414, 614, 814) having an improved nitrogen profile and a method of fabrication. The gate dielectric layer is a graded layer with a significantly higher nitrogen concentration at the electrode surface than near the substrate surface. An amorphous silicon layer (406) may be deposited prior to nitridation to retain the nitrogen concentration at the top surface (416). Alternatively, a thin silicon nitride layer (610) may be deposited after anneal or a wet nitridation process may be performed.

Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.

Abstract: An embodiment of a microelectromechanical device having a first structural element, a second structural element, which is mobile with respect to the first structural element, and an elastic supporting structure, which extends between the first and second structural elements to enable a relative movement between the first and second structural elements. The microelectromechanical device moreover possesses an anti-stiction structure, which includes at least one flexible element, which is fixed only with respect to the first structural element and, in a condition of rest, is set at a first distance from the second structural element. The anti-stiction structure is designed to generate a repulsive force between the first and second structural elements in the case of relative movement by an amount greater than the first distance.

Abstract: Spin-transfer torque memory having a compensation element is disclosed. The spin-transfer torque memory unit includes a synthetic antiferromagnetic reference element, a synthetic antiferromagnetic compensation element, a free magnetic layer between the synthetic antiferromagnetic reference element and the synthetic antiferromagnetic compensation element, and an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the synthetic antiferromagnetic reference element. The free magnetic layer has a saturation moment value greater than 1100 emu/cc.

Abstract: Flux-closed spin-transfer torque memory having a specular insulative spacer is disclosed. A flux-closed spin-transfer torque memory unit includes a multilayer free magnetic element including a first free magnetic layer anti-ferromagnetically coupled to a second free magnetic layer through an electrically insulating and electronically reflective layer. An electrically insulating and non-magnetic tunneling barrier layer separates the free magnetic element from a reference magnetic layer.

Abstract: Spin-transfer torque memory having a specular insulative spacer is disclosed. The spin-transfer torque memory unit includes a free magnetic layer, a reference magnetic layer, an electrically insulating and non-magnetic tunneling barrier layer separating the free magnetic layer from the reference magnetic layer, an electrode layer, and an electrically insulating and electronically reflective layer separating the electrode layer and the free magnetic layer.

Abstract: A solid-state imaging device includes light-sensing sections serving as pixels, and waveguides each including a core layer and a cladding layer, the waveguides each being disposed at a position corresponding to one of the light-sensing sections. A cross-sectional structure of the waveguide taken in the horizontal direction of an imaging plane is different from a cross-sectional structure of the waveguide taken in the vertical direction of the imaging plane.

Abstract: A solid-state imaging device includes a light-receiving portion, which serves as a pixel, and a waveguide, which is disposed at a location in accordance with the light-receiving portion and which includes a clad layer and a core layer embedded having a refractive index distribution in the wave-guiding direction.

Abstract: A semiconductor device, an image sensor, and methods of manufacturing the same. A semiconductor device may include metal interconnections formed over a lower substrate, a hard mask formed over metal interconnections, and/or an insulating layer formed over a surface of a lower substrate. A semiconductor device may include an insulating layer including an air gap formed between metal interconnections. An image sensor may include a pixel array area having photodiodes and transistors, and/or a logic area having a plurality of transistors, which may be formed over a semiconductor substrate. An image sensor may include a metal interconnection and/or an insulating layer structure connected to transistors, and may cover a pixel array area and/or a logic area. An image sensor may include a color filter layer formed over a pixel array area, and an insulating layer structure of a pixel array area having an air gap between metal interconnections.

Abstract: An image sensing device and a packaging method thereof is disclosed. The packaging method includes the steps of providing an adhesive layer; placing a substrate, having an opening, on the adhesive layer; disposing an image sensor within the opening on the adhesive layer; adding a filler between the image sensor and the substrate; connecting the image sensor and the substrate via a plurality of bonding wires; and removing the adhesive layer.

Abstract: A solid-state image pickup device relating to the present invention has a specific gap in a part of a lattice-shaped light blocking film pattern or wiring pattern having an opening enclosing a light reception region. Peripheral circuits and wiring layers on a pixel may be used as the light blocking film. In such a case, when multiple wiring layers are used as the light blocking film, layouts of a second and subsequent wiring layers is determined according to the layout of the first wiring layer above the light reception region. The specific gap is created in a part of the wiring enclosing the light reception region.

Abstract: In a range image sensor 8, when a first reverse bias voltage applied between a semiconductor substrate 11 and first semiconductor regions 13 is an H bias, first depleted layers A1 and A1 expanding from the p-n junctions of the first semiconductor regions 13 adjacent to each other expand and link to each other so as to cover a second depleted layer B1 expanding from the p-n junction of a second semiconductor region 14. Accordingly, carriers C generated near the rear surface 11a of the semiconductor substrate 11 are reliably captured by the first depleted layers A1. Further, when a second reverse bias voltage applied between the semiconductor substrate 11 and the second semiconductor regions 14 is an H bias, the second depleted layers adjacent to each other expand and link to each other so as to cover the first depleted layer. Accordingly, carriers generated near the rear surface of the semiconductor substrate are reliably captured by the second depleted layers.

Abstract: An image sensor includes readout circuit arranged over a semiconductor substrate, an interlayer dielectric film covering the readout circuit and including metal lines, a buffer layer arranged over the interlayer dielectric film, a crystallized silicon layer arranged over the buffer layer, an ion-implantation layer to partition photodiode regions corresponding to unit pixels in the crystallized silicon layer, and a metal plug arranged in a via-hole of the buffer layer, to electrically connect the photodiode region to the metal lines. In accordance with the method, a channel, enabling smooth transfer of photocharges, is provided between the photodiode and the readout circuit, to minimize dark current sources and prevent a deterioration in saturation and sensitivity and thereby improve image properties.

Abstract: Disclosed are an image sensor and a method for manufacturing the same. The image sensor can include a readout circuitry on a first substrate; an interlayer dielectric layer including at least one metal and contact plug electrically connected to the readout circuitry; and an image sensing device formed on a second substrate, bonded to the interlayer dielectric layer, and provided with a first conductive type conduction layer and a second conductive type conduction layer. An uppermost contact plug in the interlayer dielectric layer has a wall structure extending from an uppermost metal in the interlayer dielectric layer. The top surface of the uppermost contact plug makes contact with the image sensing device and is connected to an image sensing device and an uppermost metal of an adjacent pixel.

Abstract: An image sensor and manufacturing method thereof are provided. The image sensor includes a readout circuitry, an electrical junction region, an interconnection, and an image sensing device. The readout circuitry can be disposed at a first substrate, and the electrical junction region can be electrically connected to the readout circuitry at the first substrate. The interconnection can be disposed in an interlayer dielectric on the first substrate and electrically connected to the electrical junction region. The image sensing device can include a first conductive type layer and a second conductive type layer on the interconnection.

Abstract: A method for forming a flow sensor having self-supported heat-carrying elements is disclosed. Self-supported heat-carrying elements are capable of operating with higher thermal efficiency, enabling lower power consumption and higher sensitivity, due to a lack of heat loss into a supporting membrane. Self-supported heat-carrying elements facilitate wider operating temperature range and compatibility with harsh media.

Abstract: A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.

Abstract: An exemplary edge termination structure maintains the breakdown voltage of the semiconductor device after it has been sawed off the wafer and packaged by creating an electric field stop layer at a periphery of the semiconductor device. The electric field stop layer has a dopant concentration higher than that of the layer in which an edge termination is implemented, such as a drift layer or a channel layer. The electric field stop layer may be created by selectively masking the peripheries of the device during the device processing, i.e., mesa etch, to protect and preserve the highly doped material at the peripheries of the device.

Abstract: A semiconductor device includes a semiconductor body with a front-sided surface. An active cell region with a semiconductor device structure and an edge region surrounding the active cell region are arranged in the semiconductor body. The front-sided surface of the semiconductor body includes a passivation layer over the edge region and over the active cell region. The passivation layer includes a semiconducting insulation layer of a semiconducting material, the bandgap of which is greater than the bandgap of the material of the semiconductor body.

Abstract: Disclosed herein is a semiconductor device including an isolation structure and a recess gate and a method for fabricating the same. The method for fabricating a semiconductor device includes: forming a trench by selectively etching an isolation region of a semiconductor substrate to define an active region; forming a first SOD partially filling the trench; forming a stress shielding layer, which is denser than the first SOD, over the first SOD; forming a second SOD that fills the trench over the first SOD including the stress shielding layer; forming a recess groove by selectively etching a portion of the active region, wherein an upper surface of the first SOD is spaced downwardly from a bottom of the recess groove, and an upper surface of the stress shielding layer is spaced upwardly from the bottom of the recessed groove; and forming a gate of a transistor that fills the recess groove.

Abstract: A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises a first electrode comprising a first metal, a first region comprising a first insulating material, a second region comprising a second insulating material, and a second electrode comprising a second metal. The first region and the second region reside between the first electrode and the second electrode. The second insulating material is doped with nitrogen. Note that the second insulating material may have an interface with either the first electrode or the second electrode.

Abstract: A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench.

Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.

Abstract: A planar transformer structure, which can be constructed in an integrated semiconductor circuit without using traditional metallic windings. To avoid large thermal expansion of metallic spiral windings and associated mechanical stress on a metal-semiconductor interface, it is suggested that highly doped semiconductor materials with or without silicides and salicides can be used to form windings or conducting paths because their thermal expansion coefficients are similar to that of semiconductor material. The planar semiconductor transformer may find application for low-power and signal transfer that needs electrical isolation.

Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.

Abstract: A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer.

Abstract: A description is given of a concept for reducing shunt currents in a semiconductor body.

Abstract: A power semiconductor component is described. One embodiment provides a semiconductor body having an inner zone and an edge zone. A base zone of a first conduction type is provided. The base zone is arranged in the at least one inner zone and the at least one edge zone. An emitter zone of a second conduction type is provided. The emitter zone is arranged adjacent to the base zone in a vertical direction of the semiconductor body. A field stop zone of the first conduction type is provided. The field stop zone is arranged in the base zone and has a first field stop zone section having a first dopant dose in the edge zone and a second field stop zone section having a second dopant dose in the inner zone. The first dopant dose is higher than the second dopant dose.

Abstract: A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.

Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10 % over the bulk area.

Abstract: A wafer-cutting process includes first cutting a semiconductive wafer along a first path at a given first cutting intensity including cutting across an intersection. The process also includes second cutting the semiconductive wafer along a second path at a given second cutting intensity. The second cutting intensity is diminished during crossing the intersection and resumed to the given cutting intensity after crossing the intersection.

Abstract: In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe seal follows the perimeter of the die and into the corners, with the outer scribe seal having a continuous barrier wall towards the die edges so that moisture penetration in dielectric layers of the die is minimized, and cracks and delamination are stopped near the die edges. Limiting the extent of the insulating layer or layers in the WLCSP to cover the functional circuit area also reduces the stresses caused by these layers near the die corners. Other features further enhance the strength and barrier properties of the scribe seals and the layers near the die corners, terminate cracks and delamination at various levels within the dielectric stack of the die and the die protective overcoat, and prevent damage during the WLCSP assembly process.

Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.

Abstract: Metallised through silicon vias located in the scribe lanes between die are used to create an electrical connection between the front-side and the rear-side of a silicon die. One of the metallisation layers on the front-side of the die comprises portions which extend into the scribe lanes to form capture pads for the through silicon vias. The rear-side of the wafer is metallised and this metallisation may, in some embodiments, be patterned to form tracks or components. The silicon die may be used to create improved package on package devices. In other examples, other substrate materials may be used.

Abstract: A semiconductor device includes a substrate, a semiconductor device structure over the substrate, an insulating film that covers the semiconductor device structure, and a stress-compensation film over the insulating film. The stress-compensation film has a first stress that compensates a second stress working to bend the substrate.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the channel stop trench extends from the first surface at least partially into the semiconductor substrate and is arranged between the active area and the peripheral area. At least one electrode is arranged in the channel stop trench. The semiconductor substrate includes at least a peripheral contact region, which is arranged in the peripheral area at the first surface of the semiconductor substrate. A conductive layer is provided and in electrical contact with the electrode arranged in the channel stop trench and in electrical contact with the peripheral contact region. The conductive layer is electrically connected to the semiconductor substrate merely in the peripheral area and electrically insulated from the semiconductor substrate in the active area.

Abstract: A semiconductor device has a cell field with drift zones of a first type of conductivity and charge carrier compensation zones of a second type of conductivity complementary to the first type. An edge region which surrounds the cell field has a higher blocking strength than the cell field, the edge region having a near-surface area which is undoped to more weakly doped than the drift zones, and beneath the near-surface area at least one buried, vertically extending complementarily doped zone is positioned.