Abstract: An object of the present invention is to provide a method for producing a gallium nitride-based compound semiconductor multilayer structure useful for the production of a gallium nitride-based compound semiconductor light-emitting device which can ensure that the operating voltage is reduced, the light emission output is good and the light emission output is less changed due to aging.

Abstract: Non-polar or semi-polar (Al, Ga, In)N substrates are fabricated by re-growth of (Al, Ga, In)N crystal on (Al, Ga, In)N seed crystals, wherein the size of the seed crystal expands or is increased in the lateral and vertical directions, resulting in larger sizes of non-polar and semi-polar substrates useful for optoelectronic and microelectronic devices. One or more non-polar or semi-polar substrates may be sliced from the re-grown crystal. The lateral growth rate may be greater than the vertical growth rate. The seed crystal may be a non-polar seed crystal. The seed crystal may have crystalline edges of equivalent crystallographic orientation.

Abstract: A method of forming a semiconductor device includes providing a bumped wafer. A plurality of grooves is formed in an active surface of the bumped wafer. A pre-underfill layer is disposed over the active surface, filling the plurality of grooves. A first adhesive layer is mounted to the pre-underfill layer, and a back surface of the bumped wafer is ground. A second adhesive layer is mounted to the back surface of the bumped wafer. The first adhesive layer is peeled from the active surface of the bumped wafer, or the second adhesive layer is mounted to the first adhesive layer. The bumped wafer is singulated into a plurality of segments by cutting the bumped wafer along the plurality of grooves.

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

Abstract: A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

Abstract: A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.

Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.

Abstract: A diffusion barrier film includes a layer of compositionally graded titanium nitride, having a nitrogen-rich portion and a nitrogen-poor portion. The nitrogen-rich portion has a composition of at least about 40% (atomic) N, and resides closer to the dielectric than the nitrogen-poor portion. The nitrogen-poor portion has a composition of less than about 30% (atomic) N (e.g., between about 5-30% N) and resides in contact with the metal, e.g., copper. The diffusion barrier film can also include a layer of titanium residing between the layer of dielectric and the layer of compositionally graded titanium nitride. The layer of titanium is often partially or completely converted to titanium oxide upon contact with a dielectric layer. The barrier film having a compositionally graded titanium nitride layer provides excellent diffusion barrier properties, exhibits good adhesion to copper, and reduces uncontrolled diffusion of titanium into interconnects.

Abstract: A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.

Abstract: A method includes forming a phase change material layer on a substrate using a deposition process that employs a process gas. The process gas includes a germanium source gas, and the germanium source gas includes at least one of the atomic groups “—N?C?O”, “—N?C?S”, “—N?C?Se”, “—N?C?Te”, “—N?C?Po” and “—C?N”.

Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed.

Abstract: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.

Abstract: An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.

Abstract: In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.

Abstract: Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

Abstract: A method of manufacturing a semiconductor device, including the following processes of forming a structure in which a barrier metal containing at least of Ti and Ta and a copper wiring are exposed on its surface, or a structure in which at least one substance selected from the group consisting of Ti, W, and Cu and Al are exposed on its surface, above a semiconductor substrate, and supplying a hydrogen-dissolved solution dissolving hydrogen gas to the surface of the structure.

Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

Abstract: In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.

Abstract: An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

Abstract: Disclosed is a substrate processing method that dissolves and deforms a photoresist film having a first pattern formed on a substrate to reshape the resist film into a second pattern During the reflow process, an atmosphere of a thinner vapor-containing gas is established in a processing chamber. A substrate is placed on a temperature adjusting plate. The target temperature of the temperature adjusting plate is set and controlled by a control unit, and the temperature of the temperature adjusting plate is controlled by a temperature regulator based on the target temperature set by the control unit The control unit set and controls the target temperature so that it meets the following requirement: the atmospheric temperature?the target temperature?(the atmospheric temperature+2° C.). Due to the above, the reflowing of the resist can be performed stably, while achieving a satisfactory reflow rate although it is somewhat low.

Abstract: A method for forming a stacked-die structure is disclosed in which a buried oxide layer is formed in a semiconductor wafer. Device layers and metal layers are formed on the face side of the semiconductor wafer, defining dice, with each die including an interconnect region. Openings are etched in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer. Conductive material is deposited within the openings so as to form through-die vias. The semiconductor wafer is then attached to a wafer support structure and material is removed from the backside of the semiconductor wafer so as to form an oxide layer having a thickness that is less than the initial thickness of the buried oxide layer.

Abstract: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: A manufacturing method of a semiconductor device is carried out as follows. A first mask layer having a first linear opening pattern is formed above the first interlayer insulating layer. A second mask layer having a plurality of second linear opening patterns and first dummy opening patterns is formed above the first mask layer. The plurality of second linear opening patterns are aligned above the first linear opening pattern at given intervals to cross the first linear opening pattern. The first dummy opening patterns are arranged in close proximity to a first pattern remaining region that is present between the second linear opening patterns adjacent to each other. The first interlayer insulating layer that is present below opening patterns obtained by overlap portions of the first linear opening pattern and the second linear opening patterns is etched to form holes.

Abstract: A cleaning sequence usable in semiconductor manufacturing efficiently cleans semiconductor substrates while preventing chemical oxide formation thereon. The sequence includes the sequence of: 1) treating with an HF solution; 2) treating with pure H2SO4; 3) treating with an H2O2 solution; 4) a DI water rinse; and 5) treatment with an HCl solution. The pure H2SO4 solution may include an H2SO4 concentration of about ninety-eight percent (98%) or greater. After the HCl solution treatment, the cleaned surface may be a silicon surface that is free of a chemical oxide having a thickness of 5 angstroms or greater. The invention finds particular advantage in semiconductor devices that utilize multiple gate oxide thicknesses.

Abstract: A method of forming an ink, the ink configured to form a conductive densified film is disclosed. The method includes providing a set of Group IV semiconductor particles, wherein each Group IV semiconductor particle of the set of Group IV semiconductor particles includes a particle surface with a first exposed particle surface area. The method also includes reacting the set of Group IV semiconductor particles to a set of bulky capping agent molecules resulting in a second exposed particle surface area, wherein the second exposed particle surface area is less than the first exposed particle surface area. The method further includes dispersing the set of Group IV semiconductor particles in a vehicle, wherein the ink is formed.

Abstract: There is provided an underlayer coating that causes no intermixing with photoresist layer, can be formed by a spin-coating method, and can be used as a hard mask in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition used in manufacture of semiconductor device including metal nitride particles having an average particle diameter of 1 to 1000 nm, and an organic solvent. The metal nitride particles contain at least one element selected from the group consisting of titanium, silicon, tantalum, tungsten, cerium, germanium, hafnium, and gallium.

Abstract: A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures.

Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.

Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is arranged as a structure of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

Abstract: A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided. A manufacturing method of a semiconductor device includes: a step of forming a dielectric thin film in which a plurality of pores are arranged around a skeleton mainly made of a Si—O bond, on a surface of a semiconductor substrate on which a desired element region is formed; a step of applying patterning on a surface of the dielectric thin film through a mask; and a step of bringing a gas containing at least one kind of tetramethylcyclotetrasiloxane (TMCTS), hexamethyldisilazane (HMDS) and trimethylchlorosilane (TMCS) molecules into contact with the patterned surface of the dielectric thin film.

Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

Abstract: A method for producing complex metal oxide having nano-sized grains that includes the steps of forming a mixture containing at least one metal cation dissolved in a solution and particulate material containing at least one further metal in the form of metal(s) or metal compound(s) and treating the mixture to form the complex metal oxide having nano-sized grains. The at least one further metal from the particulate material becomes incorporated into the complex metal oxide.

Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain zirconium are deposited onto a substrate and subsequently processed to form zirconium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: In formation of a gate insulating film made of a high dielectric constant metal silicate, atomic layer deposition (ALD) is performed by setting exposure time to a precursor containing a metal or the like to saturation time of a deposition rate by a surface adsorption reaction and by setting exposure time to an oxidizing agent to time required for a composition of a metal oxide film to reach 97% or more of a stoichiometric value.

Abstract: A method light enhanced atomic layer deposition for forming a film on a substrate. The method includes disposing the substrate in a process chamber of a light enhanced atomic layer deposition (LEALD) system configured to perform a LEALD process; and depositing a film on the substrate using the LEALD process, where the depositing includes (a) exposing the substrate to a first process material, (b) exposing the substrate to a second process material containing a reducing agent and irradiating the substrate with a first light radiation having either no or at least partial temporal overlap with the exposing of the substrate to the second process material, (c) repeating steps (a) and (b) until the desired film has been deposited. According to one embodiment of the invention, the deposited film can be a TaCN film or a TaC film.

Abstract: A method of crystallizing a semiconductor film including splitting a pulse laser beam oscillated from a laser oscillator, and synthesizing the split pulse laser beams after the split pulse laser beams have propagated through optical paths different in optical path length, modulating the synthesized pulse laser beam into a pulse laser beam by a phase modulating element, and irradiating a non-single-crystal film formed on a substrate with the laser beam to crystallize the non-single-crystal film. Splitting the pulse laser beam and synthesizing the split pulse laser beams are performed using at least three optical splitting/synthesizing units arranged in order, and include sequentially splitting one pulse laser beam split by one optical splitting/synthesizing unit by succeeding splitting/synthesizing unit, and synthesizing the other pulse laser beam split by one optical splitting/synthesizing unit with the other pulse laser beam split by preceding splitting/synthesizing unit.

Abstract: The invention relates to a flexible, penetration resistant article comprising a plurality of fibrous layers including continuous filament yarns, and having an areal density of less than about 4.4 kilograms per square meter. At least one of the plurality of fibrous layers has a fiber with a tenacity of at least about 30 grams per decitex and a continuous filament yarn having a linear density of less than about 1100 decitex.

Abstract: An allergen trap is provided. The allergen trap includes a woven or nonwoven substrate having at least one strata. The trap is impregnated with or otherwise treated with a tacky adhesive by which allergens may be trapped. An example of an allergen is a dust mite. The tacky adhesive, in turn, may be treated with a miticide or activated carbon.

Abstract: The invention relates to an aluminoborosilicate glass devoid of alkali, which has the following composition (in wt. % relative to the oxide content): SiO2>58-70; B2O3 0.5-<9; Al2O3 10-25; MgO>8-15; CaO 0-<10; SrO 0-<3; BaO 0-<2; with MgO+CaO+SrO+BaO>8-18; ZnO 0-<2. Said glass is eminently suitable for use as substrate glass, both in display technology and in thin-film photovoltaic technology.

Abstract: A glass composition for chemical tempering includes oxides in wt % ranges of: SiO2 60 to 75; Al2O3 18 to 28; Li2O 3 to 9; Na2O 0 to 3; K2O 0 to 0.5; CaO 0 to 3; MgO 0 to 3; ZrO2 0 to 3; where MgO+CaO is 0 to 6 wt %; Al2O3+ZrO2 is 18 to 28 wt %, and Na2O+K2O is 0.05 to 3.00 wt %. The glass has a log 10 viscosity temperature in the temperature range of 1328° F. (720° C.) to 1499° F. (815° C.); a liquidus temperature in the temperature range of 2437° F. (1336° C.) to 2575° F. (1413° C.), and a log 7.6 softening point temperature in the temperature range of 1544° F. (840° C.) to 1724° F. (940° C.). The chemically tempered glass has, among other properties, an abraded modulus of rupture of 72 to 78 KPSI, and a modulus of rupture of 76 to 112 KPSI.

Abstract: An optical glass that contains Si, Al, Mg, and O is provided. The optical glass contains Si in an amount of 40% or more and 60% or less, in cation percent, Al in an amount of 10% or more and 35% or less, in cation percent, and Mg in an amount of 20% or more and 35% or less, in cation percent. In the optical glass, the total amount of Si, Al, and Mg is 99.5% or more, in cation percent. Furthermore, the optical glass contains Fe and Na each in an amount of 0.01 wtppm or less and has a transmittance to a light having a wavelength of 248 nm of 40% or more at a thickness of 5 mm.

Abstract: A recrystallized silicon carbide body is provided that has a resistivity of not less than about 1E5 ? cm and a nitrogen content comprising nitrogen atoms bonded within the body, wherein the nitrogen content is not greater than about 200 ppm.

Abstract: 0.5 to 30 parts by weight of a hexagonal celsian powder is added to 100 parts by weight of a ceramic raw material powder to give a mixture. The mixture is sintered to give a ceramic porcelain so as to precipitate monoclinic celsian in the ceramic porcelain.

Abstract: A dielectric ceramic composition that is used for a monolithic ceramic capacitor, can be cofired with internal electrodes mainly composed of Ni at a temperature of 1200° C. or less, and has a high resistivity is provided. The dielectric ceramic composition is mainly composed of a tungsten bronze type complex oxide having a composition formula of (K1-xNax)Sr2Nb5O15 (wherein 0?x<0.2) and further contains, as accessory components, 0.05 to 20 molar parts of R (wherein R is at least one selected from the group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu) and 0.05 to 40 molar parts of M (wherein M is at least one selected from the group consisting of Mn, V, Li, Si, Ni, Cr, Co, Fe, Zn, Mg, and Zr) per 100 molar parts of the main component.

Abstract: Multilayer ceramic chip capacitors which satisfy X8R requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel and nickel alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers comprise a barium titanate base material doped with other metal oxides such as BaO, Y2O3, ZrO2, SiO2, MgO, MnO, MoO3, CaO, Lu2O3, Yb2O3, or WO3 in various combinations.