Semiconductor device and method of protecting passivation layer in a solder bump process
A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.
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The present non-provisional patent application claims the benefit of priority of provisional application Ser. No. 60/871,410, entitled “Method of Protecting Passivation Surface in Solder Bumping Process,” filed on Dec. 21, 2006.
FIELD OF THE INVENTIONThe present invention relates in general to semiconductor devices and, more particularly, to formation of solder bump structures on semiconductor devices.
BACKGROUND OF THE INVENTIONSemiconductor devices are found in many products used in modern society. Semiconductors find applications in consumer items such as entertainment, communications, networks, computers, and household items markets. In the industrial or commercial market, semiconductors are found in military, aviation, automotive, industrial controllers, and office equipment.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level packages (WLP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.
The reliability and integrity of the interconnect structure is important to testing, manufacturing yield, and longevity of the product while in service. In some devices, a problem of cracking has been detected in the passivation layer surrounding the solder bump after solder reflow. The cracking has been attributed to degradation of the passivation layer caused by the chemical processes used during formation of the solder bumps. The cracking problem is especially noted during formation and removal of dry film used to create the solder bumps.
A need exists for a solder bump structure with enhanced strength and reliability.
SUMMARY OF THE INVENTIONIn one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a plurality of active devices formed thereon, forming a contact pad on the substrate in electrical contact with the plurality of active devices, disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad, forming a passivation layer over the substrate and intermediate conduction layer, forming an adhesive layer substantially covering the passivation layer, forming a barrier layer over the adhesive layer, forming a wetting layer over the barrier layer, and removing the barrier layer and wetting layer in a first region, while maintaining the barrier layer, wetting layer, and adhesive layer in a second region. The adhesive layer over the passivation layer in the first region is also maintained at this stage of the process. The method further includes the steps of patterning a dry film over the adhesive layer in the first region, depositing solder material over the wetting layer, barrier layer, and adhesive layer in the second region in areas between the dry film, reflowing the solder material to form solder bumps, and removing the dry film. The adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the solder bumps.
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a plurality of active devices formed thereon, forming a contact pad on the substrate in electrical contact with the plurality of active devices, forming a passivation layer over the substrate, forming an adhesive layer over the passivation layer, forming a wetting layer over the adhesive layer, and removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region. The adhesive layer over the passivation layer in the first region is also maintained during this stage of the process. The method further includes the steps of patterning a dry film over the adhesive layer in the first region, depositing solder material over the wetting layer and adhesive layer in the second region in areas between the dry film, reflowing the solder material to form solder bumps, and removing the dry film. The adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the solder bumps
In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a substrate having a plurality of active devices formed thereon, forming a contact pad on the substrate in electrical contact with the plurality of active devices, forming a passivation layer over the substrate, forming an adhesive layer over the passivation layer, forming a wetting layer over the adhesive layer, and removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region. The adhesive layer over the passivation layer in the first region is also maintained at this stage of the process. The method further includes the steps of depositing solder material over the wetting layer and adhesive layer in the second region, and reflowing the solder material to form solder bumps. The adhesive layer over the passivation layer reduces cracking in the passivation layer during formation of the solder bumps.
In another embodiment, the present invention is a semiconductor device comprising a substrate having a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate. An adhesive layer is formed over the passivation layer. A wetting layer is formed over the adhesive layer. A plurality of solder bumps is formed over the wetting layer and adhesive layer. The adhesive layer remains over the passivation layer until the solder bumps are formed to reduce cracking in the passivation layer.
The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.
A semiconductor wafer generally includes an active front side surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active front side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Patterning involves use of photolithography to mask areas of the surface and etch away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation. The active surface is substantially planar and uniform with electrical interconnects, such as bond pads.
Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip style semiconductor device 10 involves mounting an active area 12 of die 14 facedown toward a chip carrier substrate or printed circuit board (PCB) 16, as shown in
A first redistribution layer (RDL) 40 is formed over first passivation layer 36, as shown in
A second passivation layer 44 is formed over first passivation layer 36 and RDLs 40 and 42. The second passivation layer is thicker than RDLs 40 and 42. In one embodiment, passivation layer 44 is about 5-15 μm in thickness and RDL 40 is about 1-3 μm in thickness. Passivation layer 44 can be made using similar material as described for passivation layer 36. In another embodiment, passivation layers 36 and 44 are formed by repassivation. A portion of second passivation layer 44 is removed by a photoresist mask defined etching process for the first and second solder bumps in areas 48 and 50 or the second passivation layer is photosensitive and can be patterned directly.
An adhesive layer 46 is formed on passivation layer 44 and RDLs 40 and 42. In one embodiment, adhesive layer 46 is about 200-2000 angstroms in thickness. Adhesive layer 46 can be titanium (Ti), Al, titanium tungsten (TiW), and chromium (Cr). Adhesive layer 46 is patterned to follow the contour of passivation layer 44 and RDLs 40 and 42. Accordingly, the formation of adhesive layer 46 is depressed in solder bump areas 48 and 50 and covers substantially the entire surface of passivation layer 44, particularly in and around areas 48 and 50, as seen in
In
In
In
It is important to note that during the solder bump formation process, the adhesive layer 46 in the region outside the UBM structure remains in place. The previous step of removing the portion of wetting layer 54 and barrier layer 52 in the region outside the UBM structure did not involve adhesive layer 46. The adhesive layer 46 in the region outside the UBM structure remains in place and protects passivation layer 44 against chemical degradation during the formation of the solder bumps, in particular during deposition and remove of dry film layer 60. The adhesive layer over the passivation layer reduces cracking of the passivation layer 44 without incurring additional manufacturing costs.
In
In another embodiment, semiconductor device 10 can be made with a direct contact between the solder bump and the contact pad, i.e., without RDLs or other conductive routing structure. In this case, contact pad 32 is formed directly under the UBM structure. A similar process, as described in
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Claims
1. A method of making a semiconductor device, comprising:
- providing a substrate having a plurality of active devices formed thereon;
- forming a contact pad on the substrate in electrical contact with the plurality of active devices;
- disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad;
- forming a passivation layer over the substrate and intermediate conduction layer;
- forming an adhesive layer substantially covering over the passivation layer;
- forming a barrier layer over the adhesive layer;
- forming a wetting layer over the barrier layer;
- removing the barrier layer and wetting layer in a first region while maintaining the barrier layer, wetting layer, and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;
- patterning a dry film over the adhesive layer in the first region;
- depositing bump material over the wetting layer, barrier layer, and adhesive layer in the second region in areas between the dry film;
- reflowing the bump material to form interconnect bumps, wherein the adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps; and
- removing the dry film.
2. The method of claim 1, further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.
3. The method of claim 1, wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.
4. The method of claim 1, wherein the adhesive layer follows a contour of the passivation layer.
5. The method of claim 1, wherein the adhesive layer is made with a material selected from the group consisting of titanium, aluminum, titanium tungsten, and chromium.
6. A method of making a semiconductor device, comprising:
- providing a substrate having a plurality of active devices formed thereon;
- forming a contact pad on the substrate in electrical contact with the plurality of active devices;
- forming a passivation layer over the substrate;
- forming an adhesive layer over the passivation layer;
- forming a wetting layer over the adhesive layer;
- removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;
- patterning a dry film over the adhesive layer in the first region;
- depositing bump material over the wetting layer and adhesive layer in the second region in areas between the dry film;
- reflowing the bump material to form interconnect bumps, wherein the adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps; and
- removing the dry film.
7. The method of claim 6, further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.
8. The method of claim 6, further including disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad.
9. The method of claim 6, further including forming a barrier layer between the adhesive layer and the wetting layer.
10. The method of claim 6, wherein the wetting layer and adhesive layer constitute an under bump metallization structure.
11. The method of claim 6, wherein the adhesive layer follows a contour of the passivation layer.
12. A method of making a semiconductor device, comprising:
- providing a substrate having a plurality of active devices formed thereon;
- forming a contact pad on the substrate in electrical contact with the plurality of active devices;
- forming a passivation layer over the substrate;
- forming an adhesive layer over the passivation layer;
- forming a wetting layer over the adhesive layer;
- removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;
- depositing bump material over the wetting layer and adhesive layer in the second region; and
- reflowing the bump material to form interconnect bumps, wherein the adhesive layer over the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps.
13. The method of claim 12, further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.
14. The method of claim 12, further including disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad.
15. The method of claim 12, further including forming a barrier layer between the adhesive layer and the wetting layer.
16. The method of claim 12, further including:
- patterning a dry film over the adhesive layer in the first region prior to the step of depositing solder material over the wetting layer and adhesive layer in the second region; and
- removing the dry film after the step of depositing solder material over the wetting layer and adhesive layer in the second region.
17. The method of claim 12, wherein the wetting layer and adhesive layer constitute an under bump metallization structure.
18. The method of claim 12, wherein the adhesive layer follows a contour of the passivation layer.
19. The method of claim 12, wherein the adhesive layer is made with a material selected from the group consisting of titanium, aluminum, titanium tungsten, and chromium.
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20020180064 | December 5, 2002 | Hwan et al. |
20040188378 | September 30, 2004 | Wu et al. |
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Type: Grant
Filed: Nov 1, 2007
Date of Patent: Jun 1, 2010
Patent Publication Number: 20080150161
Assignee: STATS ChipPAC, Ltd. (Singapore)
Inventors: Yaojian Lin (Singapore), Haijing Cao (Singapore), Qing Zhang (Singapore)
Primary Examiner: Bradley K Smith
Attorney: Robert D. Atkins
Application Number: 11/934,009
International Classification: H01L 21/44 (20060101);