Abstract: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

Abstract: During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or porous structure may be anodized aluminum oxide or another material. A gate region may be provided one end or both ends of the porous structure. The gate electrode may be formed and extend into the porous structure.

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract: Disclosed is a method of forming a transistor in an integrated circuit structure that begins by forming a collector in a substrate and an intrinsic base above the collector. Then, the invention patterns an emitter pedestal for the lower portion of the emitter on the substrate above the intrinsic base. Before actually forming the emitter or associates spacer, the invention forms an extrinsic base in regions of the substrate not protected by the emitter pedestal. After this, the invention removes the emitter pedestal and eventually forms the emitter where the emitter pedestal was positioned.

Abstract: A diode structure fabrication method. In a P? substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corres

Abstract: A method of forming an insulating layer and a method of manufacturing a semiconductor device using insulating layer are disclosed. A preliminary insulating layer including a material having a relatively low dielectric constant is formed on an object. An upper portion of the preliminary insulating layer is provided with an ozone gas to transform the preliminary insulating layer into an insulating layer having an upper insulating film including an oxide and a lower insulating film including the material having the relatively low dielectric constant. The upper insulating film may further be located on the lower insulating film.

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Abstract: A method of bonding aluminum (Al) electrodes formed on two semiconductor substrates at a low temperature that does not affect circuits formed on the two semiconductor substrates is provided. The method includes: (a) forming aluminum (Al) electrodes on the two semiconductor substrates, respectively, and depositing a metal alloy that comprises aluminum (Al) and copper (Cu) onto the aluminum (Al) electrodes; (b) arranging the aluminum (Al) electrodes of the two semiconductor substrates to face with each other; and (c) heating the aluminum (Al) electrodes at a temperature lower than the melting point of the deposited metal alloy, and applying a specific pressure onto the two semiconductor substrates. Accordingly, bonding can be carried out at a temperature lower than the melting point of an Al0.83Cu0.17 alloy without having an effect on circuits formed on two semiconductor substrates, and can be selectively carried out at regions where pressure is applied.

Abstract: A method of making a bonded intermediate substrate includes forming a weak interface in a GaN source substrate by implanting ions into an N-terminated surface of the GaN source substrate, bonding the N-terminated surface of the GaN source substrate to a handle substrate, and exfoliating a thin GaN single crystal layer from the source substrate such that the thin GaN exfoliated single crystal layer remains bonded to the handle substrate and a Ga-terminated surface of the thin GaN single crystal layer is exposed. The method further includes depositing a capping layer directly onto the exposed surface of the thin GaN single crystal layer, and annealing the thin GaN single crystal layer in a nitrogen containing atmosphere after depositing the capping layer. The in-plane strain present in the thin GaN single crystal layer after the annealing is reduced relative to an in-plane strain present in said layer prior to the annealing.

Abstract: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.

Abstract: A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Abstract: A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of the seed layer be removed through an annealing process using H2. A copper wire may then be formed by filling the damascene pattern.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.

Abstract: A modified TDEAT (tetrakisdiethylamino titanium) based MOCVD precursor for deposition of thin amorphous TiN:Si diffusion barrier layers. The TDEAT is doped with 10 at % Si using TDMAS (trisdimethlyaminosilane); the two liquids are found to form a stable solution when mixed together. Deposition occurs via pyrolysis of the vaporised precursor and NH3 on a heated substrate surface. Experimental results show that we have modified the precursor in such a way to reduce gas phase component of the deposition when compared to the unmodified TDEAT-NH3 reaction. Deposition temperatures were the range of 250-450° C. and under a range of process conditions the modified precursor shows improvements in coating conformality, a reduction in resistivity and an amorphous structure, as shown by TEM and XRD analysis. SIMS and scanning AES have shown that the film is essentially stoichiometric in Ti:N ratio and contains low levels of C (˜0.4 at %) and trace levels of incorporated Si (0.01<Si<0.5 at %).

Abstract: The invention relates to a method for depositing at least one semiconductor layer on at least one substrate in a processing chamber (2). Said semiconductor layer is composed of several components which are evaporated by non-continuously injecting a liquid starting material (3) or a starting material (3) dissolved in a liquid into a tempered evaporation chamber (4) with the aid of one respective injector unit (5) while said vapor is fed to the processing chamber by means of a carrier gas (7). The inventive method is characterized in that the mass flow rate parameters, such as the preliminary injection pressure, the injection frequency, the pulse/pause ratio, and the phase relation between the pulses/pauses and the pulses/pauses of the other injector unit(s), which determine the progress of the mass flow rate of a first silicon-containing starting material and a germanium-containing second starting material (3) through the associated injector unit (5), are individually adjusted or varied.

Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, the method for implanting ions into a substrate by a plasma immersion ion implantation process includes providing a substrate into a processing chamber, supplying a gas mixture including a reacting gas and a reducing gas into the chamber, and implanting ions from the gas mixture into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a hydrogen containing reducing gas into the chamber, and implanting ions from the gas mixture into the substrate.

Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate and forming a memory cell at a surface of the semiconductor substrate. The step of forming the memory cell includes forming a gate dielectric on the semiconductor substrate and a control gate on the gate dielectric; forming a first and a second tunneling layer on a source side and a drain side of the memory cell, respectively; tilt implanting a lightly doped source region underlying the first tunneling layer, wherein the tilt implanting tilts only from the source side to the drain side, and wherein a portion of the semiconductor substrate under the second tunneling layer is free from the tilt implanting; forming a storage on a horizontal portion of the second tunneling layer; and forming a source region and a drain region in the semiconductor substrate.

Abstract: In a method of manufacturing a semiconductor device, a conductive layer pattern may be formed on a substrate. An oxide layer may be formed on the substrate to cover the conductive layer pattern. A diffusion barrier layer may be formed by treating the oxide layer to increase an energy required for a diffusion of impurities. An impurity region may be formed on the substrate by implanting impurities into the conductive layer pattern and a portion of the substrate adjacent to the conductive layer pattern, through the diffusion barrier. The impurities in the conductive layer pattern and the impurity region may be prevented or reduced from diffusing, and therefore, the semiconductor device may have improved performance.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a first insulating material over the semiconductor wafer, and forming a plurality of first features and a plurality of second features in the first insulating material. The plurality of first features is removed, leaving an unfilled pattern in the first insulating material. The unfilled pattern in the first insulating material is filled with a second insulating material.

Abstract: In accordance with an embodiment of the invention the method of manufacturing a semiconductor device is capable of forming a semiconductor substrate having an embossing structure. The method includes forming a layer having a plurality of hemispherical single crystal silicon elements, and forming one or more carbon nano tubes between adjacent hemispherical single crystal silicon elements, thereby, increasing a length of an effective channel of a transistor.

Abstract: Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.

Abstract: A fabricating method of a flat panel display device can reduce manufacturing costs of the flat panel display device. A fabricating method of a flat panel display device includes providing a conductive nanopowder thin film material having a first conductive nanopowder and a second conductive nanopowder, spreading the conductive nanopowder thin film material over a substrate, forming a conductive thin film pattern by patterning the conductive nanopowder thin film material, and forming a conductive thin film by baking the conductive thin film pattern, wherein the first conductive nanopowder is located in a middle of the conductive thin film and the second conductive nanopowder is located in an outer part of the conductive thin film.

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract: An improved apparatus for semiconductor wafer bumping utilizes the injection molded solder process and is designed for high volume manufacturing. The apparatus includes equipment for filling patterned mold cavities on a mold structure with solder, equipment for positioning and aligning a patterned surface of a semiconductor structure directly opposite to the solder filled patterned mold cavities of the mold structure, a fixture tool for holding and transferring the aligned mold and semiconductor structures together, and equipment for receiving the fixture tool and transferring the solder from the aligned patterned mold cavities to the aligned patterned semiconductor first surface. The solder transfer equipment include a wafer heater stack configured to heat the semiconductor structure and a mold heater stack configured to heat the mold structure to a process temperature slightly above the solder's melting point.

Abstract: A method for adding an additional layer to an integrated circuit, the method including providing an integrated circuit having an interconnect layer, depositing, over substantially all of an exposed surface of the integrated circuit, an additional layer of material whose conductivity can be altered, and selectively altering the conductivity of a first portion of the additional layer by selective annealing, to produce a sub-circuit in the additional layer, the sub-circuit being in operative electrical communication with the integrated circuit. Related apparatus and methods are also described.

Abstract: In a first aspect, a first method of manufacturing a dielectric material with a reduced dielectric constant is provided. The first method includes the steps of (1) forming a dielectric material layer including a trench on a substrate; and (2) forming a cladding region in the dielectric material layer by forming a plurality of air gaps in the dielectric material layer along at least one of a sidewall and a bottom of the trench so as to reduce an effective dielectric constant of the dielectric material. Numerous other aspects are provided.

Abstract: Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug.

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).

Abstract: In one embodiment, a method for depositing materials on a substrate is provided which includes forming a titanium nitride barrier layer on the substrate by sequentially exposing the substrate to a titanium precursor containing a titanium organic compound and a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. In another embodiment, the method includes exposing the substrate to the deposition gas containing the titanium organic compound to form a titanium-containing layer on the substrate, and exposing the titanium-containing layer disposed on the substrate to a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. The method further provides depositing a conductive material containing tungsten or copper over the substrate during a vapor deposition process. In some examples, the titanium organic compound may contain methylamido or ethylamido, such as tetrakis(dimethylamido)titanium, tetrakis(diethylamido)titanium, or derivatives thereof.

Abstract: A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage.

Abstract: Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer.

Abstract: A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

Abstract: In some embodiments, a workpiece-surface-influencing device preferentially contacts the top surface of the workpiece, to chemically modify the surface at desired field areas of the workpiece without affecting the surfaces of cavities or recesses in the field areas. The device includes a substance which is chemically reactive with material forming the workpiece surface. The substance can be in the form of a thin film or coating which contacts the surface of the workpiece to chemically modify that surface. The workpiece-surface-influencing device can be in the form of a solid state applicator such as a roller or a semi-permeable membrane. In some other embodiments, the cavities are filled with material that prevents surface modification of the cavity surfaces while allowing modification of the field areas, or which encourages surface modification of the cavity surfaces while preventing modification of the field areas. The modified surface facilitates selective deposition of materials on the workpiece.

Abstract: The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6.

Abstract: The present invention provides a method of fabricating a semiconductor device, which could advance the commercialization of semiconductor devices with a copper interconnect. In a process of metal interconnect line fabrication, a TiN thin film combined with an Al intermediate layer is used as a diffusion barrier on trench or via walls. For the formation, Al is deposited on the TiN thin film followed by copper filling the trench. Al diffuses to TiN layer and reacts with oxygen or nitrogen, which will stuff grain boundaries efficiently, thereby blocking the diffusion of copper successfully.

Abstract: The invention is directed to a chemical mechanical polishing process. The chemical mechanical polishing process comprises steps of providing a wafer disposed at a wafer handling region of a chemical mechanical polishing apparatus and then moving the wafer into a buffer region of the chemical mechanical polishing apparatus. A first detecting process is performed for obtaining a pre-polishing condition of the wafer by using a detector in the buffer region and the wafer is moved into a chemical mechanical polishing region and performing a chemical mechanical process. A second detecting process is performed, in the buffer region, for obtaining a post-polishing condition of the wafer by using the detector of the buffer region.

Abstract: A semiconductor having a leadframe is disclosed. In one embodiment, a leadframe is disclosed to be fitted with a semiconductor chip and is to be encapsulated with a plastic compound has a metallic single-piece base body, to which an interlayer is applied. The interlayer has a surface including a matrix of islands of remaining material of substantially uniform height, with voids extending between said islands.

Abstract: It is an object of the present invention to provide a method for manufacturing a substrate having film patterns such as an insulating film, a semiconductor film, and a conductive film in simple processes. It is another object of the invention to provide a method for manufacturing a semiconductor device with high throughput and high yield at low cost.

Abstract: A method for forming a semiconductor device includes forming an etch target layer, forming a sacrificial hard mask layer having a metal layer and a carbon-based material layer on the etch target layer, forming a photoresist pattern on the carbon-based material layer, etching the carbon-based material layer by the photoresist pattern until a remaining carbon-based material portion has a predetermined thickness, etching the remaining carbon-based material portion until a corresponding metal layer portion is exposed to form a carbon-based material pattern, and etching the metal layer by using the carbon-based material pattern to form a hard mask pattern for forming the pattern.

Abstract: A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

Abstract: A method for manufacturing a shallow trench isolation (STI) structure is provided. In the method, a substrate is initially provided. Then, a patterned pad layer and a patterned mask layer are successively formed in order on the substrate. After that, a portion of the substrate is removed by using the patterned mask layer and the patterned pad layer as a mask to form trenches in the substrate. Next, a first insulation layer is formed in the trenches. Afterwards, a protection layer is conformally formed on the substrate. Then, a second insulation layer is formed on the protection layer above the first insulation layer. Next, the patterned mask layer and the patterned pad layer are removed. Finally, a portion of the protection layer and the second insulation layer are removed.

Abstract: A method of fabricating a semiconductor device includes depositing a first film on a workpiece film so that a resist is formed on the first film, processing the first film with the resist serving as a mask, depositing a second film along the first film, processing the second film so that the second film is left only on a sidewall of the first film, depositing a third film on the substrate, exposing a sidewall of the second film, depositing a fourth film along the sidewall and an upper surface of the third film, removing the fourth film except for only its part on the sidewall of the second film, depositing a fifth film on the substrate, planarizing the second to fifth films so that the upper surfaces of the films are exposed, and processing the workpiece film while the second and fifth films serve as a mask.