Abstract: Described is a process for forming an LED structure using a laser lift-off process to remove the growth substrate (e.g., sapphire) after the LED die is bonded to a submount. The underside of the LED die has formed on it anode and cathode electrodes that are substantially in the same plane, where the electrodes cover at least 85% of the back surface of the LED structure. The submount has a corresponding layout of anode and cathode electrodes substantially in the same plane. The LED die electrodes and submount electrodes are ultrasonically welded together such that virtually the entire surface of the LED die is supported by the electrodes and submount. Other bonding techniques may also be used. No underfill is used. The growth substrate, forming the top of the LED structure, is then removed from the LED layers using a laser lift-off process.

Abstract: The embodiment discloses a semiconductor light emitting device. The semiconductor light emitting device includes a first conductive semiconductor layer; a first electrode layer below the first conductive semiconductor layer; a semiconductor layer at an outer peripheral portion of the first conductive semiconductor layer; an active layer on the first conductive semiconductor layer; a second conductive semiconductor layer on the active layer; and a second electrode layer on the second conductive semiconductor layer.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure including a plurality of compound semiconductor layers, a second electrode layer below the light emitting structure, a channel layer between the light emitting structure and an edge area of the second electrode layer, a buffer layer on the channel layer, and a passivation layer on the buffer layer.

Abstract: Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a first conductive semiconductor layer including a first carrier blocking layer of semiconductor material; an active layer below the first conductive semiconductor layer; and a second conductive semiconductor layer below the active layer.

Abstract: This disclosure relates to devices and methods relating to coupled first and second device portions.

Abstract: A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Abstract: A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells.

Abstract: A field effect transistor includes a first nitride semiconductor layer 13 and a second nitride semiconductor layer 14 having a band gap larger than that of the first nitride semiconductor layer 13 which are formed in this order in an upward direction on a conductive substrate 11, a source electrode 15 and a drain electrode 16 which are electrically connected to a two-dimensional electron gas layer 21, and a gate electrode 18. A rise voltage of a drain-substrate current is lower than a rise voltage of a drain-gate current and a rise voltage of a drain-source current.

Abstract: According to a method for fabricating a semiconductor device, a first semiconductor layer made of a first nitride semiconductor is formed over a substrate. Thereafter, a mask film covering part of the upper surface of the first semiconductor layer is selectively formed on the first semiconductor layer. A multilayer film, in which second and third nitride semiconductors having different band gaps are stacked, is selectively formed on the first semiconductor layer with the mask film used as a formation mask. On the multilayer film, an ohmic electrode is formed.

Abstract: A gallium nitride based semiconductor diode includes a substrate, a GaN layer formed on the substrate, an AlGaN layer formed on the GaN layer where the GaN layer and the AlGaN layer forms a cathode region of the diode, a metal layer formed on the AlGaN layer forming a Schottky junction therewith where the metal layer forms an anode electrode of the diode, and a high barrier region formed in the top surface of the AlGaN layer and positioned under an edge of the metal layer. The high barrier region has a higher bandgap energy than the AlGaN layer or being more resistive than the AlGaN layer.

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: A semiconductor integrated circuit includes a group of wirings routed at first to Nth (N being an integer not less than two) wiring positions sequentially arranged in parallel, each of the wirings being divided into two portions comprising a starting end side and a terminating end side; and an Mth buffer circuit that connects the starting end side of the wiring at the Mth wiring position (M being an integer that satisfies 1?M?K, wherein K is an integer that satisfies K?N/2) as an input and the terminating end side of the wiring at the (M+N?K)th wiring position as an output. The group of the wirings has a structure in which connection is switched so that the starting end side of the wiring at a Jth (J being an integer that satisfies K<J?N) wiring position is routed to the terminating end side of the wiring at a (J?K)th wiring position on a wiring layer above a placement region of the buffer circuit(s). Chip occupying area of the group of wirings and the buffer circuit is reduced.

Abstract: In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.

Abstract: The invention provides a method for forming a sodium ion selective electrode, including: (a) providing a conductive substrate; (b) forming a conductive wire which extends from the conductive substrate for external contact; and (c) forming a sodium ion sensing film on the conductive substrate, wherein the method for forming the conductive substrate includes: providing a substrate; and forming a conductive layer on the substrate.

Abstract: In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.

Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

Abstract: The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.

Abstract: A semiconductor transistor device is provided. The transistor device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The source region has a stress-inducing semiconductor material located therein, while the drain region is free of any stress-inducing semiconductor material. This asymmetric arrangement of stress-inducing elements results in relatively high source-body leakage, and relatively low drain-body leakage, which is beneficial in analog circuit applications.

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract: A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.

Abstract: A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film.

Abstract: A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

Abstract: A circuit and method for implementing variable threshold voltage transistors in a complementary metal oxide semiconductor (CMOS) semiconductor chip, and a design structure on which the subject circuit resides are provided. Variable threshold voltage transistors are provided utilizing the NWELL and PWELL proximity effects of the CMOS semiconductor chip without any additional mask steps. A distance between an adjacent field effect transistor (FET) and an NWELL edge or PWELL edge is adjusted to selectively provide a needed threshold voltage for the FET.

Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.

Abstract: A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other.

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract: A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell. The memory cell includes a first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film. The floating gate includes a first semiconductor film which contacts the first gate insulating film, and a metal film stacked on the semiconductor film. An effective tunneling thickness between the semiconductor substrate and the floating gate in a read operation is thicker than an effective tunneling thickness between the semiconductor substrate and the floating in a write operation.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

Abstract: A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: A non-volatile semiconductor memory device capable of more efficiently trapping charges in a charge storage layer without increasing the thickness of the charge storage layer, as well as a manufacturing method thereof. In the non-volatile semiconductor memory device a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode are disposed successively between a first source/drain region and a second source/drain region above a semiconductor substrate. The charge storage layer has a first layer and second layers, the first layer has a first nitrogen atom concentration, each of the second layers has a second nitrogen atom concentration, higher than the first nitrogen atom concentration and faces one of the tunnel insulating film and the block insulator.

Abstract: A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2<DEOT<Dk??(1) Dsio2 denotes a thickness of the dielectric when the dielectric is composed of silicon oxide with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers. Dk denotes such an equivalent oxide thickness of a first dielectric that provides the resistance value Rsio2. The resistance value Rsio2 being defined as a resistance value of the first semiconductor layer for each of the first conductive layers when the dielectric is composed of silicon oxide and has a film thickness of Dsio2.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells.

Abstract: A semiconductor device includes a main gate formed on a semiconductor substrate and a source region and a drain region formed in a surface of the semiconductor substrate on opposite sides of the main gate. An internal gate formed within a portion of the main gate that adjoins the source region.

Abstract: In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.

Abstract: The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

Abstract: It is intended to solve a problem of increase in power consumption and reduction in operating speed due to an increase in parasitic capacitance of a surrounding gate transistor (SGT) as a three-dimensional semiconductor device, to provide an SGT achieving an increase in speed and power consumption reduction in a semiconductor circuit. The semiconductor device comprises a second-conductive type impurity region (510) formed in a part of a first-conductive type semiconductor substrate (100), a first silicon pillar (810) of an arbitrary cross-sectional shape formed on the second-conductive type impurity region, a first insulating body (310) surrounding a part of a surface of the first silicon pillar, a gate (210) surrounding the first insulating body, and a second silicon pillar (820) which is formed on the first silicon pillar and which includes a second-conductive type impurity region (540).

Abstract: It is intended to provide a semiconductor device comprising a circuit which has a connection between one of a drain region and a source region of a first MOS transistor and one of a drain region and a source region of a second MOS transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate includes a pillar portion extending from a main surface of the semiconductor substrate. The first insulating film covers a side surface of the pillar portion. The second insulating film covers the main surface of the semiconductor substrate. The second insulating film is thicker than the first insulating film. The conductive layer extends along the first insulating film.

Abstract: A Semiconductor device includes a substrate having an active region defined by a device isolation layer, a trench formed by etching the active region and the device isolation layer, a buried gate filling a portion of the trench, an interlayer insulation layer formed over the buried gate and filling a remainder of the trench, and an oxidation protecting layer formed between the buried gate and the device isolation layer.

Abstract: A semiconductor device comprises a recessed trench in a substrate, a gate insulating layer including a first portion and a second portion, the first portion having a first thickness and covering lower portions of sidewalls of the recessed trench and a bottom surface of the recessed trench, and the second portion having a second thickness and covering upper portions of the sidewalls of the recessed trench, the second thickness being greater than the first thickness, a gate electrode filling the recessed trench, a first impurity region having a first concentration and disposed at opposing sides of the gate electrode, and a second impurity region having a second concentration greater than the first concentration and disposed on the first impurity region to correspond to the second portion of the gate insulating layer.

Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.

Abstract: A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array.