Abstract: In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH3 gas is fed onto the nucleation layer. This turns the surface of the nucleation layer into a group-V element and then forms a group-III-V compound layer of AlN. Then, a mixed gas of TMAl gas and NH3 gas is fed onto the group-III-V compound layer so as to form another group-III-V compound layer. Finally, a group-III nitride semiconductor layer is crystal-grown on the group-III compound layer.

Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.

Abstract: One or more embodiments relate to a method for making a semiconductor structure, the method including: forming a first conductive interconnect at least partially through the substrate; and forming a second conductive interconnect over the substrate, wherein the first conductive interconnect and the second conductive interconnect are formed at least partially simultaneously.

Abstract: Embodiments of semiconductor devices are provided. In one embodiment, the semiconductor device includes a substrate, an etch stop layer formed on the substrate, an adhesion promotion layer formed directly on the etch stop layer, and a dielectric layer formed directly on the adhesion promotion layer. The etch stop layer may include silicon, carbon, and nitrogen. The dielectric layer may include silicon, oxygen, and carbon. The adhesion promotion layer may include carbon, oxygen, and nitrogen. An example of an adhesion promotion layer includes polyimide.

Abstract: This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.

Abstract: An optoelectronic component including a connection carrier comprising a structured carrier strip in which interspaces are filled with an electrically insulating material and an optoelectronic semiconductor chip attached and electrically connected to a top portion of the connection carrier, wherein the electrically insulating material terminates substantially flush with the carrier strip in places or the carrier strip projects beyond the electrically insulating material, and the carrier strip is not covered by the electrically insulating material on the top portion and/or on a bottom portion of the connection carrier.

Abstract: The present invention relates to a chip card and a method for the production of a chip card having a chip (21) which is arranged in a card body, and having a plurality of components (18, 19, 22) being electrically conductively connected to the chip by means of a conductor arrangement (20), wherein the card body is composed of a plurality of substrate layers (11, 12, 13) which are arranged in a layer structure, wherein the components and the conductor arrangement are arranged in different substrate layers, specifically a component layer arrangement and a connecting layer arrangement, and have contact surfaces (23, 24, 25, 26, 31, 32, 33, 34), which are disposed so as to overlap one another, for producing an electrically conductive contacting.

Abstract: An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

Abstract: The invention relates to a semiconductor device having an integrated circuit die and a housing. The housing includes a base surface and at least one lateral surface which extends across to the base surface. In particular, this semiconductor device can be an electronic chip card, such as a universal integrated circuit card (UICC). The semiconductor device includes at least one electrical contact for electrically connecting the integrated circuit die with an abutting counter contact of a connecting device. The electrical contact has first and second mating sections, which are arranged on the base surface and lateral surface, respectively, and are connected to each other through a bent section.

Abstract: A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells. Each of the plurality of RF transistor cells includes a control terminal and an output terminal. The RF transistor device further includes an RF input lead, and an input matching network coupled between the RF input lead and the RF transistor die. The input matching network includes a plurality of capacitors having respective input terminals. The input terminals of the capacitors are coupled to the control terminals of respective ones of the RF transistor cells.

Abstract: A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region.

Abstract: This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a switching between the first I/O pad and the second I/O pad is implemented by wire bonding.

Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.

Abstract: There is provided a substrate with a built-in semiconductor element, including: a first substrate at which a wiring layer is layered on a dielectric layer; a semiconductor element that is structured to include a distributed constant circuit, and at which plural bonding pads are formed at a peripheral region of a surface that faces the first substrate, and that is electrically connected to the wiring layer by an electrically-conductive member that has electrical conductivity and corresponds to the plural bonding pads; a supporting member that is disposed at an inner side region that is further toward an inner side than the peripheral region of the semiconductor element, and that is interposed between the semiconductor element and the first substrate and supports the semiconductor element; and a second substrate that is laminated to the first substrate and the semiconductor element.

Abstract: A silicon compound gas, an oxidizing gas, and a rare gas are supplied into a chamber (2) of a plasma processing apparatus (1). A microwave is supplied into the chamber (2), and a silicon oxide film is formed on a target substrate with plasma generated by the microwave. A partial pressure ratio of the rare gas is 10% or more of a total gas pressure of the silicon compound gas, the oxidizing gas, and the rare gas, and an effective flow ratio of the silicon compound gas and the oxidizing gas (oxidizing gas/silicon compound gas) is not less than 3 but not more than 11.

Abstract: A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.

Abstract: An upper-side semiconductor chip is stacked on a lower-side semiconductor chip by connection through microbumps. In the lower-side semiconductor chip that forms a gap with the upper-side semiconductor chip to be filled with an underfill resin, and is sealed with a molding resin, a polyimide film is formed on the chip surface in a peripheral area excluding openings of bonding pads. A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are provided that the device is capable of suppressing generation of a void in the underfill resin layer, prevents a decrease in measurement accuracy of the gap between the stacked semiconductor chips, and prevents peeling of the molding resin.

Abstract: The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof.

Abstract: Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.

Abstract: In one embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes forming a cured film of an insulation resin on a surface of a first semiconductor chip and flip-chip bonding a second semiconductor via a bump on the first semiconductor chip on which the cured film of the insulation resin is formed. The insulation resin can be cured at temperature range from (A?50)° C. to (A+50)° C., wherein “A” is a solidification point of the bump.

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract: A method for mounting a semiconductor device by mounting a semiconductor chip on a board by flip chip bonding, comprising: contacting an Au bump of the semiconductor chip with a Sn—Bi solder; and heating the Sn—Bi solder at a temperature which is not lower than the melting point thereof and which is not higher than 180° C. for 30 minutes or more.

Abstract: A device mounting board includes an insulating resin layer, a wiring layer provided on one of main surfaces of the insulating resin layer, and bump electrodes connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A semiconductor module is formed by having the bump electrodes connected to a semiconductor device. A recess is provided in the top face of each bump electrode. The recess communicates with an opening provided on a side surface of the bump electrode.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Abstract: A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Abstract: A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads.

Abstract: A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.

Abstract: A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.

Abstract: A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines

Abstract: In sophisticated semiconductor devices, the metal-containing layer stack at the back side of the substrate may be provided so as to obtain superior adhesion to the semiconductor material in order to reduce the probability of creating leakage paths in a bump structure upon separating the substrate into individual semiconductor chips. For this purpose, in some illustrative embodiments, an adhesion layer including a metal and at least one non-metal species may be used, such as titanium oxide, in combination with further metal-containing materials, such as titanium, vanadium and gold.

Abstract: A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.

Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an opening. Then, a larger portion of the photoresist layer is exposed to light and an electrically conductive interconnect is formed in the opening. The larger portion of the photoresist layer that was exposed to light is developed to expose edges of the electrically conductive interconnect and portions of the metallization structure. A protection layer is formed on the top and edges of the electrically conductive interconnect and on the exposed portions of the metallization structure.

Abstract: A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.

Abstract: A method for fabricating an integrated circuit device includes providing a semiconductor substrate having a first region and a second region, e.g., peripheral region. The method forms a stop layer overlying the first and second regions and a low k dielectric layer (e.g., k<2.9) overlying the stop layer in the first and second regions. The method forms a cap layer overlying the low k dielectric layer. In an embodiment, the method initiates formation of a plurality of via structures within a first portion of the low k dielectric layer overlying the first region and simultaneously initiates formation of an isolated via structure for in the second region of the semiconductor substrate, using one or more etching processes. The method includes ceasing formation of the plurality of via structures within the first portion and ceasing formation of the isolated via structure in the second region when one or more portions of stop layer have been exposed.

Abstract: A device has a semiconductor chip, a wiring board, a support which supports the semiconductor chip on the wiring board and forms a gap between the semiconductor chip and the wiring board, and a sealing resin injected into the gap and covering the semiconductor chip.

Abstract: A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.

Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

Abstract: One or more embodiments may relate to a method for making a semiconductor structure, the method including: forming an opening at least partially through a workpiece; and forming an enclosed cavity within the opening, the forming the cavity comprising forming a paste within the opening.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor structure. A first via is formed in the first interconnect layer and in electrical contact with the first conductor structure. The first via has a first oval footprint.

Abstract: The electronic device includes the substrate, the electronic component mounted on a main surface of the substrate, a plurality of external terminals formed on a back surface of the substrate, and a plurality of interconnects formed on the back surface of the substrate, wherein the plurality of interconnects includes a first interconnect disposed so as to overlap with an outer edge of the electronic component in a plan view. A pitch between a first external terminal and a second external terminal, adjacent to each other in one direction with the first interconnect located therebetween, is wider than a pitch between a third external terminal and a fourth external terminal, adjacent to each other in the same direction without the first interconnect located therebetween.

Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.