Abstract: A method for manufacturing an extraordinary magnetoresistive sensor (EMR sensor) having reduced size and increased resolution is described. The sensor includes a plurality of electrically conductive leads contacting a magnetically active layer and also includes an electrically conductive shunt structure. The electrically conductive leads of the sensor and the shunt structure can be formed in a common photolithographic masking and etching process so that they are self aligned with one another. This avoids the need to align multiple photolithographic processing steps, thereby allowing greatly increased resolution and reduced lead spacing. The EMR sensor can be formed with a magnetically active layer that can be close to or at the air bearing surface (ABS) for improved magnetic spacing with an adjacent magnetic medium of a data recording system.

Abstract: In laser annealing using a solid state laser, a focus position of a minor axial direction of a rectangular beam is easily corrected depending on positional variation of a laser irradiated portion of a semiconductor film. By using a minor-axis condenser lens 29 condensing incident light in a minor axial direction and a projection lens 30 projecting light, which comes from the minor-axis condenser lens 29, onto a surface of a semiconductor film 3, laser beam 1 is condensed on the surface of the semiconductor film 3 in the minor axial direction of a rectangular beam. The positional variation of a vertical direction of the semiconductor film 3 in a laser irradiated portion of the semiconductor film 3 is detected by a positional variation detector 31, and the minor-axis condenser lens 29 is moved in an optical axis direction based on a value of the detection.

Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.

Abstract: A manufacturing yield of a semiconductor device (capacitive micromachined ultrasonic transducer) is increased. A plurality of first chips 1 in which a plurality of cells each having functions of transmitting and receiving ultrasonic waves are formed on a front surface of a first semiconductor wafer are manufactured, and each of the first chips 1 is judged as a superior/inferior product, and then, the first semiconductor wafer is sigulated into a plurality of first chips 1. Next, a plurality of second chips 2 in which a wiring layer is formed on a front surface of a second semiconductor wafer are manufactured, and each of the second chips 2 is judged as a superior/inferior product, and then, the second semiconductor wafer is sigulated into a plurality of second chips 2.

Abstract: The present disclosure provides a method for making an integrated circuit. The method comprises processing a first surface of a substrate to create the integrated circuit and grinding a second surface of the substrate to remove material until the substrate is substantially close to a desire thickness. The method also includes performing a wet etch process over the second surface of the substrate and performing a chemical mechanical polishing (CMP) process over the second surface of the substrate to remove a pattern on the substrate. The second surface of the substrate is examined with a metrological instrument to determine if the second surface is substantially smooth; if the second surface is not substantially smooth, the steps of performing the CMP process and examining the second surface with the metrological instrument are repeated until the second surface is substantially smooth.

Abstract: Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts.

Abstract: A method of forming a thermal bend actuator in an inkjet nozzle assembly. The method includes: depositing sidewalls and a roof layer to define a nozzle chamber; defining first and second vias in one sidewall to reveal first and second electrodes; filling the vias with a conductive material using electroless plating to provide first and second connector posts; depositing an active beam material onto the roof layer; etching the active beam material to define a planar active beam member comprising a bent or serpentine beam element; and etching the roof layer to define the thermal bend actuator.

Abstract: A method for producing a multiplicity of optoelectronic components includes providing a semiconductor body carrier including on a first main area a multiplicity of semiconductor bodies, each provided with a contact structure and having an active layer that generates electromagnetic radiation, in a semiconductor layer sequence, and forming a planar filling structure on the first main area such that the planar filling structure at least partly covers regions of the contact structure and the semiconductor body carrier without covering the semiconductor body.

Abstract: Provided are a flip-chip nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising a reflective layer formed on the p-type clad layer and at least one transparent conductive thin film layer made up of transparent conductive materials capable of inhibiting diffusion of materials constituting the reflective layer, interposed between the p-type clad layer and reflective layer; and a process for preparing the same. In accordance with the flip-chip nitride-based light emitting device of the present invention and a process for preparing the same, there are provided advantages such as improved ohmic contact properties with the p-type clad layer, leading to increased wire bonding efficiency and yield upon packaging the light emitting device, capability to improve luminous efficiency and life span of the device due to low specific contact resistance and excellent current-voltage properties.

Abstract: The present invention discloses a method for fabricating a heat-resistant, humidity-resistant oxide-confined vertical-cavity surface-emitting laser (VCSEL) by slowing down the oxidizing rate during a VCSEL oxidation process to thereby reduce stress concentration of an oxidation layer and by preventing moisture invasion using a passivation layer disposed on a laser window. The VCSEL device thus fabricated is heat-resistant, humidity-resistant, and highly reliable. In a preferred embodiment, the oxidation process takes place at an oxidizing rate of less than 0.4 ?m/min, and the passivation layer is a SiON passivation layer.

Abstract: Disclosed is a method of manufacturing a TFT array substrate having a reduced number of mask processes. The method includes sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate, and forming a first resist pattern having three height levels on the second conductive material. The method further includes forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern.

Abstract: A flat panel display, and method of fabricating the same, including a substrate having a display portion and a pad that is arranged on the substrate and is electrically coupled with the display portion. The pad includes a pad electrode arranged on the substrate, a passivation layer arranged on the pad electrode and having only one contact hole that exposes the pad electrode, and a transparent electrode arranged on the passivation layer and the pad electrode. The passivation layer may alternatively have a plurality of contact holes that expose the pad electrode. In this case, the reflective layer pattern is arranged on the passivation layer and the pad electrode, and it exposes portions of the pad electrode in the contact holes. Furthermore, the transparent electrode would be arranged on the reflective layer pattern and the exposed portions of the pad electrode.

Abstract: Methods for fabricating semiconductors with enhanced strain. One embodiment includes fabrication of a semiconductor device with an epitaxial structure. The epitaxial structure is formed with one or more semiconductor layers. One or more of the layers includes a dopant including small quantities of Al and repeated delta doping during expitaxial growth to form periods where surfaces are group III rich.

Abstract: Disclosed is a light emitting device having an isolating insulative layer for isolating light emitting cells from one another and a method of fabricating the same. The light emitting device comprises a substrate and a plurality of light emitting cells formed on the substrate. Each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer positioned on one region of the lower semiconductor layer, and an active layer interposed between the lower and upper semiconductor layers. Furthermore, an isolating insulative layer is filled in regions between the plurality of light emitting cells to isolate the light emitting cells from one another. Further, wirings electrically connect the light emitting cells with one another. Each of the wirings connects the lower semiconductor layer of one light emitting cell and the upper semiconductor layer of another light emitting cell adjacent to the one light emitting cell.

Abstract: Disclosed are electroluminescent materials comprising a homopolymer based on recurring structural units of the formula (I) wherein R9, R9? R9?, R11, R13? R14, R11?, R13?, R14? independently are H or an organic substituent, where at least one of R9, R9? R9?, R11, R13 R14, R11?, R13?, R14? comprises a group R10 of the formula —(Sp)x10-[PG?]< wherein Sp is a divalent organic spacer, PG? is a group derived from a polymerisable group, and x10 is 0 or 1, with substituents and spacer as defined in claim 1. Further disclosed are some novel polymers of this class as well as monomers for their preparation. The homopolymers are advantageously used as a host material in devices further comprising a luminiscent component, which is usually selected from phosphorescent metal complexes and fluorescent dopants.

Abstract: To provide a compact and high performance gyroscope. A gyroscope (10) comprises an outer frame (11); an inner frame (12) positioned inside the outer frame and supported to be movable in one reciprocating direction; a plurality of proof masses (15) positioned inside the inner frame and supported to be movable in the direction orthogonal to the one reciprocating direction; a plurality of outer support suspensions (13) which connect the outer frame and the inner frame; a plurality of inner support suspensions (14) which connect the inner frame and each of the proof masses; actuators (16) for accelerating each of the proof masses; and detectors (17) for detecting displacement of the inner frame against the outer frame. The actuators oscillate the plurality of proof masses in-phase, and wherein Coriolis forces induced on each of the proof masses are summed up in the inner frame.

Abstract: This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N? SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (which is proximal to the device's radioactive source) is only 300 nm to 5 nm thick (as an example). In one example, tritium is used as a fuel source. In other embodiments, radioisotopes (such as Nickel-63, promethium or phosphorus-33) may be used. Low energy beta sources, such as tritium, emit low energy beta-electrons that penetrate very shallow distances (as shallow as 5 nm) in semiconductors, including SiC, and can result in electron-hole pair creation near the surface of a semiconductor device rather than pair creation in a device's depletion region.

Abstract: A strip-shape flexible substrate is transported over a long horizontal distance, with its width extending in the vertical direction, the position of the substrate in the vertical direction is maintained with high precision, and the films are deposited onto its surface. When depositing the thin films to manufacture a thin film laminated body, at least one pair of gripping rollers arranged in at least one space between film deposition chambers, and which grasps an upper-side edge portion of the substrate with its width oriented in the vertical direction, are installed such that the rotation direction of the gripping rollers is diagonally upward, at an angle relative to the direction of transport of the substrate, and by changing the force with which the gripping rollers grasp the substrate, a force lifts the substrate, and the height of the substrate can be controlled.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: There are provided a CMOS image sensor and a method for fabrication thereof. The CMOS image sensor having a reset transistor, a select transistor, a drive transistor and a photodiode, includes an active region in shape of a line, a gate electrode of the drive transistor, which is intersected with the active region, a blocking layer interposed between the active region and the gate electrode in which the blocking layer is formed on an intersection region of the active region and the gate electrode, and a metal contact electrically connected to the gate electrode, wherein the metal contact is not electrically connected to the active region by the blocking layer.

Abstract: It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel.

Abstract: A method for making an optical device with integrated optoelectronic components, including a) making a protective structure including a support in which at least one blind hole is made, an optical element being positioned in the blind hole, b) attaching the support to a substrate including the integrated optoelectronic components, the blind hole forming a cavity in which the optical element faces one of the optoelectronic components, c) achieving thinning of the substrate and making electric connections through the substrate, and d) making an aperture through the bottom wall of the blind hole, uncovering at least one portion of the optical field of the optical element.

Abstract: A method of forming photovoltaic devices and modules that includes an ambient pressure thin film deposition step. The central combination of the photovoltaic device structure includes a back reflector layer, active photovoltaic material and transparent electrode. The central combination is formed on a substrate having an electrical isolation layer deposited thereon. The device structure may further include an overlying protective layer remote from the substrate and a laminate on the backside of the substrate. The individual devices may be interconnected in series via a patterning process to form a monolithically integrated module. Module fabrication is preferably performed in a continuous fashion. One or more steps of module fabrication are performed with a plasma torch. Use of a plasma torch simplifies the manufacturing process by enabling deposition of the electrical isolation and/or protective layers at ambient pressure, including in air.

Abstract: A method for manufacturing a back-illuminated type solid-state imaging device by (a) providing a substrate having, on a front surface side thereof, a semiconductor film on a semiconductor substrate with an insulation film therebetween; (b) forming in the semiconductor substrate a charge accumulation portion of a photoelectric conversion element that constitutes a pixel; (c) forming in the semiconductor film at least some transistors that constitute the pixel; and (d) forming on a rear surface side of the semiconductor substrate a rear surface electrode to which a voltage can be applied.

Abstract: Growing spin-capable multi-walled carbon nanotube (MWCNT) forests in a repeatable fashion will become possible through understanding the critical factors affecting the forest growth. Here we show that the spinning capability depends on the alignment of adjacent MWCNTs in the forest which in turn results from the synergistic combination of a high areal density of MWCNTs and short distance between the MWCNTs. This can be realized by starting with both the proper Fe nanoparticle size and density which strongly depend on the sheet resistance of the catalyst film. Simple measurement of the sheet resistance can allow one to reliably predict the growth of spin-capable forests. The properties of pulled MWCNTs sheets reflect that there is a relationship between their electrical resistance and optical transmittance. Overlaying either 3, 5, or 10 sheets pulled out from a single forest produces much more repeatable characteristics.

Abstract: A copper/indium/gallium/selenium (CIGS) solar cell structure and a method for fabricating the same are provided. The CIGS solar cell structure includes a substrate, a molybdenum thin film layer, an alloy thin film layer, and a CIGS thin film layer. According to the present invention, the alloy thin film layer is provided between the molybdenum thin film layer and the CIGS thin film layer, serving as a conductive layer of the CIGS solar cell structure. The alloy thin film layer is composed of a variety of high electrically conductive materials (such as molybdenum, copper, aluminum, and silver) in different proportions.

Abstract: Back contact solar cells including rear surface structures and methods for making same. The rear surface has small contact areas through at least one dielectric layer, including but not limited to a passivation layer, a nitride layer, a diffusion barrier, and/or a metallization barrier. The dielectric layer is preferably screen printed. Large grid areas overlay the dielectric layer. The methods provide for increasing efficiency by minimizing p-type contact areas and maximizing n-type doped regions on the rear surface of a p-type substrate.

Abstract: A method of fabricating an organic thin film transistor is disclosed, which comprises steps of (S1) forming a gate electrode on a substrate; (S2) forming a gate insulating layer on the gate electrode; (S3) providing a gas on the surface of the gate insulating layer to form hydrophobic molecules on the surface of the gate insulating layer; (S4) forming an organic semiconductor layer, a source electrode, and a drain electrode over the gate insulating layer having hydrophobic molecules thereon, wherein the gas of step (S3) is at least one selected from the group consisting of halogen-substituted hydrocarbon, un-substituted hydrocarbon, and the mixtures thereof. The method of the present invention utilizes gases comprising carbon or fluorine atom to perform surface treatment on the surface of the gate insulating layer, therefore the hydrophobic character of the surface of the gate insulating layer can be enhanced and the electrical properties of the OTFT can be improved.

Abstract: A method for assembling a first semiconductor chip provided with pads on a second semiconductor chip or wafer provided with pads, comprising covering the chip(s) with a dielectric, superposing the two chips, the pads being arranged substantially opposite to each other, and applying a voltage difference between the pads of the first and second chips to cause a breakdown of the dielectric and a diffusion of the conductor forming the pads into the broken down areas, whereby a conductive path forms between the opposite pads.

Abstract: A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections.

Abstract: Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

Abstract: A method of producing a semiconductor device that has a silicon substrate including a first major surface and a second major surface thereof, a front surface device structure being formed in a region of the first major surface, the method has a step of forming a rear electrode in a region of the second major surface, which includes evaporating or sputtering aluminum-silicon onto the second major surface to form an aluminum silicon film as a first layer of the rear electrode, the aluminum silicon film having a silicon concentration of at least 2 percent by weight when the thickness thereof is less than 0.3 ?m.

Abstract: An improved type thin film semiconductor device and a method for forming the same are described. That is, in a thin film semiconductor device such as TFT formed on an insulating substrate, it is possible to prevent the intrusion of a mobile ion from a substrate or other parts, by forming the first blocking film comprising a silicon nitride, an aluminum oxide, an aluminum nitride, a tantalum oxide, and the like, under the semiconductor device through an insulating film used in a buffering, and then, by forming the second blocking film on TFT, and further, by covering TFT with said first and second blocking films.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.

Abstract: A method of manufacturing a thin film transistor substrate includes a first process in which a gate line pattern including a gate line and a gate electrode is formed with a first conductive material on a substrate using a first mask, a second process in which a first insulating layer is formed on the substrate and a data line pattern including a data line, a source electrode, and a drain electrode is formed with a second conductive material using a second mask, and a third process in which a second insulating layer is formed on the substrate and a pixel electrode connected to the drain electrode is formed on the second insulating layer with a third conductive material.

Abstract: In order to form a plurality of semiconductor elements over an insulating surface, in one continuous semiconductor layer, an element region serving as a semiconductor element and an element isolation region having a function to electrically isolate element regions from each other by repetition of PN junctions. The element isolation region is formed by selective addition of an impurity element of at least one or more kinds of oxygen, nitrogen, and carbon and an impurity element that imparts an opposite conductivity type to that of the adjacent element region in order to electrically isolate elements from each other in one continuous semiconductor layer.

Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

Abstract: A semiconductor device manufacturing method may include the following processes. A semiconductor substrate is partially removed using a first insulating film having first and second portions as a mask to form first and second pillars of the semiconductor substrate. A second insulating film is formed on side surfaces of the first and second pillars. A silicon film is formed on the first and second insulating films. A first part of the silicon film, which is on upper surfaces of the first and second portions, is removed. A coating film, which covers the upper surfaces of the first and second portions, is formed over the semiconductor substrate. The coating film is partially removed to expose the first insulating film and a second part of the silicon film. The second part is on side surfaces of the first and second portions. The second part is removed by dry etching.

Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

Abstract: A method for selective formation of trenches is disclosed. First, a substrate is provided. The substrate includes a first semiconductor element and a second semiconductor element. The first semiconductor element has a dopant. Second, a wet etching procedure is carried out to selectively form a pair of trenches in the substrate around the second semiconductor element, a first source/drain ion implantation is selectively carried out on the first semiconductor element, or a second source/drain ion implantation is selectively carried out on the second semiconductor element.

Abstract: A trench is formed so as to reach a p?-type epitaxial layer from an upper surface of a source region. A gate electrode is formed so as to bury the trench. Each of body contact trenches is formed away from the gate electrode. A body contact region is formed at the bottom of the body contact trench. An n-type semiconductor region that is a feature of the present invention is formed in a layer below each body contact region. The impurity concentration of the n-type semiconductor region is higher than a channel forming area and lower than the body contact region.

Abstract: Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge blocking layer is formed over the channel region. A trapping layer is formed over the charge blocking layer. A tunnel layer of two or more sub-layers is formed over the trapping layer, where the two or more sub-layers form a crested barrier tunnel layer. A control gate is formed over the tunnel layer.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

Abstract: To manufacture a MOS semiconductor memory device having an insulating film laminate in which adjacent insulating films have band-gaps of different sizes, a plasma processing device which transmits microwaves to a chamber by means of a planar antenna having a plurality of holes is used to perform plasma CVD under pressure conditions that differ from at least pressure conditions used when forming the adjacent insulating films, and the insulating films are sequentially formed by altering the band-gaps of the adjacent insulating films that constitute the insulating film laminate.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Abstract: A reactive ion etching (RIE) process comprising a chlorine source gas and an oxygen source gas with an atomic ratio of chlorine to oxygen in the plasma of at least 6 to 1 is used to etch chromium alloy films such as SiCr, SiCrC, SiCrO, SiCrCO, SiCrCN, SiCrON, SiCrCON, CrO, CrN, CrON, and NiCr for example. Additionally, a fluorine source may be added to the etch chemistry.

Abstract: Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact.