Abstract: Provided is a method of manufacturing a biochip using a droplet discharging device including a droplet discharging head having a cavity and a nozzle hole provided in communication with the cavity, and a liquid housing unit connected to the cavity via a passage, having the steps of filling a retention liquid which separates without getting mixed with the sample liquid into the liquid housing unit, the passage, and the cavity; injecting the sample liquid into the liquid housing unit; moving the sample liquid from the liquid housing unit to the cavity by discharging the retention liquid from the nozzle hole; stopping the discharge of the retention liquid at the moving step upon detecting with a sensor that the sample liquid reached a position adjacent to the nozzle hole; and delivering the sample liquid as droplets onto the object by discharging the sample liquid from the nozzle hole.

Abstract: The present invention provides an active assay method for detecting a biological analyte. According to the method, a probe molecule is immobilized on a surface. An analyte is then placed in fluidic connection with the probe molecule on the surface. A force is then applied to the analyte to move it toward the surface to facilitate contact and possibly binding of the analyte to the probe. Optionally, another force can be applied or the force can be reversed, to remove unbound or weakly bound analyte from the surface. Analyte that remains bound to the surface is then detected. The detection can include rolling or sliding beads over an analyte and/or probe on a substrate, and detecting bound beads. The present invention furthermore, provides devices, such as electrophoresis apparatuses and biochip assemblies, for carrying out the methods of the invention.

Abstract: The present invention provides a protein-immobilized carrier which can realize highly efficient use of an immobilized antibody and prevent non-specific binding. A protein-immobilized carrier including a porous body having mesopores characterized in that the carrier has mesopores having an organic substance adsorbed therein other than an antibody, an antigen or a fragment thereof having a particle size smaller than the pore size of the mesopores and having an antibody, an antigen or a fragment thereof physically adsorbed and immobilized from the pore entrance to a depth of not more than the pore size in the depth direction of the mesopores.

Abstract: The disclosure provides a method of forming a ferromagnetic material, including: forming a magnetic element layer on a semiconductor layer formed on an inhibition layer; and forming a ferromagnetic layer of a Heusler alloy layer on the inhibition layer by heat treatment to induce the semiconductor layer and the magnetic element layer to react with each other, and a transistor, and a method of manufacturing the same. The inhibition layer for inhibiting a reaction of the semiconductor layer and the magnetic element layer restricts a semiconductor to be supplied for a reaction of the semiconductor and the magnetic element. Therefore, it is possible to form a ferromagnetic material having a high composition ratio of a magnetic element.

Abstract: The present invention provides a recovery processing method to restore the substrate processing apparatus to an operating state after correcting an abnormality having occurred in the substrate processing apparatus in operation and having resulted in a stop in the operation, comprising a substrate retrieval step in which substrate salvage processing is first executed for a wafer W left in a chamber in the substrate processing apparatus in correspondence to the extent to which the wafer has been processed at the time of the operation stop and the substrate having undergone the substrate salvage processing is then retrieved into the cassette storage container and an apparatus internal state restoration step in which the states inside the individual chambers of the substrate processing apparatus are restored.

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film. During the second polishing process and the third polishing process, a polishing state of the substrate is monitored with an eddy current sensor, and the third polishing process is terminated when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: A system in package (10) has a, preferably wireless, test controller (20) for testing each die (30) after it has been mounted onto the substrate of the system in package (10), and a faulty die (30) is repaired before a next die (30) is mounted onto the substrate (15). This way, the system in package (10) can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies (30) function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package (10) is obtained that has an improved yield compared to known manufacturing methods.

Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

Abstract: The present invention provides a composite laser element that solves the problems encountered with a conventional laser medium composed of an Nd:YAG single crystal or polycrystal, and exhibits excellent performance as a laser medium. The invention relates to a laser element in which two or more crystal materials are joined, wherein (1) at least one of the crystal materials is a transparent crystal material capable of laser oscillation, including a laser active element in a matrix crystal, and (2) the transparent crystal material capable of laser oscillation and/or a second crystal body joined thereto is a polycrystal.

Abstract: Disclosed herein is a light emitting device including an LED die and a photopolymerizable composition comprising a silicon-containing resin comprising silicon-bonded hydrogen and aliphatic unsaturation, and from about 0.5 to about 30 parts per million of a platinum catalyst. The photopolymerizable composition may be free of catalyst inhibitor. Also disclosed herein are methods of making the light emitting device.

Abstract: A dual panel-type organic electroluminescent display device includes first and second substrates facing and spaced apart from each other, an array element layer disposed along an inner surface of the first substrate, the array element including a thin film transistor, a connection pattern disposed on the array element layer and electrically connected to the thin film transistor, a color filter layer disposed along an inner surface of the second substrate, the color filter layer including red, green, and blue color filters, an overcoat layer disposed on the color filter layer, the overcoat layer including a hygroscopic material, an organic electroluminescent diode disposed on the overcoat layer and connected to the connection pattern, the organic electroluminescent diode including a first electrode, an organic light-emitting layer, and a second electrode sequentially formed on the overcoat layer, and the organic light-emitting layer emits substantially monochromatic light, and a seal pattern along peripheral p

Abstract: A method for manufacturing a reflective surface sub-assembly for a light-emitting device, comprising a substrate, at least one area reserved for placement of a light-emitting device assembly on the substrate, and a diffusive reflective layer applied on selected regions on the substrate, wherein if the light-emitting device assembly were placed onto the at least one area then the diffusive reflective layer would reflect photons emitted by the light-emitting device assembly is disclosed.

Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.

Abstract: Provided are a light-emitting element and a light-emitting device, and methods of fabricating the same. The method of fabricating a light-emitting element includes forming a buffer layer on a substrate and forming photonic crystal patterns and a pad pattern on the buffer layer. Each of the pad pattern and the photonic crystal patterns are made of a metal material, and the pad pattern is physically connected to the photonic crystal patterns. Forming a light-emitting structure includes sequentially stacking a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type on the buffer layer. And the method also includes forming a first electrode that is electrically connected to the first conductive pattern and forming a second electrode that is electrically connected to the second conductive pattern.

Abstract: A solid-state imaging device includes the following elements. A photoelectric conversion section is arranged in a semiconductor layer having a first surface through which light enters the photoelectric conversion section. A signal circuit section is arranged in a second surface of the semiconductor layer opposite to the first surface. The signal circuit section processes signal charge obtained by photoelectric conversion by the photoelectric conversion section. A reflective layer is arranged on the second surface of the semiconductor layer opposite to the first surface. The reflective layer reflects light transmitted through the photoelectric conversion section back thereto. The reflective layer is composed of a single tungsten layer or a laminate containing a tungsten layer.

Abstract: A wide bandgap semiconductor device with surge current protection and a method of making the device are described. The device comprises a low doped n-type region formed by plasma etching through the first epitaxial layer grown on a heavily doped n-type substrate and a plurality of heavily doped p-type regions formed by plasma etching through the second epitaxial layer grown on the first epitaxial layer. Ohmic contacts are formed on p-type regions and on the backside of the n-type substrate. Schottky contacts are formed on the top surface of the n-type region. At normal operating conditions, the current in the device flows through the Schottky contacts. The device, however, is capable of withstanding extremely high current densities due to conductivity modulation caused by minority carrier injection from p-type regions.

Abstract: A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer.

Abstract: In accordance with the present invention, accurate and easily controlled sloped walls may be formed using AlN and preferably a heated TMAH for such purpose as the fabrication of MEMS devices, wafer level packaging and fabrication of fluidic devices. Various embodiments are disclosed.

Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on a first substrate a sequence of layers of semiconductor material forming a solar cell including at least a top subcell and a bottom subcell; mounting a surrogate substrate on top of the sequence of layers adjacent to the bottom subcell; removing the first substrate to expose the surface of the top subcell; removing the surrogate substrate; and holding the solar cell on a vacuum chuck to support it for subsequent fabrication operations, such as attaching interconnects to the solar cells to form an interconnected array.

Abstract: Disclosed is a photodiode array comprising a semiconductor substrate; a plurality of photodiodes formed on the semiconductor substrate; and crystal fused regions losing crystallinity by fusing a semiconductor material of the photodiodes between the plurality of photodiodes.

Abstract: A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Abstract: A method for forming a thin film photovoltaic device includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method further includes forming a thin layer of copper gallium material overlying the first electrode layer to act as an intermediary adhesive layer to facilitate attachment to the first electrode layer. Additionally, the method includes forming a copper layer overlying the thin layer and forming an indium layer overlying the copper layer to form a multilayered structure and subjecting the multilayered structure to thermal treatment process with sulfur bearing species to form a copper indium disulfide alloy material. The copper indium disulfide alloy material comprises a copper:indium atomic ratio of about 1.2:1 to about 3.0:1 overlying a copper gallium disulfide material converted from the thin layer. Furthermore, the method includes forming a window layer overlying the copper indium disulfide alloy material.

Abstract: The present invention is a process of making a germanium-antimony-tellurium alloy film using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silyltellurium precursor is used as a source of tellurium for the alloy film and is reacted with an alcohol during the deposition process.

Abstract: As a step in performing a process on a structure, a hole pattern is provided in a thin layer of organic resin masking material formed over the structure to provide a process mask. A processing step is then performed through the openings in the mask, and after a processing step is completed the mask is adjusted by a re-flow process in which the structure is placed into an atmosphere of solvent vapor of a solvent of the mask material. By way of the re-flow process, the mask material softens and re-flows to reduce the size of the openings in the mask causing edges of the surface areas on which the processing step was performed to be covered by the mask for subsequent processing steps.

Abstract: An organic thin film transistor (OTFT) and a method of fabricating the same are provided in which an organic layer and metal interconnections are formed to have certain linewidths and shapes such that a degradation of device characteristics is prevented. The method includes providing a substrate, forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode, forming source and drain electrodes on the gate insulating layer, and forming a semiconductor layer on the source and drain electrodes. The gate electrode is formed by an inkjet printing method and ablated by a laser.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate, along with a raised feature formed on the first or the second substrate. At least one of the metal layers may be deposited conformally over the raised feature. The raised feature penetrates the molten material of the first or the second metal layers during formation of the alloy, and produces a spectrum of stoichiometries for the formation of the desired alloy, as a function of the distance from the raised feature. At some distance from the raised feature, the proper ratio of the first metal to the second metal exists to form an alloy of the preferred stoichiometry.

Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.

Abstract: A packaging method involves attaching a first chip to a stable base, forming contact pads at locations on the stable base, applying a medium onto the stable base such that it electrically insulates sides of the first chip, forming electrical paths on the medium, attaching a second chip to the first chip to form an assembly, and removing the stable base. A package has at least two chips electrically connected to each other, at least one contact pad, an electrically conductive path extending from the contact pad to a contact point on at least one of the chips, a planarizing medium, and a coating material on top of the planarizing medium.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract: A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

Abstract: An electronic device includes: a base; a conductor pattern formed on the base; and a circuit chip electrically connected to the conductor pattern. The electronic device further includes a reinforcing member which is disposed on the base to surround the circuit chip, whose outer shape is like a ring, and which includes layers stacked in the thickness direction of the base. The lowermost layer of the layers is closest to the base and softer than the layer that is at least one of the remaining layers. The electronic device further includes a sealing member which fills an inside of the reinforcing member while covering the top of the circuit chip, thereby sealing the circuit chip on the base.

Abstract: Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.

Abstract: The invention relates to a method for producing a switch element. The invention is characterised in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode.

Abstract: This invention provides methods for fabricating high speed TFTs from silicon-on-insulator and bulk single crystal semiconductor substrates, such as Si(100) and Si(110) substrates. The TFTs may be designed to have a maximum frequency of oscillation of 3 GHz, or better.

Abstract: A thin-film transistor (“TFT”) substrate includes an insulating substrate, a gate line and a data line which are insulated from each other, disposed on the insulating substrate and are arranged in a lattice, and a pixel electrode which is electrically connected to the gate line and the data line by a switching device. The data line includes a lower layer which is formed of a transparent electrode, and an upper layer which is disposed directly on the lower layer.

Abstract: A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s).

Abstract: A thin film transistor substrate, wherein the moving area of electrons between source and drain electrodes of a thin film transistor (TFT) is minimized, the moving distance of electrons is increased, and the sizes of capacitors defined by a gate electrode together with the respective source and drain electrodes are identical to each other so that an off current generated when the TFT is off can be minimized; a method of manufacturing the thin film transistor substrate; and a mask for manufacturing the thin film transistor substrate. Accordingly, it is possible to minimize an off current induced due to a phenomenon of electron trapping by light.

Abstract: A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current.

Abstract: The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present overlying a portion of the semiconducting surface in the first device region including a first work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a first type strain inducing layer present overlying the first device region; and a p-type device including a second gate structure present overlying a portion of the semiconducting surface in the second device region including a second work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a second type strain inducing layer present overlying the second device region.

Abstract: A method for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change among resistance states. The sequence of bias arrangements includes a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state.

Abstract: The thickness of a semiconductor wafer layer, extending from a mirror-finished surface thereof to a solid-state image sensing device, is measured. Based on the residual thickness data, plasma etching is performed from the mirror-finished surface until a predetermined thickness is reached by controlling the plasma etching amount. By doing this, it is possible to reduce variation in the thickness of the solid-state image sensing device at low cost without causing an increase in the number of processes.

Abstract: On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor.

Abstract: After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.

Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film.

Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other.

Abstract: A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.