Abstract: This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device.

Abstract: One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.

Abstract: A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2 oxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiO2 at bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact.

Abstract: Methods for formation of epitaxial layers containing n-doped silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the n-doped epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source, a carbon source and an n-dopant source. An epitaxial layer may have considerable tensile stress which may be created in a significant amount by a high concentration of n-dopant. A layer having n-dopant may also have substitutional carbon. Phosphorus as an n-dopant with a high concentration is provided. A substrate having an epitaxial layer with a high level of n-dopant is also disclosed.

Abstract: The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

Abstract: An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm?3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface.

Abstract: A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion.

Abstract: A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are formed over the resistor protect layer over the first and second ends of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the first dielectric material as a hard mask. Then a second dielectric layer is deposited. A first via mask and etch process is used to etch vias down to the underlying portions of the resistor protect layer over the ends of the thin film resistor. A second via mask and etch process is used to etch substrate vias to an underlying conductor layer.

Abstract: A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Abstract: A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

Abstract: A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: Methods for manufacturing electronic devices and devices produced by those methods are disclosed. One such method includes releasably bonding a first surface of a device substrate to a face of a first carrier substrate using a first bonding agent to produce a first composite substrate, where the face of the first carrier substrate includes a pattern of trenches. The method also includes processing the device substrate to manufacture an electronic device on a second surface of the device substrate. The method further includes releasing the device substrate from the first carrier substrate by a releasing agent.

Abstract: Microelectronic dies are thinned according to a variety of approaches, which may include bonding the dies to a substrate under vacuum, disposing a film over the dies and the substrate, and/or changing a center of pressure during thinning.

Abstract: A method for transferring a thin layer from an initial substrate includes forming an assembly of the initial substrate with one face of a silicone type polymer layer, this face having been treated under an ultraviolet radiation, and processing the initial substrate to form the thin layer on the silicone type polymer layer.

Abstract: A wafer for backside illumination type solid imaging device having a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side is produced by a method comprising a step of forming a BOX oxide layer on at least one of a wafer for support substrate and a wafer for active layer, a step of bonding the wafer for support substrate and the wafer for active layer and a step of thinning the wafer for active layer, which further comprises a step of forming a plurality of concave portions on a bonding face of the BOX oxide layer to the other wafer and filling a polysilicon plug into each of the concave portions to form a composite layer before the step of bonding the wafer for support substrate and the wafer for active layer.

Abstract: A method for manufacturing a device, in which a wafer having a plurality of devices formed on the face thereof is divided into the individual devices, and an adhesive film is mounted on the back side of each device.

Abstract: Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method, highly rectilinear and well-ordered nanowires can be produced in a simple manner.

Abstract: An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate.

Abstract: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 ?m and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.

Abstract: To provide a manufacturing method for an epitaxial wafer that alleviates distortions on a back surface thereof due to sticking between a wafer and a susceptor, thereby preventing decrease in flatness thereof due to a lift pin. A manufacturing method for an epitaxial wafer according to the present invention includes: an oxide film forming step in which an oxide film is formed on a back surface thereof; an etching step in which a hydrophobic portion exposing a back surface of the semiconductor wafer is provided by partially removing the oxide film; a wafer placing step in which the semiconductor wafer is placed; and an epitaxial growth step in which an epitaxial layer is grown on a main surface of the semiconductor wafer; and the diameter of the lift pin installation circle provided on a circle on a bottom face of a susceptor is smaller than that of the hydrophobic portion.

Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Abstract: The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency.

Abstract: A semiconductor structure consistent with certain implementations has a crystalline substrate oriented with a {111} plane surface that is within 10 degrees of surface normal. An epitaxially grown electrically insulating interlayer overlays the crystalline substrate and establishes a coincident lattice that mates with the surface symmetry of the {111} plane surface. An atomically stable two dimensional crystalline film resides on the epitaxial insulating layer with a coincident lattice match to the insulating interlayer. Methods of fabrication are disclosed. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface.

Abstract: The present invention relates to a method for manufacturing a polycrystalline semiconductor film that can be used for a semiconductor device. In the method, an amorphous semiconductor film is irradiated with a femtosecond laser to be crystallized. By laser irradiation using a femtosecond laser, when an amorphous semiconductor film over which a cap film is formed is crystallized with a laser, it becomes possible to perform crystallization of the semiconductor film and removal of the cap film at the same time. Therefore, a step of removing the cap film in a later step can be omitted.

Abstract: To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over either the separate single-crystal semiconductor layer or the non-single-crystal semiconductor layer, and the first region and the second region are irradiated with a laser beam by applying the laser beam from above the cap film.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches.

Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.

Abstract: A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region.

Abstract: High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

Abstract: A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Abstract: The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Abstract: A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove.

Abstract: A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.

Abstract: A method for manufacturing a structure of electrical interconnections for an integrated circuit having levels of interconnections, the method having steps of depositing a layer of sacrificial material on the substrate, etching the layer of sacrificial material with a pattern corresponding to electrical conductors, depositing, on the etched layer of the layer of sacrificial material, a layer of permeable membrane allowing an attack agent to break down the sacrificial material, breaking down the sacrificial material by using the attack agent to form air gaps to replace the broken down sacrificial material, forming electrical conductors in the etched track so as to obtain electrical interconnections separated by air gaps, and depositing a layer of insulating material to cover the electrical interconnections.

Abstract: A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

Abstract: An electronic device includes a conductive pattern formed on a first insulating film, a second insulating film formed on the conductive pattern and the first insulating film, a hole formed in the second insulating film on the conductive pattern, carbon nanotubes formed in the hole to extend from a surface of the conductive pattern, and a buried film buried in clearances among the carbon nanotubes in the hole.

Abstract: The present invention is a method of film deposition that comprises a film-depositing step of supplying a high-melting-point organometallic material gas and a nitrogen-containing gas to a processing vessel that can be evacuated, so as to deposit a thin film of a metallic compound of a high-melting-point metal on a surface of an object to be processed placed in the processing vessel. A partial pressure of the nitrogen-containing gas during the film-depositing step is 17% or lower, in order to increase carbon density contained in the thin film.

Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

Abstract: An improved method of forming a fully silicided (FUSI) gate in both NMOS and PMOS transistors of the same MOS device is disclosed. In one example, the method comprises forming a first silicide in at least a top portion of a gate electrode of the PMOS devices and not over the NMOS devices. The method further comprises concurrently forming a second silicide in at least a top portion of a gate electrode of both the NMOS and PMOS devices, and forming a FUSI gate silicide of the gate electrodes. In one embodiment, the thickness of the second silicide is greater than the first silicide by an amount which compensates for a difference in the rates of silicide formation between the NMOS and PMOS devices.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.