Abstract: A semiconductor device includes a transistor array including a plurality of transistors each having a gate electrode extended in a first direction, the plurality of transistors being arranged in a second direction intersecting the first direction, and a pad electrode arranged in the first direction of the transistor array and electrically connected to source regions of the plurality of transistors.

Abstract: A plurality of transistors in which ratios of a channel length L to a channel width W, ?=W/L, are different from each other is provided in parallel as output side transistors 105a to 105c in a current mirror circuit 101 which amplifies a photocurrent of a photoelectric conversion device and an internal resistor is connected to each of the output side transistors 105a to 105c in series. The sum of currents which flow through the plurality of transistors and the internal resistor is output, whereby a transistor with large amount of ? can be driven in a linear range with low illuminance, and a transistor with small amount of ? can be driven in a linear range with high illuminance, so that applicable illuminance range of the photoelectric conversion device can be widened.

Abstract: Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method for manufacturing a semiconductor device includes forming a device isolation film defining an active region over a semiconductor substrate including a periphery region, forming a gate pattern over the active region, forming a contact plug coupled to each of the gate pattern and the active region, forming a line coupled to the contact plug and a first reservoir capacitor over the same layer as in the line, and forming a second storage capacitor coupled to the first storage capacitor. The semiconductor device sufficiently endures a high bias not only using a line electrode and a dielectric film of a periphery region but also using a MOS-type storage capacitor of an upper electrode, and couples a cylindrical storage capacitor in series to a MOS-type capacitor so that it can be used in a small region.

Abstract: A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device may include a substrate provided with a transistor, an insulating layer disposed on the substrate, the insulating layer including a contact hole exposing a portion of the transistor, a spacer disposed on an inner sidewall of the contact hole, and a contact plug disposed in the contact hole. Here, a space defined by the spacer may increase in width from a bottom side thereof to a top side thereof.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

Abstract: A semiconductor storage device with active regions formed in the shape of a band in a substrate; a plurality of word lines arranged at equal intervals that intersect the active regions; cell contacts that includes first cell contacts in the active regions in the center portions in a longitudinal direction, and second cell contacts at both ends in the longitudinal direction; bit line contacts on the first cell contacts; bit lines that pass over the bit line contacts; storage node contacts on the second cell contacts; storage node contact pads on the storage node contacts; and storage capacitors on the storage node contact pads. The center positions of the storage node contacts are offset from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset from the center positions of the storage node contacts.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract: A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

Abstract: According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.

Abstract: According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

Abstract: A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction.

Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.

Abstract: According to one embodiment, a plurality of memory cells are provided on a semiconductor substrate. In each memory cell, a control gate electrode is provided on a charge accumulation layer with an inter-electrode insulation film interposed between the control gate electrode and the charge accumulation layer, an air gap is provided between the charge accumulation layers adjacent to each other in a word line direction, and an insulation film disposed below the inter-electrode insulation film is divided into an upper part and a lower part by the air gap.

Abstract: A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Abstract: An organic thin-film transistor (100) includes, on a substrate (1), a gate electrode (2), a gate insulating layer (3), a source electrode (4), and a drain electrode (5). Part of surface of the source electrode (4) is covered by a first organic molecular layer (6a). Part of surface of the drain electrode (5) is covered by a second organic molecular layer (6b). An organic semiconductor layer (7) is formed so as to cover the organic molecular layer (6) (first and second organic molecular layers (6a, 6b)), the source electrode (4), and the drain electrode (5), and get into a channel section (20) which is a gap between the electrodes. Since the organic thin-film transistor (100) has the organic molecular layer (6) covering at least part of surface of each of the source and drain electrodes (4, 5), hole-electron injection efficiency is increased. This makes it possible to obtain large current.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Embodiments of the present invention relate generally to semiconductor devices and, more particularly, to a structure for high-voltage (HV) semiconductor-on-insulator (SOI) devices and methods for their formation. In one embodiment, the invention provides a semiconductor-on-insulator (SOI) device comprising: a substrate; an insulator layer atop the substrate; a polysilicon layer atop the insulator layer; a device layer atop the polysilicon layer, the device layer comprising: a P-well; an N-well; and an undoped silicon region between the P-well and the N-well; and a trench isolation adjacent one of the P-well and the N-well and extending through the device layer and the polysilicon layer to the insulator layer.

Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

Abstract: To provide a technology capable of manufacturing a semiconductor device equipped with a HK/MG transistor having a gate insulating film comprised of a high-k material and a gate electrode comprised of a metal material and having stable operation characteristics. A film stack configuring an Nch gate stack structure is formed only in a region located in an active region surrounded with an element isolation portion and in which a gate of a core nMIS is to be formed in a later step is formed, while a film stack configuring a Pch gate stack structure is formed in a region other than the above region. This makes it possible to reduce a supply amount of oxygen atoms to be attracted from the element isolation portion to the region in which the gate of the core nMIS is to be formed.

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract: Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: A method for forming a tileable detector array is presented.

Abstract: A method for producing microelectromechanical structures in a substrate includes: arranging at least one metal-plated layer on a main surface of the substrate in a structure pattern; leaving substrate webs open beneath a structure pattern region by introducing first trenches into the substrate perpendicular to a surface normal of the main surface in a region surrounding the structure pattern; coating the walls of the first trenches perpendicular to the surface normal of the main surface with a passivation layer; and introducing cavity structures into the substrate at the base of the first trenches in a region beneath the structure pattern region.

Abstract: A micromechanical component includes: a substrate having a multitude of trench structures which separate a first and a second mass element of the substrate from a web element of the substrate, in such a way that the first and second mass elements enclose the web element along an extension direction of the main surface of the substrate and are disposed to allow movement relative to the substrate in the direction of a surface normal of the main surface; a first electrode layer applied on the main surface of the substrate and forms a first electrode on the web element between the first and second mass elements; and a second electrode layer applied on the first and second mass elements and forming a self-supporting second electrode above the first electrode in the area of the web element, the first and second electrode forming a capacitance.

Abstract: A method for producing oblique surfaces in a substrate, comprising a formation of recesses on both surfaces of the substrate, until the recesses are so deep that the substrate is perforated by the two recesses. One recess is produced going out from a first main surface in the region of a first surface, and the other recess is produced going out from the second main surface in the region of a second surface, so that the first surface and the second surface do not coincide along a surface normal of the main surfaces of the substrate. Subsequently, flexible diaphragms are attached over the recesses on each of the main surfaces. If a vacuum pressure is then produced inside the recesses, the flexible diaphragms each curve in the direction of the recesses until their surfaces facing the substrate come into contact with one another, generally in the center of the recesses.

Abstract: A capacitive sensor is configured for collapsed mode, e.g. for measuring sound or pressure, wherein the moveable element is partitioned into smaller sections. The capacitive sensor provides increased signal to noise ratio.

Abstract: In one embodiment, a semiconductor structure includes a beam positioned within a sealed cavity, the beam including: an upper insulator layer including one or more layers; and a lower insulator layer including one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer, such that the beam bends.

Abstract: A magnetization reversal device includes a ferromagnetic 12 body which is provided in an interconnection of a non-ferromagnetic dot 11 so that a part or a whole of the ferromagnetic dot is three-dimensionally buried in the interconnection of said non-ferromagnetic dot, and a spin injection source 13 which generates a spin-polarized pure spin current without a flow of charges, and which is provided in the interconnection of the non-ferromagnetic dot 11 to be in contact therewith so that the interconnection of the non-ferromagnetic dot serves as a common electrode, and the pure spin current flows into the ferromagnetic dot 2 through the interconnection of the non-magnetic body by the spin injection source 13 due to a diffusion current, to thereby reverse magnetization of the ferromagnetic dot 12.

Abstract: Provided are a spin-injection element having high spin-injection efficiency, and a magnetic field sensor and a magnetic recording memory employing the element. The element comprises a barrier layer, a magnetic conductive layer, and a spin accumulation portion comprised of non-magnetic conductive material. In the element, a first spin accumulation layer (103) and the barrier layer (102) have respectively a body-centered cubic lattice structure. Due to this, the first spin accumulation layer (103) and the barrier layer (102) come into contact with each other through a boundary face with improved crystalline symmetry. Thereby, lattice matching is improved and scattering of the tunnel electrons in the ?1 band is prevented, resulting in improvement in the spin polarizability. Further, the characteristics of the device employing the spin injection element are improved.

Abstract: There has been such a problem that radiation detecting elements using semiconductor elements have a low radiation detection efficiency, since the radiation detecting elements easily transmit radiation, even though the radiation detecting elements have merits, such as small dimensions and light weight. Disclosed are a radiation detecting element and a radiation detecting device, wherein a film formed of a metal, such as tungsten, is formed on the radiation incident surface of the radiation detecting element, and the incident energy of the radiation is attenuated. The efficiency of generating carriers by way of radiation incidence is improved by attenuating the incident energy, the thickness of the metal film is optimized, and the radiation detection efficiency is improved.

Abstract: According to one embodiment, a semiconductor device includes: a through-hole formed in a semiconductor layer; a through-hole insulting layer formed on a sidewall of the through-hole to retract from a front surface of the semiconductor layer; a through-electrode embedded in the through-hole via the through-hole insulating layer; and a sidewall insulating film formed on a sidewall of the through-electrode to be embedded in a retracting section of the through-hole insulating layer.

Abstract: A solid-state imaging device according to an embodiment includes: a plurality of pixels arranged on a first face of a first semiconductor layer, each of the pixels including a photoelectric conversion element converting light entering through a second face of the first semiconductor layer on the opposite side from the first face into a signal charge, the photoelectric conversion element having a pn junction formed with a first semiconductor region formed on the first face and a second semiconductor region formed on a surface of the first semiconductor region; pixel separating regions separating the pixels from one another and formed between the pixels, each of the pixel separating regions including a second semiconductor layer covering faces in contact with the photoelectric conversion elements, and an insulating film with a lower refractive index than a refractive index of the second semiconductor layer to cover the second semiconductor layer.

Abstract: The present invention relates to a composite system for photovoltaic (PV) modules. The composite system consists of a carrier foil, a metal foil applied onto the carrier foil, and an insulating layer applied onto the metal foil. Using different connecting techniques, different photovoltaic (PV) cells can be fastened to the composite system and electrically interconnected thereby. In addition, the invention relates to a method for producing the composite system for PV modules, and to the use of the composite system for the back side contacting of wafer cells that have both contacts on the same side and that are placed, with the contacts, onto conductor structures that interconnect them into a module, and to the use of the composite system for modules of internally interconnected thin-film cells.

Abstract: A semiconductor light receiving element includes a first semiconductor layer having a first conduction type, a second semiconductor layer that is provided on the first semiconductor layer and has a light receiving area, the second semiconductor layer having a second conduction type opposite to the first conduction type, an insulation film provided on the second semiconductor layer, and an electrode provided on the insulation film, the insulation film having a plurality of windows in an area in which the electrode overlaps the plurality of windows, the electrode being electrically connected to the second semiconductor layer via the plurality of windows.