Abstract: An oxide semiconductor thin film transistor structure includes a substrate, a gate electrode disposed on the substrate, a semiconductor insulating layer disposed on the substrate and the gate electrode, an oxide semiconductor layer disposed on the semiconductor insulating layer, a patterned semiconductor layer disposed on the oxide semiconductor layer, and a source electrode and a drain electrode respectively disposed on the patterned semiconductor layer. The source electrode and the drain electrode are made of a metal layer.

Abstract: A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.

Abstract: An organic light-emitting display apparatus includes: an active layer formed on the substrate; a gate electrode, in which a first insulation layer formed on the active layer, a first conductive layer formed on the first insulation layer and comprising a transparent conductive material, and a second conductive layer comprising a metal are sequentially stacked; a pixel electrode, in which a first electrode layer formed on the first insulation layer to be spaced apart from the gate electrode and comprising a transparent conductive material, a second electrode layer formed of a semi-permeable metal and comprising pores, and a third electrode layer comprising a metal are sequentially stacked; source/drain electrodes electrically connected to the active layer with a second insulation layer covering the gate electrode and the pixel electrode interposed therebetween; an electro-luminescence (EL) layer formed on the pixel electrode; and an opposite electrode formed on the EL layer to face the pixel electrode, wherein

Abstract: A display substrate having a low resistance signal line and a method of manufacturing the display substrate are provided. The display substrate includes an insulation substrate, a gate line, a data line and a pixel electrode. The gate line gate line is formed through a sub-trench and an opening portion. The sub-trench is formed in the insulation substrate and the opening portion is formed through a planarization layer on the insulation substrate at a position corresponding to the position of the sub-trench. The data line crosses the gate line. The pixel electrode is electrically connected to the gate line and the data line through a switching element. Thus, a signal line is formed through a trench formed by using a planarization layer and an insulation substrate, so that a resistance of the signal line may be reduced.

Abstract: A display device free of contact resistance between a drain electrode (or a source electrode) and a pixel electrode. The display device includes a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor layer formed over the gate insulating layer, and a source electrode and a drain electrode separated from each other and in partial-contact with and over the semiconductor layer, and one of the source electrode and the drain electrode also serves as a pixel electrode, the other of the source electrode and the drain electrode also serves as a signal line, and a low resistant conductive layer is preferably formed over the other of the source electrode and the drain electrode. The low resistant conductive layer can be formed by an electroplating method or the like.

Abstract: It is an object to provide a transistor having a new multigate structure in which operating characteristics and reliability are improved. In a transistor having a multigate structure, which includes two gate electrodes electrically connected to each other and a semiconductor layer including two channel regions connected in series formed between a source region and a drain region, and a high concentration impurity region is formed between the two channel regions; the channel length of the channel region adjacent to the source region is longer than the channel length of the channel region adjacent to the drain region.

Abstract: In an organic light emitting diode (OLED) display and a manufacturing method, an organic light emitting diode (OLED) display includes: a substrate; a semiconductor layer pattern formed on the substrate and including a first capacitor electrode; a gate insulating layer covering the semiconductor layer pattern; a first conductive layer pattern formed on the gate insulating layer and including a second capacitor electrode having at least a portion overlapping the first capacitor electrode; an interlayer insulating layer having a capacitor opening exposing a portion of the second capacitor electrode and covering the second capacitor electrode; and a second conductive layer pattern formed on the interlayer insulating layer, wherein the capacitor opening includes a first transverse side wall parallel to and overlapping the second capacitor electrode, a second transverse side wall parallel to and not overlapping the second capacitor electrode, and a longitudinal side wall connecting the first transverse side wall an

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

Abstract: A structure and a method can provide a crystalline seed layer material, such as GaN, on a crystalline carrier material, such as sapphire, aligned such that a common crystal plane exists between the two materials. The common crystal plane may provide for a fracture surface along a cleavage plane that may be oriented to be perpendicular to the top surface of an optoelectronic device as well as perpendicular to a light emission direction.

Abstract: The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.

Abstract: In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 ?m from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

Abstract: A method for manufacturing a semiconductor structure is provided which includes the following steps: a crystalline semiconductor substrate (1) is supplied; a porous region (10) is provided adjacent to a surface (OF) of the semiconductor substrate (1); a dopant (12) is introduced into the porous region (10) from the surface (OF); and the porous region (10) is thermally recrystallized into a crystalline doping region (10?) of the semiconductor substrate (1) whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate (1). A corresponding semiconductor structure is likewise provided.

Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

Abstract: An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti(1?x?y)Si(s)C(y) ternary film of which a composition ratio is within a composition range that is surrounded by two lines and two curves expressed by an expression x=0 (0.35?y?0.5), an expression y=?1.120x+0.5200 (0.1667?x?0.375), an expression y=1.778(x?0.375)2+0.1 (0?x?0.375) and an expression y=?2.504x2?0.5828x+0.5 (0?x?0.1667) and that excludes the line expressed by the expression x=0. The ohmic layer is directly laminated on a surface of a p-type SiC semiconductor.

Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically, and thermally stable, and is excellent in respect of low contact resistance, and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni, and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy, or the nickel-chromium compound, it is improved in characteristics.

Abstract: A phosphor blend for an LED light source is provided wherein the phosphor blend comprises from about 7 to about 12 weight percent of a cerium-activated yttrium aluminum garnet phosphor, from about 3 to about 6 weight percent of a europium-activated strontium calcium silicon nitride phosphor, from about 15 to about 20 weight percent of a europium-activated calcium silicon nitride phosphor, and from about 55 to about 80 weight percent of a europium-activated calcium magnesium chlorosilicate phosphor. An LED light source in accordance with this invention has a B:G:R ratio for a 3200 K tungsten balanced color film of X:Y:Z when directly exposed through a nominal photographic lens, wherein X, Y and Z each have a value from 0.90 to 1.10.

Abstract: Active or functional additives are embedded into surfaces of host materials for use as components in a variety of electronic or optoelectronic devices, including solar devices, smart windows, displays, and so forth. Resulting surface-embedded device components provide improved performance, as well as cost benefits arising from their compositions and manufacturing processes.

Abstract: According to one embodiment, an LED module includes a substrate, an interconnect layer, a light emitting diode (LED) package, and a reflection member. The interconnect layer is provided on the substrate. The LED package is mounted on the interconnect layer. The reflection member is provided on a region in the substrate where the LED package is not mounted and has a property of reflecting light emitted from the LED package. The LED package includes a first lead frame, a second lead frame, an LED chip, and a resin body. The first lead frame and the second lead frame are arranged apart from each other on the same plane. The LED chip is provided above the first lead frame and the second lead frame, with one terminal connected to the first lead frame and one other terminal connected to the second lead frame.

Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes: a substrate, an organic light emitting diode positioned on the substrate, a metal layer positioned on the substrate with the organic light emitting diode interposed therebetween, and a resin layer positioned on the metal layer and configured to reinforce a strength of the metal layer.

Abstract: According to one embodiment, an LED module includes a substrate, an interconnect layer, an LED package, and a resin. The resin is provided on the substrate to cover the LED package. The resin has a refractive index higher than a refractive index of air. The resin is transmissive with respect to light emitted from the LED package. The LED package includes first and second leadframes, an LED chip, and a resin body. The first and second leadframes are disposed on a plane. An exterior form of the resin body is used as an exterior form of the LED package.

Abstract: An organic EL element has an anode, a cathode, a hole injection layer and at least one functional layer disposed between the anode and the cathode. The at least one functional layer contains an organic material. Holes are injected into the functional layer from the hole injection layer, which contains a tungsten oxide. A Ultraviolet Photoelectron Spectroscopy (UPS) spectrum obtained from a UPS measurement has a protrusion near a Fermi surface and within a region corresponding to a binding energy range lower than a top of the valence band. The tungsten oxide contained in the hole injection layer satisfies a condition, determined from an X-ray Photoelectronic Spectroscopy measurement, that a ratio in a number density of atoms other than tungsten and oxygen atoms to the tungsten atoms does not exceed approximately 0.83.

Abstract: A method of manufacturing an organic light-emitting element. A first layer is formed above a substrate, and exhibits hole injection properties. A bank material layer is formed above the first layer using a bank material. Banks are formed by patterning the bank material layer, and forming a resin film on a surface of the first layer by attaching a portion of the bank material layer to the first layer, the banks defining apertures corresponding to light-emitters, the resin material being the same as the bank material. A functional layer is formed by applying ink to the apertures that contacts the resin film. The ink contains an organic material. The functional layer includes an organic light-emitting layer. A second layer is formed above the functional layer and exhibits electron injection properties. The hole injection properties of the first layer are then degraded by applying electrical power to an element structure.

Abstract: The present disclosure provides a radiation device. The radiation device includes a first light emitting diode (LED) operable to emit light having a first central wavelength; a second LED configured adjacent the first LED and operable to emit light having a second central wavelength substantially less than the first central wavelength; and a luminescent material disposed on the first LED and the second LED. The luminescent material includes a strontium silicon nitride (SrSi6N8) doped by one of cerium (Ce3+) and cerium, lithium (Ce3+, Li+).

Abstract: The present invention is directed to LED packages and methods utilizing waterproof and UV resistant packages with improved structural integrity. In some embodiments, the improved structural integrity is provided by various features in the lead frame that the casing material encompasses to improve the adhesion between the lead frame and the casing for a stronger, waterproof package. Moreover, in some embodiments the improved structural integrity and waterproofing is further provided by improved adhesion between the encapsulant and the casing. Some embodiments also provide for improved wire bonds, with the length, thickness, and loop height of the wire bonds controlled and optimized for improved adhesion between the wire bonds and the encapsulant as well as improved reliability.

Abstract: According to one embodiment, an LED package includes a first, a second, and a third lead frame separated from one another. The LED package includes a first LED chip of a top surface terminal type having one terminal connected to the second lead frame, and having one other terminal connected to the third lead frame, the first LED chip is mounted on the first lead frame. The LED package includes a first protection chip of a top surface terminal type having one terminal connected to the second lead frame, and having one other terminal connected to the third lead frame, the first protection chip is mounted on the first lead frame. And, a resin body covers a part of the first, second and third lead frames, the first LED chip, and the first protection chip, An outer shape of the resin body forms an outer shape of the LED package.

Abstract: Disclosed is a light emitting device employing non-stoichiometric tetragonal Alkaline Earth Silicate phosphors. The light emitting device comprises a light emitting diode emitting light of ultraviolet or visible light, and non-stoichiometric luminescent material disposed around the light emitting diode. The luminescent material adsorbs at least a portion of the light emitted from the light emitting diode and emits light having a different wavelength from the absorbed light. The non-stoichiometric luminescent material has tetragonal crystal structure, and contains more silicon in the crystal lattice than that in the crystal lattice of silicate phosphors having stoichiometric crystal structure. The luminescent material is represented as the formula (BauSrvCawCux)3-y(Zn,Mg,Mn)zSi1+bO5+2b:Eua. Light emitting devices having improved temperature and humidity stability can be provided by employing the non-stoichiometric tetragonal Alkaline Earth Silicate phosphors.

Abstract: According to one embodiment, an optical semiconductor device includes an n-type semiconductor layer, a p-type semiconductor layer, and a functional part. The functional part is provided between the n-type semiconductor layer and the p-type semiconductor layers. The functional part includes a plurality of active layers stacked in a direction from the n-type semiconductor layer toward the p-type semiconductor layer. At least two of the active layers include a multilayer stacked body, an n-side barrier layer, a well layer and a p-side barrier layer. The multilayer stacked body includes a plurality of thick film layers and a plurality of thin film layers alternately stacked in the direction. The n-side barrier layer is provided between the multilayer stacked body and the p-type layer. The well layer is provided between the n-side barrier layer and the p-type layer. The p-side barrier layer is provided between the well layer and the p-type layer.

Abstract: The present invention provides a light emitting device and a method for manufacturing a light emitting device. The light emitting device includes a base, an LED inversely mounted on the base. The LED includes an LED chip connected to the base and a buffer layer located on the LED. The buffer layer includes a plurality of depressions with complementary pyramid structure on a surface of the buffer layer not face the LED, the surface being a light-exiting surface of the LED. The buffer layer is made from silicon carbide. The light emitting device has a large area of the light-exiting surface and provides a reflecting film on a base, thus improving the luminous efficiency of the light emitting device. Inversely mounting mode is adopt, which is easy to implement.

Abstract: An exemplary LED package includes first and second electrodes, an LED chip and two electrically conductive wires. The first electrode has a top surface and an opposite bottom surface. A recess is defined in the top surface of the first electrode. The second electrode has a top surface and an opposite bottom surface. A recess is defined in the top surface of the second electrode. The LED chip has a bottom surface attached to the top surface of the first electrode, and a top surface on which a first pad and a second pad are formed. One of the electrically conductive wires has an end connecting to the first pad and an opposite end joining with a bottom of the recess of the first electrode. The other has an end connecting to the second pad and an opposite end joining with a bottom of the recess of the second electrode.

Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, an electrode, a p-type semiconductor layer and a light emitting layer. The p-type semiconductor layer is provided between the n-type semiconductor layer and the electrode and includes a p-side contact layer contacting the electrode. The light emitting layer is provided between the n-type and the p-type semiconductor layers. The p-side contact layer includes a flat part having a plane perpendicular to a first direction from the n-type semiconductor layer toward the p-type semiconductor layer and multiple protruding parts protruding from the flat part toward the electrode. A height of the multiple protruding parts along the first direction is smaller than one-fourth of a dominant wavelength of light emitted from the light emitting layer. A density of the multiple protruding parts in the plane is 5×107/cm2 or more and 2×108/cm2 or less.

Abstract: Disclosed is a light-emitting device comprising: a carrier; a light-emitting element disposed on the carrier; a first light guide layer covering the light-emitting element, and disposed on the carrier; a wavelength conversion and light guide layer covering the first light guide layer and the light-emitting element, and disposed on the carrier; and a low refractive index layer disposed between the first light guide layer and the wavelength conversion and light guide layer; wherein the first light guide layer comprises a gradient refractive index, the wavelength conversion and light guide layer comprises a dome shape structure and is used to convert a wavelength of light emitted from the light-emitting element and transmit light, and the low refractive index layer is used to reflect light from the wavelength conversion and light guide layer.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence. The semiconductor layer sequence contains at least one active layer for generating primary radiation. In addition, the semiconductor layer sequence includes a plurality of conversion layers, the conversion layers being designed to absorb the primary radiation at least partially and to convert it into secondary radiation of a longer wavelength than the primary radiation. Furthermore the semiconductor layer sequence comprises a roughening which extends at least into the conversion layers.

Abstract: A light emitting device is disclosed. The light emitting device includes a first electrode and a second electrode, which have different areas, thereby achieving enhanced bonding reliability.

Abstract: A light-emitting diode includes a carrier having a mounting surface; at least one light-emitting diode chip fixed to the mounting surface; and a reflective element provided for reflecting electromagnetic radiation, wherein the reflecting element is fixed to the carrier and includes porous polytetrafluoroethylene.

Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitter, a first and a second electrode layer, a pad electrode and an auxiliary electrode portion. The emitter includes a first semiconductor layer provided on one side of the emitter, a second semiconductor layer provided on one other side of the emitter, and a light emitting layer provided between the first and second semiconductor layers. The first electrode layer is provided on opposite side of the second semiconductor layer from the first semiconductor layer and includes a metal layer and a plurality of apertures penetrating through the metal layer. The second electrode layer is electrically continuous with the first semiconductor layer. The pad electrode is electrically continuous with the first electrode layer. The auxiliary electrode portion is electrically continuous with the first electrode layer and extends in a second direction orthogonal to the first direction.

Abstract: According to one embodiment, an LED package includes mutually-separated first and second leadframes, an LED chip, and a resin body. One selected from the first leadframe and the second leadframe includes a base portion, and an extending portion. The base portion has an end surface covered with the resin body. The extending portion extends from the base portion and has an unevenness provided in a surface of the extending portion. A lower surface of the extending portion is covered with the resin body. A tip surface of the extending portion is exposed from the resin body. An exterior form of the resin body is used as an exterior form of the LED package.

Abstract: An organic light-emitting device includes a base plate, an organic light-emitting body formed on the base plate, a heat-transferring filling material formed around the organic light-emitting body to cover the organic light-emitting body, the heat-transferring filling material having an electrically insulating property, and a sealing plate arranged on the heat-transferring filling material.

Abstract: The disclosed light emitting diode includes a substrate provided, at a surface thereof, with protrusions, a buffer layer formed over the entirety of the surface of the substrate, a first semiconductor layer formed over the buffer layer, an active layer formed on a portion of the first semiconductor layer, a second semiconductor layer formed over the active layer, a first electrode pad formed on another portion of the first semiconductor layer, except for the portion where the active layer is formed, and a second electrode pad formed on the second semiconductor layer. Each protrusion has a side surface inclined from the surface of the substrate at a first angle, and another side surface inclined from the surface of the substrate at a second angle different from the first angle.

Abstract: A light-emitting diode (LED) structure with an improved heat transfer path with a lower thermal resistance than conventional LED lamps is provided. For some embodiments, a surface-mountable light-emitting diode structure is provided having an active layer deposited on a substrate directly bonded to a metal plate that is substantially exposed for low thermal resistance by positioning the metal plate at the bottom of the light-emitting diode structure. This metal plate may then be soldered to a printed circuit board (PCB) that includes a heat sink. For some embodiments of the invention, the metal plate is thermally and electrically conductively coupled through several heat conduction layers to a large heat sink that may be included in the structure.

Abstract: A thin-layer encapsulation (1) for an optoelectronic component. The thin-layer encapsulation (1) comprises a sequence of layers (2) that comprises the following layers: a first ALD layer (3) deposited by means of atomic layer deposition, and a second ALD layer (4) deposited by means of atomic layer deposition. A method is disclosed for producing the thin-layer encapsulation and an optoelectronic component is disclosed having such a thin-layer encapsulation.

Abstract: A semiconductor device includes a semiconductor substrate with a first surface and a second surface. The semiconductor substrate has an element region including an IGBT region and a diode region located adjacent to the IGBT region. An IGBT element is formed in the IGBT region. A diode element is formed in the diode region. A heavily doped region of first conductivity type is located on the first surface side around the element region. An absorption region of first conductivity type is located on the second surface side around the element region. A third semiconductor region of second conductivity type is located on the second surface side around the element region.

Abstract: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.

Abstract: A semiconductor component having a semiconductor body is disclosed. In one embodiment, the semiconductor component includes a drift zone of a first conductivity type, a drift control zone composed of a semiconductor material which is arranged adjacent to the drift zone at least in places, a dielectric which is arranged between the drift zone and the drift control zone at least in places. A quotient of the net dopant charge of the drift control zone, in an area adjacent to the accumulation dielectric and the drift zone, divided by the area of the dielectric arranged between the drift control zone and the drift zone is less than the breakdown charge of the semiconductor material in the drift control zone.

Abstract: A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.

Abstract: A novel semiconductor transistor is presented. The semiconductor structure has a gate region forming a channel with repetitive patterns in the direction perpendicular to the current flow, so that the portion of its channel that is not strictly planar contributes to a significant reduction of the silicon area occupied by the device. It offers the advantage of lower on-resistance for the same silicon area while improving on its dynamic performances. The additional cost to shape the channel region of the device in periodic repetitive patterns is minimum, which makes the present invention easy to implement in any conventional CMOS process technology and very cost effective.

Abstract: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact and provides a reduction in the peak operational electric field.

Abstract: The present invention may provide an integrated device, which may include a substrate having first and second regions, the first region spaced apart from the second region, a first heterojunction bipolar transistor (HBT) device formed on the first region of the substrate, the first HBT device having a first collector layer formed above the first region of the substrate, the first collector layer having a first collector thickness and a first collector doping level, and a second HBT device formed on the second region of the substrate, the second HBT device having a second collector layer formed above the second region of the substrate, the second collector layer having a second collector thickness and a second collector doping level, the second collector thickness substantially greater than the first collector thickness, the second collector doping level lower than the first collector doping level.

Abstract: Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.

Abstract: A method of manufacturing a semiconductor device, in which a second semiconductor layer of AlxGa1-x-yInyN (wherein x, y, and x+y satisfy x>0, y?0, and x+y?1, respectively) on a first semiconductor layer of GaN by hetero-epitaxial growth using a MOCVD method, the method including the steps of: (a) supplying N source gas and Ga source gas to form the first semiconductor layer; (b) supplying the N source gas without supplying the Ga source gas and Al source gas, after step (a); (c) supplying the N source gas and the Al source gas without supplying the Ga source gas, after step (b); and (d) supplying the N source gas, the Ga source gas and the Al source gas to form the second semiconductor layer, after step (c).

Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.