Abstract: An apparatus for controlling a head lamp for vehicles which includes an image providing unit which acquires image information in front of a subject vehicle through a camera module and an information processing unit which detects a position of a vehicle in front of the subject vehicle based on the image information to determine a high beam avoidance area. In particular, a light source unit irradiates a high beam and a low beam in the head lamp based on the driving information acquired. In particular, the high beam avoidance area is represented by an angular range, and is within a range of 90 degrees with respect to a forward direction of the subject vehicle, and the angular range of the high beam avoidance area is determined based on outermost vehicles on left and right sides in the image information.

Abstract: A safety rearview mirror for the backseat of automobile vehicles, comprising a rigid plaque which has on one of its faces a finished and reflective surface and on the other face an opaque covering, except for at least, a zone free of the covering, wherein this zone corresponds to signs and/or drawings which are visible through transparency due to a light source associated with the other face. The light source may be of the LED/LCD type or an incandescent lamp.

Abstract: Arrangement accuracy of a transmission member with respect to an exposure hole is increased. In a door mirror device for a vehicle, a turn lamp is assembled to a bracket, a visor rim, and a visor cover, and an exposure portion of a lamp lens of the turn lamp is exposed by an exposure hole of a lower visor cover. As an anchor plate of the lower visor cover is inserted into an anchoring hole of the lamp lens and a fitting column of the lamp lens is inserted into a fitting hole of the lower visor cover, the lamp lens is positioned in the lower visor cover. Therefore, the accuracy precision of the exposure portion with respect to the exposure hole can be increased, thereby enhancing the appearance of a gap between the exposure portion and the periphery of the exposure hole.

Abstract: A vehicle lamp includes a lamp housing, a first light emitting component, a second light emitting component, a lens member, and a light-blocking plate. The lamp housing defines a receiving space having first and second space portions adjacent to each other, and is formed with a light-exit opening. The first and second light emitting components are disposed in a respective one of the first and second space portions. The lens member closes the light-exit opening, and includes a first lens body aligned with the first light emitting component and a second lens body aligned with the second light emitting component. The light-blocking plate is disposed in the receiving space, is aligned with a portion of the second lens body that is adjacent to the first lens body, and is disposed to block a portion of light radiated by the second light emitting component from reaching the second lens body.

Abstract: A head lamp apparatus for a vehicle may include a reflector provided with a light source that emits light to reflect the light emitted from the light source in a forward direction, the reflector having an upper end at which a first auxiliary reflective surface may be formed, and a lower end at which a second auxiliary reflective surface may be formed, and a bezel mounted in front of the reflector and having an upper part on which a first reflective hole that corresponds to the first auxiliary reflective surface may be formed, and a lower part on which a second reflective hole that corresponds to the second auxiliary reflective surface may be formed.

Abstract: A light emitting diode (LED) light box including a housing, a first LED module and a light guiding block is provided. The housing has a first hole. The first LED module is disposed inside the housing. The light guiding block is disposed inside the housing and located in front of the first LED module and opposite to the first hole. The first light emitted by the first LED module enters and proceeds in the light guiding block and then passes through the first hole.

Abstract: A tubular skylight, comprising a tubular body (2) provided with an inner reflecting surface (3), a light collector (4) mounted to a first end of the tubular body (2) and a light diffuser (6) mounted to a second end of said tubular body (2). The skylight further comprises a source of artificial light (9) external to the tubular body (2) to enable it not to interfere with the natural light, and mounted in the vicinity of the diffuser (6). This artificial-light source (9) is preferably defined by a plurality of LEDs positioned around the diffuser (6) itself.

Abstract: A light source for a crystal lamp has a light guide pillar, a light-emitting element, and a linear micro structure. The light guide pillar has a top surface, a bottom surface and a side surface, and the light-emitting element is disposed next to the bottom surface. The linear micro structure is formed on and surrounds the side surface, and the emitting light beams of the light-emitting element are reflected by or refracted through the linear micro structure to allow the linear micro structure to function as a thin-lined light source surrounding the light guide pillar.

Abstract: A one-way see-through illumination system is constructed from a light guide panel, a front-illumination image film, and a light injector. The light injector injects light into the light guide panel at a suitable angle for total internal reflection of the injected light at the surfaces of the light guide panel. The image film includes a half-toned front-illuminable image pattern that extracts light from the light guide panel. When active, light from the light guide panel front illuminates the image pattern for viewing by a front-side view, while a back-side viewer can see through the image pattern.

Abstract: A lighting device is disclosed that is configured for mounting in or on a motor vehicle. The lighting device comprises a light guiding element and a light source. The light guiding element has a light entry face and a light exit face. A depth of the lighting device perpendicular to the light exit face corresponds essentially fully to the depth of the light guiding element.

Abstract: A backlight device wherein LEDs which are arranged side by side at a first arrangement interval (P1) are provided to each LED unit. The LED units are mounted to a flexible board at a second arrangement interval. A light guide plate is disposed in such a manner that an end surface thereof is spaced from the LEDs by a distance (H). The light guide plate is disposed so as to satisfy the following relationship: first arrangement interval (P1)?distance (H)?second arrangement interval (P2). Specifically, the LEDs are arranged side by side in such a manner that the first arrangement interval (P1) is not less than 0.1 mm but not greater than 3 mm and the second arrangement interval (P2) is not less than 5 mm but not greater than 15 mm. The light guide plate is disposed in such a manner that the distance (H) is not less than 1 mm but not greater than 7 mm.

Abstract: Provided are planar lighting device that is excellent in luminance uniformity and light use efficiency and a display device including the planar lighting device.

Abstract: The present invention discloses a backlight module and a light guide plate thereof. The light guide plate has a side incident surface, a light-emitting surface adjacent to the side incident surface, and a micro-structure array adjacent to the side incident surface. The side incident surface receives incident lights from a light source. The micro-structure array has a plurality of elongated prisms, and an end of each of the prisms is oriented to the side incident surface, so that an extension direction of each prism is parallel to or nearly parallel to a normal line of a light-emitting surface of the light source. The light guide plate can increase light transmission distance to provide uniform brightness. The structures of the prisms are maintained in a uniform arrangement, so that a prism mold need not be re-designed to satisfy requirements of panels with different sizes.

Abstract: A light guide plate for a surface light source device is provided, which includes an incident surface configured to have light from lamps disposed along a predetermined axis, be incident thereon, an emitting surface configured to have the incident light emitted therefrom, a back surface configured to face the emitting surface, and a plurality of unit cells configured to have microprism patterns engraved thereon and distributed and arranged on the back surface. A crossing angle of a microprism arrangement axis, formed by a ridge direction of the microprism patterns, and of an arrangement axis of the lamps is disposed in an alternate angle. The light guide plate has a high front brightness and an excellent uniformity in brightness and does not have a moire phenomenon. In a backlight unit, the use of optical sheets stacked on the light guide plate can be reduced.

Abstract: An embodiment discloses a light emitting device package including a first lead frame and a second lead frame disposed spaced from each other, a light emitting device disposed on the first lead frame, and a reflective sidewall disposed on the first lead frame and the second lead frame to surround the light emitting device, wherein a portion of the reflective sidewall has a height higher than the other portion of the reflective sidewall.

Abstract: Disclosed are a mosaic light guide plate structure and a backlight module. The mosaic light guide plate structure comprises at least two light guide plate units. Each of the light guide plate units comprises a first tilt face and a second tilt face with cooperation of at least one light-emitting unit. The first tilt face is positioned at a side of the light guide plate unit. The second tilt face is oppositely positioned to the first tilt face at the other side. The at least one light-emitting unit is positioned under the first tilt face. The present invention assembles adjacent tilt faces to form the light guide plate and changes the direction of light with the tilt faces for solving issues of length limitation for the light guide plate. Accordingly, the mosaic light guide plate structure of the present invention can be suitable for large-scale LCDs and realize local dimming.

Abstract: To provide a DC/DC converter capable of down-sizing magnetic components and varying boosting and bucking ratios, and a bidirectional boosting-bucking operations, a bidirectional boosting-bucking magnetic-field cancellation type of DC/DC converter (10) is provided which includes: a first voltage side port (P1), a second voltage side port (P2); a common reference terminal (CP), a smoothing capacitor (C1), four switching elements (SW1, SW2, SW3, SW4), an inductors (L1, L2), a magnetic-field cancellation type transformer T including a primary winding (L3) and a secondary winging (L4), four switching elements (SW5, SW6, SW7, SW8), and a smoothing capacitor (C2).

Abstract: A primary power supply input can be supplied to each of gate driving units through individual transformers, respectively, from power supply terminals. One end of a primary winding of each of the transformers can be connected to the power supply terminal by power supply lines. In addition, the other end of each of the primary windings can be connected to one another by common connection lines to be further connected to a drain terminal of a MOSFET for controlling a current flowing in each of the primary windings. A gate power supply control circuit, to which an output current detected by an auxiliary winding of the transformer is fed back, can control a duty ratio for the on-off control of the MOSFET.

Abstract: A switching mode power supply (SMPS) includes a transformer having a primary winding, a secondary winding for providing an output voltage, and an auxiliary winding. The SMPS also includes a power switch coupled to the primary winding. A first control circuit is coupled to the secondary winding, and is configured to provide a first electrical signal to the secondary winding when the output voltage of the SMPS is less than a reference voltage during a discontinuous time, whereupon a second electrical signal is induced in the auxiliary winding. A second control circuit is coupled to the auxiliary winding and the power switch. The second control circuit is configured to regulate the output of the SMPS by controlling the power switch in response to a feedback voltage signal from the auxiliary winding, and is further configured to turn on the power switch in response to the second electrical signal.

Abstract: The invention relates to a control method implemented in a power converter, such as, for example, a variable speed drive. This control method is designed to make the power converter operate when the latter is connected to the network in single-phase mode. The power converter notably includes a controlled current source connected in series to its DC power supply bus. This controlled current source includes an electronic converter (2) provided with two controlled switching arms. The switching arms are controlled by alternating a modulation phase with a saturation phase, said saturation phase being applied for a determined duration (?) in order to make the power converter operate in discontinuous mode.

Abstract: The present disclosure relates to a multi-level inverter having a plurality of single inverter modules, the multi-level inverter including: a first controller providing a control signal to the multi-level inverter in response to voltage and frequency command based on detection of current and rotation speed of a motor; a second controller providing a control signal to the multi-level inverter in response to voltage and frequency command based on detection of current and rotation speed of a motor; and a plurality of single inverter modules converting an inputted AC power to DC power in response to the control signal from the first controller or the second controller, smoothing the converted DC power, converting the smoothed DC power to a three phase current in response to the control signal and outputting the three phase current.

Abstract: There is provided a circuit for discharging AC power including: a first rectifier rectifying AC power inputted from an AC power line; an electro-magnetic interference (EMI) removing unit installed between the AC power line and the first rectifier to suppress EMI of the AC power; a discharging signal generator generating a discharging signal from the AC power; and a discharging unit including a discharging resistor for discharging a voltage charged in the EMI removing unit according to the discharging signal, whereby standby power consumption may be reduced when the AC power is inputted and the voltage charged in a capacitor for removing EMI may be discharged to meet a predetermined safety standard when the AC power is blocked.

Abstract: An apparatus for delivering AC power to an AC load may include a plurality of inverters to receive direct current (DC) power from a respective DC power source and respectively provide AC power to an AC load. The apparatus may further include a first controller to generate a first control signal based on total AC current and total AC voltage being delivered to the AC load by the plurality of inverters. The apparatus may further include a plurality of secondary controllers to each receive the first control signal and each produce a respective secondary control signal based on the first control signal. The respective secondary control signal for each of the plurality of secondary controllers is configured to control a corresponding one of the plurality of inverters to provide a portion of the AC power.

Abstract: A boost converter comprises an inductance that receives an input signal. A switch controls current supplied by the inductance to a load. A power factor control module comprises a mode control module that selects an operating mode of the boost converter and a switch control module that switches the switch at a frequency. The frequency is equal to a first frequency when the mode control module selects a continuous mode and equal to a second frequency when the mode control module selects a discontinuous mode. The first frequency is greater than the second frequency.

Abstract: An electric machine drive system is described. The system includes an inverter, an electric machine coupled to the inverter by at least one output conductor and including a ground connection, and an active common mode current reducing device coupled between the ground connection of the electric machine and the inverter.

Abstract: An apparatus to deliver an alternating current (AC) power may include a controller having a processor and a memory. The apparatus may also include a plurality of power inverters in communication with the controller. Each power inverter may be configured to convert direct-current (DC) power into the (AC) power. Each of the plurality of power inverters may be configured to be controlled by the controller to generate AC power below at least one predetermined operating threshold. The plurality of power inverters may be configured to combine AC power generated by each of the plurality of power inverters, such that the combined AC power is delivered to a common AC load above the predetermined operating threshold. The apparatus may be arranged and operated according to a ratio of FMA=Fr/N, where Fr=fs/fl, fs is the switching frequency of the plurality of power inverters, fl is the frequency of the common AC load, and N is the number of power inverters of the apparatus.

Abstract: An image forming apparatus includes an image forming unit which forms an image, a power supply which converts input alternating current (AC) power and outputs direct current (DC) power having a predetermined level to operate the image forming unit; a mechanical power switch through which the AC power is supplied and/or shut off, a switch circuit unit which includes a soft power switch to select a turned-on status and/or a turned-off status in accordance with a user's handling, and outputs a switch signal corresponding to a status of the soft power switch, a power controller which selectively supplies the DC power from the power supply to the image forming unit on the basis of the switch signal, and a discharging circuit unit which discharges remaining power of the power supply if the AC power is shut off by the mechanical power switch. Accordingly, a user may quickly turn on/off power using a power switch, and mistaken malfunction may be prevented.

Abstract: A power converting apparatus comprises a DC-DC converter circuit that steps up or steps down an input voltage from a DC power supply, a DC-AC converter circuit that converts an intermediate voltage outputted by the DC-DC converter circuit to an alternate current, and a control circuit that controls the DC-DC converter circuit and the DC-AC converter circuit. The control circuit is provided with a circuit control unit that controls the DC-DC converter circuit so that the modulation factor, which is the amplitude ratio between a signal wave for manipulating the DC-AC converter circuit and the carrier wave therefor, will become a target modulation factor.

Abstract: A semiconductor memory device includes: a plurality of mats; a plurality of sense amplifier regions disposed on a side of the plurality of mats; and a plurality of main bit lines overlapping with a plurality of secondary bit lines, respectively, in regions for the plurality of mats, wherein the plurality of main bit lines and the plurality of secondary bit lines are formed in regions for the plurality of mats and the plurality of sense amplifier regions.

Abstract: A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

Abstract: A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract: The present invention relates to a memory device having 4F2 size cells and a method for fabricating the same. The memory device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other, and plural memory cells having a transistor that fills a groove between two adjoining memory cells in a direction of the bit lines. A side wall between the two adjoining memory cells is simultaneously covered by an insulating film formed between the gate terminal and the two memory cells. The gate terminal is connected electrically to a word line, drain terminals of two adjoining memory cells are connected electrically to a bit line, and the gate and drain terminals are alternately arranged. One of the plural memory cells is buried in the substrate, and is electrically connected with a substrate or a well formed in the substrate.

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states.

Abstract: Provided is a memory cell including: a ferroelectric transistor; a plurality of switching elements electrically connected to the ferroelectric transistor; and a plurality of control lines for transmitting individual control signals to each of the plurality of switching element for separately controlling the plurality of switching elements. The plurality of switching elements are configured to be separately controlled on the basis of the individual control signals so as to prevent each electrode of the ferroelectric transistor from being floated.

Abstract: A memory system includes a memory cell array including a plurality of memory cells electrically connected to pairs of bit lines once a word line is activated; latch portions connected to respective pairs of bit lines; a sense amplifier connected to the latch portions; and a control circuit configured to control the latch portions for a reading operation in order that data in all memory cells connected to the word line, once selected, come to be held in the corresponding latch portions as a group.

Abstract: Logic circuits based, at least in part, on use of spin-torque transfer (STT) to switch the magnetization—and hence the logic state—of a magnetic material are disclosed. Aspects of the invention include novel STT-based switching devices, new configurations of known STT-based devices into useful logic circuits, common logic circuits and system building blocks based on these new devices and configurations, as well as methods for inexpensively mass-producing such devices and circuits.

Abstract: Method and apparatus for writing data to a magnetic memory element, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a multi-level cell (MLC) magnetic memory cell stack has first and second magnetic memory elements connected to a first control line and a switching device connected to a second control line. The first memory element is connected in parallel with the second memory element, and the first and second memory elements are connected in series with the switching device. The first and second memory elements are further disposed at different non-overlapping elevations within the stack. Programming currents are passed between the first and second control lines to concurrently set the first and second magnetic memory elements to different programmed resistances.

Abstract: A magnetic memory element and a method of driving such an element are disclosed. The magnetic memory element has a magnetic tunnel junction portion with a spin-valve structure having a perpendicular magnetization free layer formed of a perpendicular magnetization film, a perpendicular magnetization pinned layer formed of a perpendicular magnetization film, and a nonmagnetic layer sandwiched between the perpendicular magnetization free layer and the perpendicular magnetization pinned layer, and records information by application of an electric pulse to the magnetic tunnel junction portion. An in-plane magnetization film, interposed in the path of the electric pulse, is disposed in the magnetic tunnel junction portion. The in-plane magnetization film is configured so as to exhibit antiferromagnetic (low-temperature)-ferromagnetic (high-temperature) phase transitions depending on temperature changes based on application of the electric pulse to the magnetic tunnel junction portion.

Abstract: Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices.

Abstract: In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M>n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M>n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M>n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

Abstract: The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device.

Abstract: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.

Abstract: A memory device comprising: a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material capable of receiving electrons and holes, and able to perform storage of electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material capable of performing storage of electrical charges, a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.

Abstract: In one embodiment, the method for reading memory cells in an array of non-volatile memory cells includes reading data from a memory cell using a set of hard decision voltages and at least a first set of soft decision voltages based on a single read command.

Abstract: A non-volatile memory device performs a read operation for compensating for coupling due to an adjacent memory cell. With the read operation of the non-volatile memory device, the coupling effect included in a read result of the selected memory cell is compensated on the basis of a program state of an adjacent memory cell adjacent to the selected memory cell. Toward this end, a read operation for the adjacent memory cell is selectively performed before the selected memory cell is read. Upon sensing of data from the selected memory cell, one or more read operations for the selected memory cell are performed according to the program state of the adjacent memory cell with a read voltage being changed in level depending on the program state of the adjacent memory cell.

Abstract: A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A memory system includes: a plurality of banks each including a memory cell array and a sense amplifier; a buffer circuit electrically connected to the plurality of banks; a switch circuit configured to switch on and off an electrical connection between the buffer circuit and each of the plurality of banks an interface electrically connected to the buffer circuit; and a controller configured to control the plurality of banks, the buffer circuit, the switch circuit and the interface, wherein for reading data held in the memory cell array by outputting the data to the interface in 5 clock cycles, the controller is configured to control the switch circuit in order that the switch circuit electrically connects a selected one of the banks to the buffer circuit upon the lapse of 1.5 clock cycles after a clock is inputted into the selected bank.

Abstract: A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage.

Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.