Abstract: In a Schottky electrode formation region on a nitride semiconductor, the total length of junctions of Schottky electrodes and a surface of a nitride semiconductor layer is longer than the perimeter of the Schottky electrode formation region. The total length is preferably 10 times longer than the perimeter. For example, the Schottky electrodes are formed concentrically and circularly.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.

Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: A light emitting element has an anode, a cathode, a light emitting layer which is provided between the anode and the cathode and emits light by energizing the anode and the cathode, and a functional layer (a hole injecting layer and a hole transporting layer) which is provided between the anode and the light emitting layer in contact therewith and has a function of transporting a hole, in which the hole injecting layer and the hole transporting layer each are constituted including an electron transporting material having electron transporting properties. The content of the electron transporting material contained in the hole injecting layer and the content thereof contained in the hole transporting layer are different from each other.

Abstract: A highly reliable light-emitting device or lighting device is provided. Further, a light-emitting device or lighting device with a high manufacturing yield is provided. Provided is a light-emitting device having a contact structure which includes a separation layer having a shape typified by a reverse tapered shape in which an outline of the bottom portion is inside an outline of an upper portion and which utilizes the difference between an amount of a light-emitting layer extending inside the outline and that of an upper electrode extending inside the outline. Further, when the outline of the separation layer which forms the contact portion has a depression and a projection, the length of the contact portion can be increased, and thus, contact resistance can be reduced.

Abstract: A light emitting diode package includes a first lead frame comprising a first hole cup, a second lead frame comprising a second hole cup and disposed to face the first lead frame with a gap disposed between the first lead frame and the second lead frame, a first light emitting diode chip disposed on the first hole cup, and a second light emitting diode chip disposed on the second hole cup, the first lead frame comprising a first enlarged region formed between the gap and the first hole cup, and the second lead frame comprising a second enlarged region formed between the gap and the second hole cup.

Abstract: Ceramic diode carriers (10) comprising a ceramic carrier body (2) integrally connected to ceramic cooling elements (7) dissipating heat, wherein sintered metallization regions (41) are disposed as conductors on the surface (3) of the carrier body (2). LEDs (13) can be fastened to the diode carrier (10), the electrical connections thereof being electrically connectable to the conductors. In order to produce luminous bodies from ceramic diode carriers (10), at least two identical ceramic diode carriers (10) are connected into an array.

Abstract: A light emitting unit including plural kinds of light emitting elements with different light emitting wavelengths, wherein, among the light emitting elements, at least one kind of light emitting element includes a semiconductor layer configured by laminating a first conductive layer, an active layer and a second conductive layer and having a side surface exposed by the first conductive layer, the active layer and the second conductive layer; a first electrode electrically connected to the first conductive layer; a second electrode electrically connected to the second conductive layer; a first insulation layer contacting at least an exposed surface of the active layer in the surface of the semiconductor layer; and a metal layer contacting at least a surface, which is opposite to the exposed surface of the active layer, in the surface of the first insulation layer, and electrically separated from the first electrode and the second electrode.

Abstract: To provide a display device with low power consumption. The display device includes a plurality of pixels each having a light-emitting element having a structure in which light emitted from a light-emitting layer is resonated between a reflective electrode and a light-transmitting electrode, wherein no color filter layers are provided or color filter layers with high transmittance are provided in pixels for light with relatively short wavelengths (e.g., pixels for blue and/or green), and a color filter layer is selectively provided in pixels for light with a long wavelength (e.g., pixels for red), and thereby maintaining color reproducibility and consuming less power.

Abstract: Provided are a light emitting device, a light emitting device package, and a lighting apparatus. The light emitting device includes: an n-type semiconductor layer including a first area and a second area in a plane; an active layer disposed on the n-type semiconductor layer in the first area; an electron barrier layer disposed on the active layer in the first area; and a p-type semiconductor layer disposed on the electron barrier layer in the first area.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes a first electrode layer having electrical continuity with the first semiconductor layer and a second electrode layer provided on the second semiconductor layer, the second electrode layer including a metal portion having a thickness not less than 10 nanometers and not more than 100 nanometers along a direction from the first semiconductor layer to the second semiconductor layer.

Abstract: A front side emitting type organic light-emitting display device includes a substrate; an anode electrode formed over the substrate; an organic layer formed over the anode electrode; a cathode electrode formed over the organic layer; a pair of transparent conductive oxide layers disposed over the cathode electrode; and a metal layer interposed between the pair of transparent conductive oxide layers.

Abstract: To provide a substrate which is light and has high reliability and high light extraction efficiency from an organic EL element. To provide a substrate which includes a protective layer in a resin layer, an uneven structure on a light incident surface, and an opening which surrounds the uneven structure and through which the protective layer is exposed. To provide a light-emitting device which includes a resin layer provided with an uneven structure on a light incident surface over a protective layer, and a light-emitting element in the protective layer and a counter substrate which are bonded with a sealant. The protective layer and the resin layer have a property of transmitting visible light. The light-emitting element includes a light-transmitting first electrode over a resin layer, a layer containing a light-transmitting organic compound over the first electrode, and a second electrode over the layer containing a light-transmitting organic compound.

Abstract: A light emitting diode (LED) device and packaging for same is disclosed. In some aspects, the LED is manufactured using a vertical configuration including a plurality of layers. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids design problems, including manufacturing complexities, costs and heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate or wafer stacked over a semiconductor LED and positioned using one or more alignment markers.

Abstract: An LED light emitting device is provided that has high color rendering properties and is excellent color uniformity and, at the same time, can realize even luminescence unattainable by conventional techniques. A phosphor having a composition represented by formula: (Sr2-X-Y-Z-?BaXMgYMnZEu?)SiO4 wherein x, y, z, and u are respectively coefficients satisfying 0.1<x<1, 0<y<0.5, 0<z<0.1, y>z, and 0.01<?<0.2. is provided. The phosphor is used in combination with ultraviolet and blue light emitting diodes having a luminescence peak wavelength of 360 to 470 nm to form an LED light emitting device.

Abstract: A light-emitting diode structure includes a base with a recessed portion, a light-emitting chip and a light-transmissive block. The light-emitting chip disposed in the recessed portion of the base and emits a light beam. The light-transmissive block disposed on the base covers the recessed portion and the light-emitting chip, so that the light beam emitted from the light-emitting chip is radiated outwardly via the light-transmissive block. The light-transmissive block is a flat-top multilateral cone including a bottom surface, a top surface, and several side surfaces connected to and located between the bottom surface and the top surface. A slot with a bottom portion is formed on the top surface of the light-transmissive block.

Abstract: A semiconductor, room-temperature, electrically excited, two-photon device with thick optically active layer is provided. The intrinsic AlGaAs active layer is sandwiched between two intrinsic graded waveguide layers having increased aluminum concentration at increased distance from the active layer. The waveguide structure is sandwiched between two cladding layers of high aluminum concentration, n and p doped respectively. The structure is epitaxially grown on a substrate and further comprises other layers such as buffer, graded layers and contact layers. An etched ridge provides lateral confinement for light. The device provides two-photons gain and may be used in light sources, optical amplifiers, pulse compressors and lasers.

Abstract: According to one embodiment, a semiconductor light emitting device includes a structure, a first electrode layer, and a second electrode layer. The structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode layer is provided on the first semiconductor layer side of the structure. The first electrode layer is made of metal and contains a portion contacting the first semiconductor layer. The second electrode layer is provided on the second semiconductor layer side of the structure. The second electrode layer has a metal portion with a thickness of not less than 10 nanometers and not more than 50 nanometers, and a plurality of openings piercing the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers.

Abstract: According to an embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type different from the first conductivity type, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device includes a first layer, a first electrode, a second electrode and a third electrode. The first layer is provided on a surface of the second semiconductor layer opposite to the light emitting layer and including conductive oxide. The first electrode is in contact with a part of the first layer and includes a reducible element for reducing the conductive oxide. The second electrode includes a first portion covering the first electrode and a second portion being in contact with the first layer, and the third electrode is electrically connected to the first semiconductor layer.

Abstract: The present disclosure relates to a semiconductor light-emitting device, which includes: a first semiconductor layer having first conductivity; a second semiconductor layer having second conductivity different from the first conductivity; an active layer disposed between the first semiconductor layer and the second semiconductor layer and generating light by recombination of electrons and holes; a first pad electrode electrically connected to the second semiconductor layer; a high-resistance body partially disposed on the second semiconductor layer; and a branch electrode disposed on the second semiconductor layer, partially extending over the high-resistance body, and electrically connected to the first pad electrode.

Abstract: The present disclosure relates to methods for tuning the work function of a metal nanostructure-based conductive film by forming a dipole surface layer on individual metal nanostructures.

Abstract: Provided is a semiconductor light emitting device. The semiconductor light emitting device includes: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; an insulation layer on the second conductive semiconductor layer and including a first hole therein; a second electrode on the second conductive semiconductor layer; and a first electrode on the insulation layer and including a connection portion electrically connected to the first conductive semiconductor layer. The second electrode includes a plurality of line patterns. The connection portion of the first electrode is disposed between the plurality of line patterns of the second electrode and is disposed in the first hole of the insulation layer.

Abstract: An opto-electronic component has a carrier element (3) with a connection region (5). Arranged on the carrier element (3) is a semiconductor chip (7). A contact region (10) is mounted on the surface (8) of the semiconductor chip (7) remote from the carrier element (3). The connection region (5) is electrically conductively connected to the contact region (10) by way of an unsupported conductive structure (13). A method for manufacturing an opto-electronic component is described.

Abstract: The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size.

Abstract: A method of fabrication of barrier diode based infrared detectors, utilizing the growth of unstrained, not relaxed III-V compound semiconductor material layers having a lattice constant over 6 Angstrom, is provided. The growth is performed by the means of Molecular Beam Epitaxy (MBE) or Metal-Organic Vapor Phase Epitaxy (MOVPE). The method comprises the use of bulk crystalline substrates and the growth of a transitional layer of GaInAsSb with graded composition, followed by an optional thick layer of GaInAsSb of constant composition, lattice matched to the said III-V compound semiconductor material layers, the said optional layer of GaInAsSb of constant composition serving as a virtual substrate. The method provides high crystalline quality layers suitable for semiconductor device fabrication that can effectively interact with electromagnetic radiation of the mid-infrared spectral range with a wavelength between about 2 micrometers to about 16 micrometers.

Abstract: In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: A multiple field plate transistor includes an active region, with a source, drain, and gate. A first spacer layer is between the source and the gate and a second spacer layer between the drain and the gate. A first field plate on the first spacer layer and a second field plate on the second spacer layer are connected to the gate. A third field plate connected to the source is on a third spacer layer, which is on the gate and the first and second field plates and spacer layers. The transistor exhibits a blocking voltage of at least 600 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 5.0 or 5.3 m?-cm2, respectively, and at least 900 Volts while supporting current of at least 2 or 3 Amps with on resistance of no more than 6.6 or 7.0 m?-cm2, respectively.

Abstract: The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

Abstract: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract: A biochemical sensor and a method of manufacturing the same are disclosed. The biochemical sensor includes a substrate, a gate arranged on one side of the substrate, a gate insulating layer arranged on one side of the gate opposite to the substrate, an active layer arranged on one side of the gate insulating layer opposite to the gate, a source and a drain arranged on one side of the active layer opposite to the gate insulating layer, and a biochemical sensing layer arranged on one side of the active layer opposite to the gate insulating layer and between the source and the drain.

Abstract: A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

Abstract: An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.

Abstract: In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.

Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.

Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.

Abstract: A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.

Abstract: A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

Abstract: Thin film transistors (TFT) and methods of manufacturing the same. A TFT includes a line-shaped gate of uniform thickness. A cross-section of the gate is curved where a side surface and a top surface meet. The gate includes one, or two or more gate lines.

Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.