Abstract: A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) thrilled over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material.

Abstract: An example embodiment relates to a transistor including a channel layer. A channel layer of the transistor may include a plurality of unit layers spaced apart from each other in a vertical direction. Each of the unit layers may include a plurality of unit channels spaced apart from each other in a horizontal direction. The unit channels in each unit layer may form a stripe pattern. Each of the unit channels may include a plurality of nanostructures. Each nanostructure may have a nanotube or nanowire structure, for example a carbon nanotube (CNT).

Abstract: This invention relates light-emitting diode displays with silmple structure and fabricating method as well as excellent efficiency. In an embodiment, the display features a nanorod LED array arranged on a substrate and divided into a first, second, and third sub-pixels. Two electrodes are preferably arranged in a vertical configuration for driving the sub-pixels. In another embodiment, a method features the sub-pixels for emitting multi-primary colors being formed on a conductive substrate and thus simplifies the steps.

Abstract: A light-receiving element includes a group III-V compound semiconductor stacked structure that includes an absorption layer having a pn-junction therein. The stacked structure is formed on a group III-V compound semiconductor substrate. The absorption layer has a multi- quantum well structure composed of group III-V compound semiconductors, and the pn-junction is formed by selectively diffusing an impurity element into the absorption layer. A diffusion concentration distribution control layer composed of a III-V group semiconductor is disposed in contact with the absorption layer on a side of the absorption layer opposite the side adjacent to the group III-V compound semiconductor substrate. The bandgap energy of the diffusion concentration distribution control layer is smaller than that of the group III-V compound semiconductor substrate. The concentration of the impurity element selectively diffused in the diffusion concentration distribution control layer is 5×1016/cm3 or less toward the absorption layer.

Abstract: A photodetector includes one or more photodiodes and a signal processing circuit. Each photodiode includes a transparent first electrode, a second electrode, and a heterojunction interposed between the first electrode and the second electrode. Each heterojunction includes a quantum dot layer and a fullerene layer disposed directly on the quantum dot layer. The signal processing circuit is in signal communication each the second electrode. The photodetector may be responsive to wavelengths in the infrared, visible, and/or ultraviolet ranges. The quantum dot layer may be treated with a chemistry that increases the charge carrier mobility of the quantum dot layer.

Abstract: Integrated circuit multilayer integration techniques are provided. In one aspect, a method of fabricating an integrated circuit is provided. The method includes the following steps. A substrate is provided. A plurality of interconnect layers are formed on the substrate arranged in a stack, each interconnect layer comprising one or more metal lines, wherein the metal lines in a given one of the interconnect layers are larger than the metal lines in the interconnect layers, if present, above the given interconnect layer in the stack and wherein the metal lines in the given interconnect layer are smaller than the metal lines in the interconnect layers, if present, below the given interconnect layer in the stack. At least one transistor is formed on a top-most layer of the stack.

Abstract: Biodegradable electronic devices may include a biodegradable semiconducting material and a biodegradable substrate layer for providing mechanical support to the biodegradable semiconducting material.

Abstract: The present invention relates to a method and a device for providing a current of spin-polarised electrons. More particularly, the present invention is suited for use in spin electronics or detection of spin-polarised electrons.

Abstract: Provided are an organic electroluminescence device having high current efficiency and a long lifetime, and a biscarbazole derivative for realizing the device. The biscarbazole derivative has a specific substituent. The organic EL device has a plurality of organic thin-film layers including a light emitting layer between a cathode and an anode, and at least one layer of the organic thin-film layers contains the biscarbazole derivative.

Abstract: An organic semiconductive material comprising at least one matrix material and at least one doping material, wherein the doping material is selected from an organic compound and wherein the matrix material is selected from an diamine compound, also an organic component and a mixture for producing a doped semiconductor layer.

Abstract: A light-emitting element includes an anode, a cathode, a luminescent layer that is disposed between the anode and the cathode and emits light by applying a current between the anode and the cathode, and an organic layer that is disposed in contact with the anode and the luminescent layer between the anode and the luminescent layer and functions to transport holes. The organic layer includes a hole injection layer and a hole transport layer. The hole injection layer and the hole transport layer each contain an electron transport material that can transport electrons. The electron transport material content in the hole injection layer is different from that in the hole transport layer.

Abstract: A triarylamine derivative represented by a general formula (G1) given below is provided. Note that in the formula, Ar represents either a substituted or unsubstituted phenyl group or a substituted or unsubstituted biphenyl group; ? represents a substituted or unsubstituted naphthyl group; ? represents either hydrogen or a substituted or unsubstituted naphthyl group; n and m each independently represent 1 or 2; and R1 to R8 each independently represent any of hydrogen, an alkyl group having 1 to 6 carbon atoms, or a phenyl group.

Abstract: Embodiments include memory cells having an oxide material in contact with a metal material. In one embodiment, a memory cell includes titanium nitride, titanium oxynitride in contact with the titanium nitride and copper in contact with the titanium oxynitride. A plurality of such memory cells and respective access devices can be included in a memory array. The memory cell and access device are electrically connected between an access line and a data/sense line. An array can include a plurality of memory cells vertically stacked with respective access devices. Embodiments also include methods of forming memory cells and arrays and stacking memory arrays over one another.

Abstract: A thin film transistor array panel and a manufacturing method capable of forming an insulating layer made of different materials for a portion contacting an oxide semiconductor and a second portion without an additional process. The thin film transistor array panel includes: a gate electrode; a source electrode and a drain electrode spaced apart from each other, each of the source and drain electrodes comprising a lower layer and an upper layer; an insulating layer disposed between the gate electrode and the source and drain electrodes; a semiconductor, the source electrode and the drain electrode being electrically connected to the semiconductor; a first passivation layer contacting the lower layer of the source and drain electrodes but not contacting the upper layer of the source and drain electrodes; and a second passivation layer disposed on the upper layer of the source and drain electrodes.

Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.

Abstract: By using a coating method, which is a method of manufacturing a transparent conductive film, with low-temperature heating lower than 300° C., a transparent conductive film with excellent transparency, conductivity, film strength, and resistance stability and a method of manufacturing this film are provided. In the method of manufacturing a transparent conductive film, a heat energy ray irradiating step is a step of irradiating with the energy rays while heating under an oxygen-containing atmosphere to a heating temperature lower than 300° C. to form the inorganic film, and the plasma processing step is a step of performing the plasma processing on the inorganic film under a non-oxidizing gas atmosphere at a substrate temperature lower than 300° C. to promote mineralization or crystallization of the film, thereby forming a conductive oxide fine-particle layer densely packed with conductive oxide fine particles having a metal oxide as a main component.

Abstract: The present invention generally relates to an offset electrode TFT and a method of its manufacture. The offset electrode TFT is a TFT in which one electrode, either the source or the drain, surrounds the other electrode. The gate electrode continues to be below both the source and the drain electrodes. By redesigning the TFT, less voltage is necessary to transfer the voltage from the source to the drain electrode as compared to traditional bottom gate TFTs or top gate TFTs. The offset electrode TFT structure is applicable not only to silicon based TFTs, but also to transparent TFTs that include metal oxides such as zinc oxide or IGZO and metal oxynitrides such as ZnON.

Abstract: A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor.

Abstract: Provided is a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which a semiconductor film whose threshold voltage is difficult to control is used as an active layer. By using a silicon oxide film having a negative fixed charge as a film in contact with the active layer of the transistor or a film in the vicinity of the active layer, a negative electric field is always applied to the active layer due to the negative fixed charge and the threshold voltage of the transistor can be shifted in the positive direction. Thus, the highly reliable semiconductor device can be manufactured by giving stable electric characteristics to the transistor.

Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

Abstract: A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.

Abstract: The present invention provides a thin-film transistor capable of high-speed operation, a process for producing the same, and a display device including the same. The thin-film transistor of the present invention includes, on a substrate, in the order of: a gate electrode; a gate insulating film; an oxide semiconductor film; and a protective insulating film, the protective insulating film having a planar shape that is completely or substantially the same as the planar shape of the gate electrode.

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract: A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.

Abstract: A semiconductor device of the present invention includes a gate electrode which includes a pair of first protrusions and a second protrusion provided between the pair of first protrusions; a gate insulating film covering the gate electrode; a semiconductor film which is in contact with the gate insulating film and overlaps with the pair of first protrusions and the second protrusion; and a pair of electrodes which is in contact with the semiconductor film and overlaps with the pair of first protrusions. The side edges of the semiconductor film are on the outer sides than the top surfaces of the pair of first protrusions in the direction of the channel width of the semiconductor film. The side edges of the pair of electrodes are on the outer sides than the top surfaces of the pair of first protrusions in the direction of the channel width of the semiconductor film.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: Disclosed is a thin film transistor substrate which is provided with: a plurality of source lines 11a provided to extend parallel to a substrate 10; a plurality of gate lines 13a provided to extend parallel to each other in the direction that intersects the source lines 11a; and a plurality of pixel electrodes 17a, which are arranged in a matrix along the direction wherein the source lines 11a extend and in the direction wherein the gate lines 13a extend. On each gate line 13a, a through hole Ha is provided at a part where each gate line intersects each source line 11a, and inside of the through hole Ha, a semiconductor layer 15a is provided with a gate insulating film 14a therebetween.

Abstract: Thin film transistor devices comprising a dielectric component and an inorganic semiconductor component coupled thereto, wherein said coupled inorganic semiconductor component is obtainable by a process that comprises contact of said dielectric component and a fluid medium comprising said inorganic semiconductor component.

Abstract: Disclosed is a display device including: a gate electrode; a semiconductor layer formed into an island shape on an upper side of the gate electrode; a side wall oxide film formed on a lateral surface of the semiconductor layer; and a drain electrode and a source electrode formed on an upper side of the semiconductor layer extending from a lateral side of the semiconductor layer, wherein the side wall oxide film has a thickness of 2.1 nm or more.

Abstract: Disclosed is a thin film transistor wherein an ON current is increased and a leak current is reduced. The channel layer 60 of the TFT 10 is formed of a crystalline silicon, and the lower surface of one end of the channel layer 60 is electrically connected to the surface of an n+ silicon layer 40a, and the lower surface of the other end is electrically connected to the surface of an n+ silicon layer 40b. Furthermore, the side surface of said end of the channel layer 60 is electrically connected to a source electrode 50a, and the side surface of the other end is electrically connected to a drain electrode 50b. Thus, a barrier that makes electrons, which act as carriers, not easily transferred is formed on the boundary between the source electrode 50a and the channel layer 60. As a result, the ON current that flows when the TFT 10 is in the ON state can be increased, and the leak current that flows when the TFT is in the OFF state can be reduced.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.

Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Abstract: A III-N semiconductor device can include an electrode-defining layer having a thickness on a surface of a III-N material structure. The electrode-defining layer has a recess with a sidewall, the sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a first width, and a portion of the recess proximal to the III-N material structure has a second width, the first width being larger than the second width. An electrode is in the recess, the electrode including an extending portion over the sidewall of the recess. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The sidewall forms an effective angle of about 40 degrees or less relative to the surface of the III-N material structure.

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.

Abstract: An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer. The first n-type GaN layer, the connecting layer, and the second n-type GaN layer are formed on the substrate in sequence. The connecting layer is etchable by alkaline solution, and a bottom surface of the second n-type GaN layer facing towards the connecting layer has a roughed exposed portion. The GaN on the bottom surface of the second n-type GaN layer is N-face GaN. A top surface of the second n-type GaN layer facing away from the connecting layer includes a first area and a second area. The light emitting layer and the p-type GaN layer are formed on the first area of the top surface of the second n-type GaN layer in sequence.

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor.

Abstract: A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked.

Abstract: Disclosed is a novel method for group III polarity growth on a sapphire substrate. Specifically disclosed is a method for producing a laminate wherein a group III nitride single crystal layer is laminated on a sapphire substrate by an MOCVD method.

Abstract: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

Abstract: A semiconductor device comprises: a semiconductor substrate located on an insulating layer; and an insulator located on the insulating layer and embedded in the semiconductor substrate, wherein the insulator applies stress therein to the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a cavity within the semiconductor substrate so as to expose the insulating layer; forming an insulator in the cavity, wherein the insulator applies stress therein to the semiconductor substrate. It facilitates the reduction of the short channel effect, the resistance of source/drain regions and parasitic capacitance.

Abstract: A semiconductor rectifying device of an embodiment includes a first-conductive-type semiconductor substrate made of a wide bandgap semiconductor, a first-conductive-type semiconductor layer formed on an upper surface of the semiconductor substrate and made of the wide bandgap semiconductor having an impurity concentration lower than that of the semiconductor substrate, a first-conductive-type first semiconductor region formed at a surface of the semiconductor layer and made of the wide bandgap semiconductor, a second-conductive-type second semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor, a second-conductive-type third semiconductor region formed around the first semiconductor region and made of the wide bandgap semiconductor having a junction depth deeper than a junction depth of the second semiconductor region, a first electrode that is formed on the first, second, and third semiconductor regions, and a second electrode formed on a lower surface of

Abstract: A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm3 and 5E+16 atoms/cm3 inclusive, and a thickness thereof is 8 ?m or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 ?m or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Abstract: LED devices and methods for making such devices are provided. One such method may include forming epitaxially a substantially single crystal SiC layer on a substantially single crystal Si wafer, forming epitaxially a substantially single crystal diamond layer on the SiC layer, doping the diamond layer to form a conductive diamond layer, removing the Si wafer to expose the SiC layer opposite to the conductive diamond layer, forming epitaxially a plurality of semiconductor layers on the SiC layer such that at least one of the semiconductive layers contacts the SiC layer, and coupling an n-type electrode to at least one of the semiconductor layers such that the plurality of semiconductor layers is functionally located between the conductive diamond layer and the n-type electrode.

Abstract: Marking of an SiC wafer with an identifier is realized by irradiation with a pulsed laser using a harmonic of a wavelength four times that of a YAG laser. A speed at which a laser head moves, an orbit in which the laser head moves, the output power and Q-switch frequency of a pulsed laser to be applied, and the like are determined such that pulse-irradiated marks formed as a result of irradiation with corresponding pulses of the pulsed laser do not overlap each other.

Abstract: A semiconductor device includes a semiconductor substrate including a collector layer of a first conductivity type and a drift layer of a second conductivity type in contact with said collector layer, said drift layer receiving a supply of carriers from said collector layer. The semiconductor device further includes a lattice defect formed to penetrate through said semiconductor substrate and enclose a predetermined portion of said semiconductor substrate, a sense emitter electrode formed on the top surface of said predetermined portion, and a collector electrode formed on the bottom surface of said predetermined portion.