Abstract: The present disclosure provides a tunneling device, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; and a gate stack formed on the channel region and a first side wall and a second side wall formed on two sides of the gate stack, wherein the gate stack comprises: a first gate dielectric layer; at least a first gate electrode and a second gate electrode formed on the first gate dielectric layer; a second gate dielectric layer formed between the first gate electrode and the first side wall; and a third gate dielectric layer formed between the second gate electrode and the second side wall.

Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

Abstract: A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.

Abstract: The present disclosure provides a TFET, which comprises: a substrate; a channel region formed in the substrate, and a source region and a drain region formed on two sides of the channel region; a gate stack formed on the channel region, wherein the gate stack comprises: a gate dielectric layer, and at least a first gate electrode and a second gate electrode distributed in a direction from the source region to the drain region and formed on the gate dielectric layer, and the first gate electrode and the second gate electrode have different work functions; and a first side wall and a second side wall formed on a side of the first gate electrode and on a side of the second gate electrode respectively.

Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.

Abstract: A semiconductor device includes a first device region formed over a semiconductor substrate and defined by a device isolation region, a first transistor including a first gate electrode formed over the first device region, a first source region formed in the first device region on a first side of the gate electrode, and a first drain region formed in the first device region on a second side of the first gate electrode, a first pattern formed over the device isolation region on the first side of the first gate electrode in parallel with the first gate electrode, and a first conductor plug connected to the first source region. The first conductor plug is electrically connected to one of a ground line and a power source line, and the first pattern is electrically connected to the other of the ground line and the power source line.

Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

Abstract: A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

Abstract: The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a power line, and each cell of a second subset of ROM cells has a source electrically isolated.

Abstract: One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

Abstract: A method for manufacturing a metal gate structure includes providing a substrate having a high-K gate dielectric layer and a bottom barrier layer sequentially formed thereon, forming a work function metal layer on the substrate, and performing an anneal treatment to the work function metal layer in-situ.

Abstract: The present invention relates to a method for manufacturing a contact and a semiconductor device having said contact. The present invention proposes to form first a trench contract of relatively large size, then to form one or more dielectric layer(s) within the trench contact, and then to remove the upper part of the dielectric layer(s) and to fill the same with a conductive material. The use of such a method makes it easy to form a trench contact of relatively large size which is easy for manufacturing; besides, since dielectric layer(s) is/are formed in the trench contact, thence capacitance between a source/drain trench contact and a gate electrode is reduced accordingly.

Abstract: A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region.

Abstract: A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.

Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.

Abstract: A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.

Abstract: An integrated circuit includes an antenna, a die manufactured from a semiconducting material, an RF energy collection and processing means disposed on or within said die and including at least a receiver and a processing means, an input configured to supply power to said RF energy collection and processing means and an output for operative communication by said RF energy collection and processing means. The integrated circuit is configurable and operable to provide at least one of electromagnetic emission anomaly detection, tamper detection, anti-tamper monitoring, degradation monitoring, health monitoring, counterfeit detection, software changes monitoring, firmware changes monitoring and monitoring of other RF energy anomalies.

Abstract: The detection device includes a semiconductor substrate of a first conductivity type. A matrix of photodiodes organized along a first organization axis is formed on the substrate. Each photodiode is at least partially formed in the substrate. A peripheral biasing ring is formed around the photodiode matrix. The biasing ring is connected to a bias voltage generator. An electrically conducting contact is connected to the substrate and arranged between two photodiodes on the first organization axis. The distance separating the contact from each of the two photodiodes is equal to the distance separating two adjacent photodiodes along the first organization axis. The contact is connected to the bias voltage generator.

Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an insulating film, a heat conductive member, and an element. A cavity and a connecting hole are formed in the semiconductor substrate. The connecting hole spatially connects the cavity to an upper face of the semiconductor substrate. The insulating film is provided on inner faces of the cavity and the connecting hole. The heat conductive member is embedded in the cavity and the connecting hole. Heat conductivity of the heat conductive member is higher than heat conductivity of the insulating film. And, the element is formed in a region immediately above the cavity in the semiconductor substrate.

Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.

Abstract: Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

Abstract: A region-divided substrate includes: a substrate having a first surface and a second surface opposite to the first surface and having a plurality of partial regions, which are divided by a plurality of trenches, wherein each trench penetrates the substrate from the first surface to the second surface; a conductive layer having an electrical conductivity higher than the substrate and disposed on a sidewall of one of the plurality of partial regions from the first surface to the second surface; and an insulator embedded in each trench.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract: Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.

Abstract: In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

Abstract: According to one disclosed embodiment, a power semiconductor package includes an insulated-gate bipolar transistor (IGBT) residing on a package substrate, where the IGBT includes a plurality of solderable front metal (SFM) coated emitter segments situated atop the IGBT and connected to an emitter of the IGBT. The power semiconductor package also includes a conductive clip coupling the plurality of SFM coated emitter segments to an emitter pad on the package substrate. Additionally, the power semiconductor package includes a gate pad on the package substrate coupled to a gate of the IGBT, a collector pad on the package substrate situated under the IGBT and coupled to a collector of the IGBT, and an emitter terminal, a collector terminal and a gate terminal of the package substrate that are routed to the emitter pad, collector pad, and gate pad, respectively.

Abstract: A thin-film semiconductor component includes a carrier and a semiconductor body with a semiconductor layer sequence including an active region provided to generate radiation. The semiconductor body is externally electrically contactable by a first contact and a second contact. The carrier includes a protection diode structure connected electrically in parallel to the semiconductor body. The protection diode structure includes a first diode and a second diode. The first diode and the second diode are electrically connected in series in mutually opposing directions with regard to their forward direction.

Abstract: A group III nitride crystal substrate is provided wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.9×10?3, and wherein the main surface has a plane orientation inclined in a <11-20> direction at an angle equal to or greater than 10° and equal to or smaller than 81° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

Abstract: Solution processible hardmasks are described that can be formed from aqueous precursor solutions comprising polyoxometal clusters and anions, such as polyatomic anions. The solution processible metal oxide layers are generally placed under relatively thin etch resist layers to provide desired etch contrast with underlying substrates and/or antireflective properties. In some embodiments, the metal oxide hardmasks can be used along with an additional hardmask and/or antireflective layers. The metal oxide hardmasks can be etched with wet or dry etching. Desirable processing improvements can be obtained with the solution processible hardmasks.

Abstract: A method for controlling the distribution of the stresses in a structure of the semiconductor-on-insulator type during its manufacturing, which includes a thin layer of semiconducting material on a supporting substrate and an insulating layer present on each of the front and rear faces of the supporting substrate, with the insulating layer on the front face forming at least one portion of a thick buried insulator (BOX) layer. The method includes the adhesive bonding of the thin layer onto the supporting substrate. Prior to this adhesive bonding, the insulating layer on the rear face of the supporting substrate is covered with a distinct material that is capable of withstanding deoxidation. The covering material, in combination with this insulating layer on the rear face of the supporting substrate, at least partly compensates for the stress exerted by the buried insulator (BOX) on the supporting substrate.

Abstract: One aspect includes a semiconductor arrangement with a semiconductor body having a first surface. A buried material layer is in the semiconductor body, the buried material layer being arranged distant to the first surface. A monocrystalline semiconductor material is arranged between the material layer and the first surface, and a monocrystalline semiconductor material adjoins the material layer in a lateral direction of the semiconductor body.

Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

Abstract: To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

Abstract: A lead frame strip includes an array of sites connected to two side rails which traverse the lead frame strip on two opposite sides. Each site includes a die pad for affixing a semiconductor die and leads for enabling electrical communication between the semiconductor die and a workpiece. Each site is further connected to the two side rails by a sub-rail, which extends between the two side rails. The sub-rail includes a flat portion and a raised or indented rib protruding from the flat portion. The rib has a long dimension parallel to the sub-rail.

Abstract: Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam.

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract: A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.

Abstract: An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof.

Abstract: The present invention relates to a solder ball for semiconductor packaging and an electronic member having such solder ball. Specifically there are provided: a solder ball capable of ensuring a sufficient thermal fatigue property even when a diameter thereof is not larger than 250 ?m as observed in recent years; and an electronic member having such solder ball. More specifically, there are provided: a solder ball for semiconductor packaging that is made of a solder alloy containing Sn as a main element, 0.1-2.5% Ag by mass, 0.1-1.5% Cu by mass and at least one of Mg, Al and Zn in a total amount of 0.0001-0.005% by mass, such solder ball having a surface including a noncrystalline phase that has a thickness of 1-50 nm and contains at least one of Mg, Al and Zn, O and Sn, and an electronic member having such solder ball.

Abstract: A through-silicon via and a method for forming the same are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including an upper surface and an opposite lower surface; etching the upper surface of the semiconductor substrate to form an opening; filling the opening with a conductive material to form a first nail; etching the lower surface of the semiconductor substrate to form a recess, such that the first nail is exposed at a bottom of the recess; filling the recess with a conductive material that can be etched, and etching the conductive material that can be etched to form a second nail, such that the second nail is vertically connected with the first nail; and filling a gap between the second nail and the semiconductor substrate and a gap between the second nail and an adjacent second nail with a dielectric layer. Then invention can improve the reliability of through-silicon vias and avoid voids.

Abstract: An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad.

Abstract: A semiconductor package including connecting members having a controlled content ratio of gold capable of increasing durability and reliability by preventing an intermetallic compound having high brittleness from being formed. The semiconductor package includes a base substrate; a first semiconductor chip disposed on the base substrate; and a first connecting member for electrically connecting the base substrate and the first semiconductor chip, and comprising a first bonding portion that includes gold and has a first content ratio of gold that is controlled to prevent an intermetallic compound of AuSn4, (Cu, Au)Sn4, or (Ni, Au)Sn4 from being formed.

Abstract: An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 200 of compressible dielectric material and second, outer regions of dielectric material. In one embodiment, an underfill can contact a face of the microelectronic element between respective connectors or second regions. The second regions can provide restraining force, such that during volume expansion of the connectors, the first regions can compress against the restraining force of the second regions.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base integrated circuit over a base substrate; stacking a mountable device over the base package with a flow channel between the mountable device and the base package; and forming an external lead having a lead platform and a lead leg, the lead platform extending from the mountable device and the lead leg parallel to the base package.

Abstract: A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.