Abstract: A system, method and computer program product are provided for heuristically identifying protocols during network analysis utilizing a network analyzer. First provided is a sequencing and reassembly (SAR) engine module for sequencing and/or re-assembling network communications. Coupled to the engine module is a plurality of protocol interpreter modules for interpreting protocols associated with the network communications. At least one of the protocol interpreter modules is adapted for heuristically identifying protocols associated with the network communications.

Abstract: Provided are methods and systems for variable speed playback. In one aspect the disclosure provides for receiving content having a first playback speed, determining a second playback speed for at least a portion of the content based on a playback factor, associating the second playback speed with the portion of the content, and providing at least the portion of the content at the second playback speed to a display device.

Abstract: Process of communication via HTTP or HTTPS between a device running Java ME® and a server over the air, said server receiving and transmitting SOAP (Simple Object Access Protocol) messages from/to an operator on a host over a network and being capable of exchanging SOAP messages under Application Protocol Data Unit (APDU) data form/with the device, characterized in that the SOAP messages are translated from/to binary messages according to a protocol in the server, said binary messages being exchanged with the device, the binary messages being binary request messages or binary response messages.

Abstract: A method of transmitting data for use at a data processing system and network interface device, the data processing system being coupled to a network by the network interface device, the method comprising: forming a message template in accordance with a predetermined set of network protocols, the message template including at least in part one or more protocol headers; forming an application layer message in one or more parts; updating the message template with the parts of the application layer message; processing the message template in accordance with the predetermined set of network protocols so as to complete the protocol headers; and causing the network interface device to transmit the completed message over the network.

Abstract: Techniques are provided to detect and correct for packet loops associated with network traffic that passes through a wide-area application services (WAAS) device in a data center network environment. The WAAS device receives a packet from a device in a first data center. The WAAS device determines the directionality of the packet relative to a destination device of the packet. The WAAS device also determines whether the packet has an indicator that associates the packet with the WAAS device. Based on whether the packet has an indicator that associates the packet with the wide area application services device, the WAAS device inserts an indicator within the packet when the directionality of the packet indicates that the packet is to be transmitted across a wide area network (WAN), wherein the indicator comprises information that associates the packet with the WAAS device. The WAAS device forwards the packet to a network based on its directionality.

Abstract: A mechanism is provided for automatically routing network interconnects in a data processing system. A processor in a node of a plurality of nodes receives network topology from neighboring nodes in the plurality of nodes within the data processing system. The processor constructs a system node map that identifies a physical connectivity between the node and the neighboring nodes. The processor programs a switch in the node with a connectivity map that indicates a set of point-to-point connections with the neighboring nodes. The set of point-to-point connections comprise locally-connected connections and pass-through connections.

Abstract: In general, a mobile virtual private network (VPN) is described in which service provider networks cooperate to dynamically extend a virtual routing area of a home service provider network to the edge of a visited service provider network and thereby enable IP address continuity for a roaming wireless device. In one example, a home service provider network allocates an IP address to a wireless device and establishes a mobile VPN. The home service provider network dynamically provisions a visited service provider network with the mobile VPN, when the wireless device attaches to an access network served by the visited service provider network, to enable the wireless device to exchange network traffic with the visited service provider network using the IP address allocated by the home service provider network.

Abstract: Providing synchronization notifications to a client device. In response to a server receiving notification that an event of interest has been received, a state of the client device is determined. The state indicates whether or not the client device has any outstanding sync notifications. In an embodiment, the state is determined based on a first parameter and a second parameter. When the state of the client device indicates that the client device has no outstanding sync notifications prior to the receipt the received notification, the first parameter is set equal to the second parameter, and the second parameter is updated after each successful device synchronization of the client device. A filter is applied prior to sending out the sync notification to the client device.

Abstract: The invention relates generally to synchronizing functions on handheld devices and more particularly to precisely synchronizing a function among a large number of devices having multiple different platforms. The invention provides the ability to cause a large number of handheld devices to perform certain functions simultaneously, within seconds or fractions of a second of each other. In certain aspects, the invention provides an apparatus for synchronizing a function among devices, including one or more processors in communication with a memory and configured to, for each of the devices, send an event to the device, receive a timepacket, and send a return timepacket, thereby causing the device to receive the event and invoke the function after a delay.

Abstract: One or more techniques and/or systems are disclosed for matching a client device with an appropriate network service provider data package. A device ID for the client device can be decomposed to one or more device ID ranges in a device decomposition set. One or more ranges of client ID can be assigned to a network service provider data package, which can be decomposed into a set of package decomposition ranges in a package decompositions set. The device decomposition set can be compared to the package decomposition set, and if an intersection is identified between the sets, the network service provider data package can be provided to the client device.

Abstract: In one implementation, a pairing device provides an identify instruction to a peripheral device during a pairing process. The peripheral device generates an identification output in response to the identify instruction.

Abstract: Various embodiments of a system, method, and memory-medium provide for configuration of a programmable waveform that allows for communication with one of a plurality of different target devices. The programmable waveform comprises one or more waveform parameters and one or more waveform lines. The waveform lines may comprise control lines and/or data lines. One or more of the waveform parameters may be set in response to user input, and corresponding signals based on the waveform lines may be generated in order to communicate with a target device selected from a variety of different possible target devices. Waveform parameters may include one or more of: setup time, hold time, lead time, trail time, idle time, clock frequency, clock duty cycle, number of data bits per transmission, number of data lines, pulse width, polarity, and phase.

Abstract: The invention provides a method for identifying version type of a Windows operating system on a host by USB device, relating to operating system field and including steps: A, USB device is powered on and initialized; B, the USB device performs USB enumeration, determines whether a first predetermined instruction is received in process of USB enumeration, if yes, determines the operating system is a first operating system and goes to Step D, if no, goes to C; C, the USB device determines the device type returned in process of USB enumeration, if it is a CCID device, determines whether the received instruction includes a second predetermined instruction, if yes, determines the operating system is a second operating system, if no, determines the operating system is a third operating system; when the device is an SCSI device, the USB device determines whether the second received SCSI instruction is a third predetermined instruction or fourth predetermined instruction, if it is the third predetermined instruction,

Abstract: A data storage system includes a sensor unit, a storage unit, and a data exchange unit. The data exchange unit connects to the sensor unit and the storage unit, and transmits a data message received from the sensor unit to the storage unit, wherein the data exchange unit need not know the addresses of the sensor unit and the storage unit ahead of time to be able to successfully transmit the data message to the storage unit requesting the data message.

Abstract: In one embodiment, a method includes determining a request for a transfer of content where the request is associated with a user device. It is determined if a deferred transfer should be performed. The deferred transfer defers the transfer of the content with a completion by a completion time. The request is stored in a queue where the request is associated with the completion time. The method processes the request from the queue to transfer the content at a start time. The content is transferred by the completion time. The method then adjusts, for a user associated with the user device, a charging parameter for the transfer due to the transfer being deferred.

Abstract: A detection device to detect a power serving time of a super capacitor for a power-disconnected storage card and an amount of the data packets capable of being stored during the detected serving time is provided. The power-disconnected storage card includes a memory. The detection device includes a power supply unit, the super capacitor, a controller, a storage unit, and a detection unit. The storage unit stores the data packets. The detection unit includes a charge notification module, a data notification module and a time module. The charge notification module generates a first notification signal to the time module. The data notification module generates a second notification signal to the time module when the storage unit transmits the data packet to the memory. The time module records time when the memory completely store the data packet according to the first notification signal and the second notification signal.

Abstract: The disclosed embodiments provide a system that uses a DMA engine to automatically validate DMA data paths for a computing device. During operation, the system configures the DMA engine to perform a programmable DMA operation that generates a sequence of memory accesses which validate the memory subsystem and DMA paths of the computing device. For instance, the operation may include a sequence of reads and/or writes that generate sufficient data traffic to exercise the computing device's I/O controller interface and DMA data paths to memory to a specified level. The system initiates this programmable DMA operation, and then checks outputs for the operation to confirm that the operation executed successfully.

Abstract: Disclosed are a method and a computer program storage product for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. A plurality of downstream processing elements and an upstream processing element are associated with at least one input buffer. Each of the downstream processing elements consumes data packets produced by the upstream processing element received on an output stream associated with the upstream processing element. A fastest input rate among each downstream processing element in the plurality of downstream processing elements is identified. An output rate of the upstream processing element is set to the fastest input rate that has been determined for the plurality of downstream processing elements.

Abstract: A data transfer apparatus includes a serial interface controller configured to perform data transfer between the data transfer apparatus and a destination device via a serial transmission line; and a transfer controller configured to control the data transfer, issue a read request for data to the destination device, and resume issue of the read request after elapse of a given retransmission time when a positive acknowledgement in response to the read request is not received from the destination device under a given condition.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: An apparatus for determining and/or monitoring a chemical or physical, process variable in automation technology, comprising: a superordinated control unit; and a transmitter electronics having a first interface, a second interface and a third interface. The transmitter electronics communicates with the superordinated control unit by means of the first interface via a bus protocol. The transmitter electronics can be connected with a service unit via the second interface; and the third interface has a plurality of data channels for corresponding data source components; and wherein individual data channels are addressable and tunable via the service unit as a function of the connected data source components, so that data selected from the data for the connected data source components can be transmitted at the same time in at least one telegram to the superordinated control unit.

Abstract: An active information sharing system having a master device and a slave device is disclosed. When the master device is connected to a first host of an administrator, the master device automatically links to a server through a first network module of the first host, for sharing at least an information from the administrator. The master device correspondingly sets a first parameter to the slave device. When the slave device is connected to a second host of an invited client, the slave device automatically links to the server through a second network module of the second host according to the first parameter, for acquiring the information shared from the administrator.

Abstract: An interrupt control apparatus and interrupt control method reduce situations in which the output of interrupt information is suspended and thus reduce stress caused in a user, without missing the appropriate output timing for interrupt information having a high priority level. A priority level setting unit raises the value of a priority level for an interrupt voice message during a period in which the interrupt voice message is being outputted, and a voice output control unit, when interrupts from two or more overlapping interrupt voice messages occurs, carries out control in accordance with priority levels set for each of the two or more interrupt voice messages so that the interrupt voice message having the higher priority level value is preferentially outputted.

Abstract: A peripheral component interconnect express (PCI-E) system has a reconfigurable link architecture. The system comprises a system slot adapted to receive a PCI-E compatible system controller, a plurality of peripheral slots adapted to receive a plurality of peripheral modules, and a reconfigurable switch fabric configured to create a variable number of PCI-E links between the system slot and the plurality of peripheral slots.

Abstract: A detachable assembled electronic device includes a portable device having a display interface and a docking station. The docking station includes a docking station main body and a connecting structure. The connecting structure is assembled to the docking station main body to support the portable device, and includes a flexible element and a first section. The first section is wrapped by the flexible element. When the first section is attached to the portable device, the first section and the flexible element are adapted to support the portable device on the docking station main body, and the portable device is adapted to rotate relative to the docking station main body by the bending of the flexible element to form an operation angle.

Abstract: System and method for implementing a secure processor data bus are described. One embodiment is a circuit comprising a processor disposed in a processor partition, the circuit further comprising a first set of peripherals disposed in a first peripheral partition; a second set of peripherals disposed in a second peripheral partition physically isolated from the first peripheral partition; a first state control register for controlling access to the first set of peripherals by the processor; and a second state control register for controlling access to the second set of peripherals by the processor. When the first and second state control registers are in a first mode of operation, the processor has read and write access to the first set of peripherals and write only access to the second set of peripherals.

Abstract: A method is provided in one example embodiment that includes rebasing a module in a virtual partition to load at a fixed address and storing a hash of a page of memory associated with the fixed address. An external handler may receive a notification associated with an event affecting the page. An internal agent within the virtual partition can execute a task and return results based on the task to the external handler, and a policy action may be taken based on the results returned by the internal agent. In some embodiments, a code portion and a data portion of the page can be identified and only a hash of the code portion is stored.

Abstract: A host selects a memory page that has been allocated to a guest for eviction. The host may be a host machine that hosts a plurality of virtual machines. The host accesses a bitmap maintained by the guest to determine a state of a bit in the bitmap associated with the memory page. The host determines whether content of the memory page is to be preserved based on the state of the bit. In response to determining that the content of the memory page is not to be preserved, the host discards the content of the memory page.

Abstract: A processing device executing an operating system such as a guest operating system generates a bitmap wherein bits of the bitmap represent statuses of memory pages that are available to the operating system. The processing device frees a memory page. The processing device then sets a bit in the bitmap to indicate that the memory page is unused after the memory page is freed.

Abstract: A physical host executes a hypervisor or virtual machine monitor (VMM) that instantiates at least one virtual machine (VM) and a virtual input/output server (VIOS). The VIOS determines by reference to a policy data structure a disposition of a packet of network communication with the VM, where the disposition includes one of dropping the packet and forwarding the packet. Thereafter, the determined disposition is applied to a subsequent packet in a same packet flow as the packet.

Abstract: A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.

Abstract: A method and apparatus for managing address map information are disclosed. In one embodiment, an apparatus may comprise a processor configured to store address map changes to a first data storage medium, save the address map changes to a nonvolatile data storage medium when an abnormal power state is detected, and when the power state is no longer abnormal retrieve the last saved address map information and address map changes and update the address map information using the address map changes. The apparatus may be configured to retrieve the instructions for the processor operation over a network connection.

Abstract: A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.

Abstract: A composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics, is described. This composite memory device may receive requests, a given one of which includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command. For the given request, the composite memory device executes the command on the block of data at the logical address in at least one of the types of non-volatile memory devices. Furthermore, the composite memory device conditionally executes the hint based on one or more criteria, such as: available memory in the types of non-volatile memory devices, traffic through an interface circuit in the composite memory device, operational states of the types of non-volatile memory devices, a target performance characteristic of the composite memory device, and an environmental condition of the composite memory device.

Abstract: In general, embodiments of the present invention provide a disk an I/O layer architecture having a customized block-level device driver. In a typical embodiment, the architecture described herein comprises a file system layer being configured to handle user data; a buffer cache layer, adjacent the file system layer, the buffer cache layer being configured to handle page data; a block device driver layer adjacent the buffer cache layer, the block device driver layer being configured to handle block data, and the block device driver layer comprising an I/O scheduler layer and a device driver layer; and a storage unit layer adjacent the block device driver layer, the storage unit layer being configured to hand command data. Moreover, the storage unit layer can comprise a set (e.g., at least one) of semiconductor storage device (SSD) memory units, and the I/O scheduler layer can be configured to handle memory-based devices (e.g.

Abstract: According to an aspect of the inventive concepts, there is provided a non-volatile memory device including a memory array with at least one stripe. The at least one stripe includes at least one parity page and at least one data page. The non-volatile memory device further includes a chip controller. The chip controller includes an operation module configured to perform an operation on data input from the outside of the memory device, to store a result of the performing, and to program the result of the performing into the at least one parity page. The chip controller further includes a data buffer configured to store the input data and to program the input data into the at least one data page.

Abstract: A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory.

Abstract: Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data.

Abstract: Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.

Abstract: A method for data storage in a nonvolatile memory device includes compressing current data. The compressed current data is written to a space of the nonvolatile memory device that does not include a most recently written data. If the compressed current data is successfully written, identification data is stored on the nonvolatile memory device. The identification data identifies the written compressed current data as a currently valid version.

Abstract: Disclosed herein is an information processing system having first and second devices. The second device alternately issues a self-refresh command and a self-refresh exit command to the first device. The first device performs a refresh operation once in response to the self-refresh command and updates a state of a DLL circuit in response to the self-refresh exit command.

Abstract: Apparatuses and methods for prefetching data are disclosed. A method may include receiving a read request at a data storage device, determining a meta key in an address map that includes a logical block address (LBA) of the read request, wherein the meta key includes a beginning LBA and a size field corresponding to a number of consecutive sequential LBAs stored on the data storage device, calculating a prefetch operation to prefetch data based on addresses included in the meta key, and reading data corresponding to the prefetch operation and the read request. An apparatus may include a processor configured to receive a read request, determine a first meta key and a second meta key in an address map, calculate a prefetch operation based on addresses included in the first meta key and the second meta key, and read data corresponding to the prefetch operation and the read request.

Abstract: A storage apparatus includes a memory that stores a job management information that registers a write job corresponding to a write command upon receiving the write command from other apparatus, a cache memory that stores data designated as target data by the write command, a storage drive that records the data stored in the cache memory to a storage medium based on the write job registered in the job management information, and a controller that controls a timing to output to the other apparatus a completion report of the write command based on a load condition of the storage device related to an accumulation count of write job acquired from the job management information.

Abstract: A device driver includes an aggregator aggregating data blocks into one or more container objects suited for storage in an object store; and a logger for maintaining in at least one log file for each data block an identification of a container object wherein the data block is stored with an identification of the location of the data block in the container object.

Abstract: A cache memory associated with a main memory and a processor capable of executing a dataflow processing task, includes a plurality of disjoint storage segments, each associated with a distinct data category. A first segment is dedicated to input data originating from a dataflow consumed by the processing task. A second segment is dedicated to output data originating from a dataflow produced by the processing task. A third segment is dedicated to global constants, corresponding to data available in a single memory location to multiple instances of the processing task.

Abstract: A computer system includes: a main storage unit, a processing executing unit sequentially executing processing to be executed on virtual processors; a level-1 cache memory shared among the virtual processors; a level-2 cache memory including storage areas partitioned based on the number of the virtual processors, the storage areas each (i) corresponding to one of the virtual processors and (ii) holding the data to be used by the corresponding one of the virtual processors; a context memory holding a context item corresponding to the virtual processor; a virtual processor control unit saving and restoring a context item of one of the virtual processors; a level-1 cache control unit; and a level-2 cache control unit.

Abstract: There is provided is an interface apparatus including: a stream converter receiving write-addresses and write-data, storing the received data in a buffer, and sorting the stored write-data in the order of the write-addresses to output the write-data as stream-data; a cache memory storing received stream-data if a load-signal indicates that the stream-data are necessarily loaded and outputting data stored in a storage device corresponding to an input cache-address as cache-data; a controller determining whether or not data allocated with a read-address have already been loaded, outputting the load-signal instructing the loading on the cache memory if not loaded, and outputting a load-address indicating a load-completed-address of the cache memory; and at least one address converter calculating which one of the storage devices the allocated data are stored in, by using the load-address, outputting the calculated value as the cache-address to the cache memory, and outputting the cache-data as read-data.

Abstract: A cache memory controller including: a pre-fetch requester configured to issue pre-fetch requests, each pre-fetch request having one of a plurality of different quality of services.

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract: A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.