Abstract: A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.

Abstract: Semiconductor die are assembled on a substrate by providing the semiconductor die, substrate, and an elastically deformable foil fixture preformed with one or more sunken regions having sidewalls and a bottom, and placing the semiconductor die in the one or more sunken regions so that the foil fixture is populated with a first side of the semiconductor die facing the bottom of the one or more sunken regions and a second opposing side of the semiconductor die facing away from the bottom of the one or more sunken regions. The substrate is placed adjacent the second side of the semiconductor die with a joining material interposed between the substrate and the semiconductor die. The substrate and the populated foil fixture are pressed together at an elevated temperature and pressure via first and second pressing tool members so that the substrate is attached to the second side of the semiconductor die via the joining material.

Abstract: A spiral staircase shaped stacked semiconductor package is presented. The package includes a semiconductor chip module, a substrate and connection members. The semiconductor chip module includes at least two semiconductor chips which have chip selection pads and through-electrodes. The semiconductor chips are stacked such that the chip selection pads are exposed and the through-electrodes of the stacked semiconductor chips are electrically connected to one another. The substrate has the semiconductor chip module mounted thereto and has connection pads. The connection members electrically connect the chip selection pads to respective connection pads.

Abstract: A method for forming a sealing body without cracks in manufacture of a semiconductor device having an external terminal formed through the use of an electrolysis plating method. A front surface of a semiconductor wafer is placed over a front surface of a first support heated to a first temperature. An adhesive sheet is then bonded to a back surface of the semiconductor wafer, after which the semiconductor wafer is subjected to heat treatment at a second temperature higher than the first temperature. After the semiconductor wafer and the adhesive sheet are cut along cutting regions, a plurality of semiconductor chips each having an adhesive patch bonded thereto are obtained. A mother substrate is placed over a front surface of a second support heated to a third temperature and the semiconductor chips are fixed to an upper surface of the mother substrate via the adhesive patch.

Abstract: A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the recesses. Additional embodiments are disclosed.

Abstract: The present disclosure provides manufacturing techniques in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage on the basis of a selectively applied threshold voltage adjusting semiconductor alloy. In order to reduce the surface topography upon patterning the deposition mask while still allowing the usage of well-established epitaxial growth recipes developed for silicon dioxide-based hard mask materials, a silicon nitride base material may be used in combination with a surface treatment. In this manner, the surface of the silicon nitride material may exhibit a silicon dioxide-like behavior, while the patterning of the hard mask may be accomplished on the basis of highly selective etch techniques.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: The present invention discloses a method of manufacturing an N-type LDMOS device. The method comprises forming a gate above the semiconductor substrate; forming a body, comprising forming a Pwell apart from the gate and forming a Pbase partly in the Pwell, wherein the Pbase is wider and shallower than the Pwell; and forming an N-type source and a drain contact region. Wherein the body curvature of the LDMOS device is controlled by adjusting the layout width of the Pwell.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

Abstract: A method for manufacturing a transistor and a semiconductor device is provided. The method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack or a dummy gate stack, a source/drain extension region, a spacer and a source/drain region, wherein the source/drain extension region is embedded in the active area and self-aligned on both sides of the gate stack or dummy gate stack, the spacer surrounds the gate stack or dummy gate stack, and the source/drain region is embedded in the active area and self-aligned outside the spacer; removing at least a portion of the spacer to expose a portion of the active area; and forming an interlayer dielectric layer which covers the gate stack or dummy gate stack, the spacer and the exposed active area, wherein the dielectric constant of the material of the interlayer dielectric layer is smaller than that of the removed material of the spacer.

Abstract: A method of manufacturing a semiconductor die having a substrate with a front side and a back side includes fabricating openings for through substrate vias on the front side of the semiconductor die. The method also includes depositing a first conductor in the through substrate vias, depositing a dielectric on the first conductor and depositing a second conductor on the dielectric. The method further includes depositing a protective insulator layer on the back side of the substrate covering the through substrate vias.

Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.

Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.

Abstract: Various embodiments relate to a method of modifying the electrical properties of carbon nanotubes. The method may include providing a substrate having carbon nanotubes deposited on a surface of the substrate, and depositing on the carbon nanotubes a coating layer comprising a mixture of nanoparticles, a matrix in which the nanoparticles are dissolved or stabilized, and an ionic liquid. A field-effect transistor including the modified carbon nanotubes is also provided.

Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.

Abstract: A process for supplying a mixed material gas that includes a chlorosilane gas and a carrier gas to a surface of a substrate heated at 1200 to 1400° C. from a direction perpendicular to the surface is provided. A supply rate of the chlorosilane gas is equal to or more than 200 ?mol per minute per 1 cm2 of the surface of the substrate. The carrier gas includes a hydrogen gas and at least one or more gases selected from argon, xenon, krypton and neon.

Abstract: The present method of manufacturing a GaN-based film includes the steps of preparing a composite substrate, the composite substrate including a support substrate in which a coefficient of thermal expansion in a main surface is more than 0.8 time and less than 1.2 times as high as a coefficient of thermal expansion of GaN crystal in a direction of a axis and a single crystal film arranged on a side of the main surface of the support substrate, the single crystal film having threefold symmetry with respect to an axis perpendicular to a main surface of the single crystal film, and forming a GaN-based film on the main surface of the single crystal film in the composite substrate. Thus, a method of manufacturing a GaN-based film capable of manufacturing a GaN-based film having a large main surface area and less warpage is provided.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Abstract: Embodiments of the invention provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a remote plasma system includes a remote plasma chamber defining a first region for generating a plasma comprising ions and radicals, a process chamber defining a second region for processing a semiconductor device, the process chamber comprising an inlet port formed in a sidewall of the process chamber, the inlet port being in fluid communication with the second region, and a delivery member disposed between the remote plasma chamber and the process chamber and having a passageway in fluid communication with the first region and the inlet port, wherein the delivery member is configured such that a longitudinal axis of the passageway intersects at an angle of about 20 degrees to about 80 degrees with respect to a longitudinal axis of the inlet port.

Abstract: A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.

Abstract: A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.

Abstract: Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.

Abstract: In a method of forming a metal or metal nitride pattern, a metal or metal nitride layer is formed on a substrate, and a photoresist pattern is formed on the metal or metal nitride layer. An over-coating composition is coated on the metal or metal nitride layer and on the photoresist pattern to form a capping layer on the photoresist pattern. The over-coating composition includes a polymer having amine groups as a side chain or a branch and a solvent. A remaining portion of the over-coating composition is removed by washing with a hydrophilic solution. The metal or metal nitride layer is partially removed using the capping layer and the photoresist pattern as an etching mask.

Abstract: An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another.

Abstract: Disclosed herein are various methods of forming metal-containing insulating material regions on a metal layer of a gate structure of a semiconductor device. In one example, the method includes forming a gate structure of a transistor, the gate structure comprising at least a first metal layer, and forming a first metal-containing insulating material region in the first metal layer by performing a gas cluster ion beam process using to implant gas molecules into the first metal layer.

Abstract: A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.

Abstract: A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

Abstract: A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

Abstract: A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a groove is formed in a insulating film on a semiconductor substrate. An underlayer film is formed on the insulating film. A metal film is formed on the underlayer film. First polishing, in which the metal film is removed, is performed by supplying a first CMP slurry containing metal ions. The surfaces of the polishing pad and the semiconductor substrate are cleaned by supplying organic acid and pure water. Second polishing, in which the underlayer film is removed from the portion other than the groove, is performed by supplying a second CMP slurry different from the first CMP slurry.

Abstract: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Abstract: A method of depositing a thin film by atomic layer deposition (ALD) on a substrate surface is disclosed. The disclosed method includes placing an ALD deposition proximity head above the substrate with at least one gas channel configured to dispense a gas to an active process region of the substrate surface. The ALD deposition proximity head extends over and is being spaced apart from the active process region of the substrate surface when present. After a pulse of a first reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head, a pulse of a second reactant gas is dispensed on the active process region of the substrate surface underneath the proximity head to react with the first reactant gas to form a portion of the thin layer of ALD film on the surface of substrate underneath the proximity head.

Abstract: A polishing composition contains at least one water soluble polymer selected from the group consisting of polyvinylpyrrolidone and poly(N-vinylformamide), and an alkali, and preferably further contains at least one of a chelating agent and an abrasive grain. The water soluble polymer preferably has a weight average molecular weight of 6,000 to 4,000,000. The polishing composition is mainly used in polishing of the surfaces of semiconductor wafers such as silicon wafers, especially used in preliminary polishing of the surfaces of such wafers.

Abstract: A method of fabricating a semiconductor device for improving the performance of “?” shaped embedded source/drain regions is disclosed. A “U” shaped recess is formed in a Si substrate. The recess is treated with a surfactant, the amount of surfactant adsorbed on the recess sidewalls being greater than that on the recess bottom. An oxide is formed on the bottom. The presence of surfactant on the sidewalls, prevents oxide from forming thereon. The surfactant on the sidewalls is then removed and an orientation selective wet etching process is performed on the sidewalls. The oxide protects the Si at the bottom is from being etched.

Abstract: A mask layer is formed by: a step in which a first photoresist layer is formed, exposed, and developed on a substrate, thereby forming a first photoresist pattern; a step in which the first photoresist pattern is made insoluble; a step in which a second photoresist layer is formed, exposed, and developed on top of the first photoresist layer, thereby forming a second photoresist pattern that intersects the first photoresist pattern; a step in which the second photoresist pattern is made insoluble; and a step in which a third photoresist layer is formed, exposed, and developed on top of the first and second photoresist patterns, thereby forming a third photoresist pattern.

Abstract: Methods of patterning low-k dielectric films are described.

Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

Abstract: In a modified region forming step, an element-group formation substrate (20) having plural semiconductor light emitting elements (21) formed on a substrate front surface (11a) of a wafer substrate (11) is irradiated with laser light (64) from the substrate back surface (11b) of the substrate, thereby forming the following inside the substrate: first and third modified regions (L1) and (L3) oriented in a y-direction (corresponding to a first direction) that is parallel to the surfaces of the substrate; and second and fourth modified regions (L2) and (L4) oriented in an x-direction (corresponding to a second direction) that is parallel to the surfaces of the substrate and differs from the y-direction. In the step, the first modified region (L1), the second modified region (L2), the third modified region (L3) and the fourth modified region (L4) are formed at different depths from the substrate back surface of the substrate.

Abstract: An apparatus for supporting an electrical connection, the apparatus including attachment means for enabling the apparatus to be mounted to a surface, a frame means rotatably coupled to the attachment means, an electrical connection coupled to the frame means, and an electrical wire coupled to the electrical connection.

Abstract: Provided is a remote-controlled mirror drive unit, the drive unit eliminating the need to provide a splice portion that short-circuits terminals of two motors at a halfway position in a mirror harness and enabling the short-circuit part to be arranged outside a mirror unit. A mirror harness includes four wires connected respectively to four terminals of two mirror angle adjustment motors. The mirror harness is led to a vehicle body inner portion through a mirror housing and a mirror base. In the vehicle body inner portion, a mirror switch circuit is disposed. Three wires that supply drive power to the motors are drawn out from the mirror switch circuit. The four wires and the three wires are interconnected in an in-vehicle body connector. Here, two wires are connected to one wire, and two wires are individually connected to two wires.

Abstract: An electrical connector includes a first connector, and a second connector detachably coupled to the first connector. The first connector has a first magnetic body and at least one first conductive body. The second connector has a second magnetic body and at least one second conductive body. The first magnetic body is capable of magnetically attracting the second magnetic body to form a sealed enclosure to receive the at least one first conductive body and the at least one second conductive body. The at least one first conductive body electrically connects to the at least one second conductive body when the first magnetic body is magnetically bound to the second magnetic body.

Abstract: A magnetic connector system having a durable and reliable construction and a reduced height while maintaining sufficient holding strength. A connector insert may utilize a crimping piece to crimp a braiding of a cable. The crimping piece may be fixed to an attraction plate and a board in the insert for mechanical reliability. Retention clips may be used to fix a shell to the attraction plate. A connector receptacle may employ a magnetically conductive label to improve holding strength.

Abstract: An interposer adapted to interrupt the power source of a streetlight and intervening between an existing photo-controller and the streetlight with a lamp connected to a power line, the interposer having a body having a top and a bottom, the top of the body having an electrical receptacle, the bottom of the body having an electrical plug, the body containing a microprocessor and a load switch connected to the main power line and lamp, wherein the microprocessor instructs the load switch to selectively connect and disconnect the power line and the lamp, or to dim a multi-level lighting device.

Abstract: An electrical device for electrically connection an electronic component, comprises a substrate, and a plurality of contact units mounted on the substrate. The contact units each comprises a lower contact positioned on the substrate and an upper contact coupled to the lower contact. The upper contact is floatably received in a receiving space defined by the lower contact and upward and downward movement of the upper contact relative to the lower contact are limited by the lower contact.