Method of Multi-Chip Wafer Level Packaging
A method of multi-chip wafer level packaging comprises forming a reconfigured wafer using a plurality of photo-sensitive material layers. A plurality of semiconductor chips and wafers are embedded in the photo-sensitive material layers. Furthermore, a variety of through assembly vias are formed in the photo-sensitive material layers. Each semiconductor chip embedded in the photo-sensitive material layers is connected to input/output pads through connection paths formed by the through assembly vias.
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The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, multi-chip wafer level package based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a wafer level package based semiconductor device, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. Much higher density can be achieved by employing multi-chip semiconductor devices. Furthermore, multi-chip semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
A multi-chip semiconductor device may comprise a top active circuit layer, a bottom active circuit layer and a plurality of inter-layers. In a multi-chip semiconductor device, two dies may be bonded together through a plurality of micro bumps and electrically coupled to each other through a plurality of through-silicon vias. The micro bumps and through-silicon vias provide an electrical interconnection in the vertical axis of the multi-chip semiconductor device. As a result, the signal paths between two semiconductor dies are shorter than those in a traditional multi-chip device in which different dies are bonded together using interconnection technologies such as wire bonding based chip stacking packages. A multi-chip semiconductor device may comprise a variety of semiconductor dies stacked together. The multiple semiconductor dies are packaged before the wafer has been diced. The wafer level package technology has some advantages. One advantageous feature of packaging multiple semiconductor dies at the wafer level is multi-chip wafer level package techniques may reduce fabrication costs. Another advantageous feature of wafer level package based multi-chip semiconductor devices is that parasitic losses are reduced by employing micro bumps and through-silicon vias.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present disclosure will be described with respect to embodiments in a specific context, a multi-chip wafer level semiconductor package. The embodiments may also be applied, however, to a variety of semiconductor devices.
Referring initially to
The multi-chip semiconductor device 100 further comprises a plurality of solder balls 110 as input/output (I/O) pads mounted on the top side of the multi-chip semiconductor device 100 using a plurality of under bump metallization (UBM) structures 112. In order to give a basic insight of the inventive aspects of various embodiments, the first semiconductor die 131, the second semiconductor die 132 and the third semiconductor die 133 are drawn without details. However, it should be noted the first semiconductor die 131, the second semiconductor die 132 and the third semiconductor die 133 may comprise basic semiconductor layers such as active circuit layers, substrate layers, inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers (not shown).
In accordance with an embodiment, the first semiconductor die 131 may comprise a plurality of logic circuits such as central processing unit (CPU), graphics processing unit (GPU) and the like. the second semiconductor die 132 and the third semiconductor die 133 may comprise a plurality of memory circuits such as static random access memory (SRAM) and dynamic random access memory (DRAM) and the like. It should be noted that the first semiconductor die 131, the second semiconductor die 132 and the third semiconductor die 133 may have many embodiments, which are also in the scope of the present disclosure.
The multi-chip semiconductor device 100 may comprise two photo-sensitive material layers 106 and 108. The photo-sensitive material layer 106 is formed on top of the photo-sensitive material layer 108. As shown in
The active circuit layer (not shown) of the first semiconductor die 131 is coupled to the solder balls 110 through the plurality of TAVs 102, 104 and redistribution layers 114 and 134. More particularly, the second redistribution layer 134, the TAVs 102, the TAVs 104 and the first redistribution layer 114 may form various connection paths so that the active circuits of the first semiconductor die 131 can be connected with the solder balls 110. Likewise, the first redistribution layer 114, the second redistribution layer 134 and the TAVs 104, 116 may form various connection paths so that the active circuit (not shown) of the second semiconductor die 132 and the third semiconductor die 133 can be connected with the solder balls 110.
The multi-chip semiconductor device 100 may comprise a base plane 120 formed on the backside of the first semiconductor die 131. The base plane 120 may be formed of a conductive material such as copper, sliver, gold, tungsten, aluminum, combinations thereof or the like. Alternatively, the base plane 120 may be formed of a wide variety of materials comprising glass, silicon, ceramics, polymers and the like. In accordance with an embodiment, the base plane 120 may be adhered on the backside of the semiconductor die 131 by an adhesive 122, such as thermal interface materials including epoxy and the like.
As shown in
It should further be noted that one of ordinary skill in the art would recognize the stacking structure of the multi-die semiconductor device 100 may have variations, alternatives, and modifications. For example, the second semiconductor die 132 may be face-to-face attached to the first semiconductor die 131 using a plurality of metal bumps (not shown) Likewise, the third semiconductor die 133 can be flipped. As a result, there may be a face-to-face stacking structure between the third semiconductor die 133 and the second semiconductor die 132.
Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method comprising:
- attaching a first semiconductor die on a top side of a wafer;
- attaching a second semiconductor die on the first semiconductor die;
- forming a reconfigured wafer by embedding the first semiconductor die and the second semiconductor die into a first photo-sensitive material layer; and
- forming a first group of through assembly vias in the first photo-sensitive material layer.
2. The method of claim 1, further comprising:
- attaching the wafer on a base plane using an adhesive layer; and
- detaching the base plane from the wafer.
3. The method of claim 1, further comprising:
- attaching the second semiconductor die to the first semiconductor die using a first adhesive layer;
- back-to-face attaching the first semiconductor die to the wafer using a second adhesive layer;
- forming a first redistribution layer on top of the first photo-sensitive material layer; and
- forming a plurality of solder balls on top of the first redistribution layer.
4. The method of claim 1, further comprising:
- face-to-face attaching the second semiconductor die to the first semiconductor die using a plurality of metal bumps; and
- face-to-face attaching the first semiconductor die to the wafer using a plurality of metal bumps.
5. The method of claim 1, further comprising:
- forming a first group of openings between one side of the second semiconductor die and a front side of the first photo-sensitive material layer;
- forming a second group of openings between one side of the first semiconductor die and the front side of the first photo-sensitive material layer; and
- forming a third group of openings between one side of the wafer and the front side of the first photo-sensitive material layer.
6. The method of claim 5, further comprising:
- electroplating conductive materials in the first group of openings;
- electroplating conductive materials in the second group of openings; and
- electroplating conductive materials in the third group of openings.
7. The method of claim 1, further comprising:
- sawing the reconfigured wafer into a plurality of packages, wherein each package comprises a plurality of semiconductor dies.
8. A method comprising:
- attaching a semiconductor die on a top side of a second wafer;
- forming a first reconfigured wafer by embedding the second wafer and the semiconductor die into a first photo-sensitive material layer;
- sawing the first reconfigured wafer into a plurality of multi-die structures;
- attaching the plurality of multi-die structures on a top side of a first wafer;
- forming a second reconfigured wafer by embedding the plurality of multi-die structures into a second photo-sensitive material layer; and
- forming a first group of through assembly vias in the second photo-sensitive material layer.
9. The method of claim 8, further comprising:
- attaching the first wafer on a first base plane using a first adhesive layer; and
- detaching the first base plane from the first wafer.
10. The method of claim 8, further comprising:
- attaching the semiconductor die to the second wafer using a third adhesive layer;
- back-to-face attaching the plurality of multi-die structures to the first wafer using a fourth adhesive layer;
- forming a first redistribution layer on top of the first photo-sensitive material layer;
- forming a second redistribution layer on top of the second photo-sensitive material layer; and
- forming a plurality of solder balls on top of the second redistribution layer.
11. The method of claim 8, further comprising:
- face-to-face attaching the semiconductor die to the second wafer using a plurality of metal bumps; and
- face-to-face attaching the plurality of multi-die structures to the first wafer using a plurality of metal bumps.
12. The method of claim 8, further comprising:
- forming a first group of openings between one side of the semiconductor die and a front side of the first photo-sensitive material layer;
- forming a second group of openings between one side of the second wafer and the front side of the first photo-sensitive material layer;
- forming a third group of openings between one side of the first wafer and a front side of the second photo-sensitive material layer; and
- forming a fourth group of openings between the front side of the second photo-sensitive material layer and the front side of the first photo-sensitive material layer.
13. The method of claim 12, further comprising:
- electroplating conductive materials in the first group of openings;
- electroplating conductive materials in the second group of openings;
- electroplating conductive materials in the third group of openings; and
- electroplating conductive materials in the fourth group of openings.
14. The method of claim 8, further comprising:
- sawing the second reconfigured wafer into a plurality of packages, wherein each package comprises a plurality of semiconductor dies.
15. A method comprising:
- attaching a first semiconductor die on a top side of a wafer;
- forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer;
- forming a first group of through assembly vias in the first photo-sensitive material layer;
- attaching a second semiconductor die on the first photo-sensitive material layer;
- forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer; and
- forming a second group of through assembly vias in the second photo-sensitive material layer.
16. The method of claim 15, further comprising:
- attaching the wafer on a first base plane.
17. The method of claim 15, further comprising:
- attaching the second semiconductor die to the first semiconductor die using a first adhesive layer;
- back-to-face attaching the first semiconductor die to the wafer using a second adhesive layer;
- forming a first redistribution layer on top of the first photo-sensitive material layer;
- forming a second redistribution layer on top of the second photo-sensitive material layer; and
- forming a plurality of solder balls on top of the second redistribution layer.
18. The method of claim 17, further comprising:
- attaching a top side of the second semiconductor die to the first redistribution layer using a plurality of metal bumps; and
- face-to-face attaching the first semiconductor die to the wafer using a plurality of metal bumps.
19. The method of claim 15, further comprising interconnecting the first group through assembly vias and the second group through assembly vias.
20. The method of claim 15, further comprising:
- forming a second reconfigured wafer by embedding the first reconfigured wafer and the second semiconductor die into the second photo-sensitive material layer; and
- sawing the second reconfigured wafer into a plurality of packages, wherein each package comprises a plurality of semiconductor dies.
Type: Application
Filed: Aug 10, 2011
Publication Date: Feb 14, 2013
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Chih-Hang Tung (Hsin-Chu), Chun Hui Yu (Zhubei City), Chen-Hua Yu (Hsin-Chu), Da-Yuan Shih (Hsin-Chu)
Application Number: 13/206,602
International Classification: H01L 21/56 (20060101); H01L 21/82 (20060101);