Abstract: The amorphous silicon film is formed over the microcrystalline silicon film, and plasma treatment is performed on the amorphous silicon film in a mixed gas atmosphere of H2 and Ar at a pressure higher than 1000 Pa, so that etching is performed to expose the microcrystalline silicon film. In the etching, the etching rate of the amorphous silicon film and that of the microcrystalline silicon film is large.

Abstract: A silicon compound film is dry etched by parallel-plate type dry etching using an etching gas including at least COF2.

Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.

Abstract: A semiconductor memory device includes a first active region, a second active region, a first element isolating region and a second element isolating region. The first active region is formed in a semiconductor substrate. The second active region is formed in the semiconductor substrate. The first element isolating region electrically separates the first active regions adjacent to each other. The second element isolating region electrically separates the second active regions adjacent to each other. An impurity concentration in a part of the second active region in contact with a side face of the second element isolating region is higher than that in the central part of the second active region, and a impurity concentration in a part of the first active region in contact with a side face of the first element isolating region is equal to that in the first active region.

Abstract: According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si1-xGex (0<x<1) formed on the active area, and a fin structure of Si1-yGey (x<y?1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

Abstract: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Abstract: A semiconductor device includes a first MISFET having a first conduction type channel and formed on a semiconductor substrate; a second MISFET having a second conduction type channel and formed on the semiconductor substrate; a first strain film having a first sign strain that covers a region where the second MISFET is disposed; and a second strain film having a second sign strain that covers a region where the first MISFET is disposed. In the semiconductor device, an edge of the second strain film closer to the second MISFET overlaps with part of the first strain film; and the second strain film at a portion where the second strain film overlaps with the first strain film and at a portion extending from the portion, is thinner than the second strain film at a portion that covers the first MISFET.

Abstract: A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.

Abstract: This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation portion formed by filling an insulator in a trench formed in the semiconductor substrate, a first device provided in the first device formation region, a second region defined on the semiconductor substrate separately from the first region and having a second device formation region, and a second device provided in the second device formation region and having a higher breakdown voltage than the first device, the second device having a drift drain structure in which a LOCOS oxide film thicker than a gate insulation film thereof is disposed at an edge of a gate electrode thereof.

Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

Abstract: A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process.

Abstract: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

Abstract: An electronic device includes a first memory cell and a second memory cell, of a nonvolatile memory array. The first memory cell includes a body region, a gate structure, a source region, and a drain region. The second memory cell includes a body region, a gate structure, a source region, and a drain region. In one embodiment, the body of the second memory cell is physically isolated from the body region of the first memory cell. A bitline segment is electrically connected to the drain region of the first memory cell and to the drain region of the second memory cell.

Abstract: A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.

Abstract: A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.

Abstract: The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (11?)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.

Abstract: Provided is a method of manufacturing a semiconductor device. According to the method, a first buried oxide layer is formed in the semiconductor substrate in a first region, such that a first semiconductor layer is defined on the first buried oxide layer. An active portion is defined by forming a trench in the semiconductor substrate in a second region. A capping semiconductor pattern is formed on a top surface and an upper portion of a sidewall of the active portion. An oxide layer is formed by oxidizing the capping semiconductor pattern and an exposed lower portion of the sidewall of the active portion, such that the oxide layer surrounds a non-oxidized portion of the active portion. The non-oxidized portion of the active portion is a core and one end of the core is connected to a first optical device formed at the first semiconductor.

Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

Abstract: One aspect of the invention relates to a method for splitting an object made of brittle material into at least two pieces. The object has a first flat surface and a second flat surface opposite to each other. The method includes etching at least one trench in at least one of the surfaces so as to form at least one line on the surface. The method also includes splitting the object into separate pieces along the line.

Abstract: A method and system for assembling a quasicrystalline heterostructure. A plurality of particles is provided with desirable predetermined character. The particles are suspended in a medium, and holographic optical traps are used to position the particles in a way to achieve an arrangement which provides a desired property.

Abstract: A process for producing a high-performance photovoltaic device by depositing a high-quality crystalline silicon layer, and a deposition apparatus for depositing the high-quality crystalline silicon layer. A process for producing a photovoltaic device that comprises forming a crystalline silicon-based photovoltaic layer comprising an i-layer on a substrate using a plasma-enhanced CVD method, wherein formation of the i-layer comprises an initial layer deposition stage and a bulk i-layer deposition stage, and the initial layer deposition stage comprises depositing the initial layer using a silane-based gas flow rate during the initial layer deposition stage that is lower than the silane-based gas flow rate during the bulk i-layer deposition stage, with the deposition time for the initial layer deposition stage set to not less than 0.

Abstract: A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

Abstract: Various embodiments of the present disclosure provide a method of simultaneously co-doping a wide band gap material with p-type and n-type impurities to create a p-n junction within the resulting wide band gap composite material. The method includes disposing a sample comprising a dopant including both p-type and n-type impurities between a pair of wide band gap material films and disposing the sample between a pair of opposing electrodes; and subjecting the sample to a preselected vacuum; and heating the sample to a preselected temperature; and applying a preselected voltage across the sample; and subjecting the sample to at least one laser beam having a preselected intensity and a preselected wavelength, such that the p-type and n-type impurities of the dopant substantially simultaneously diffuse into the wide band gap material films resulting in a wide band gap compound material comprising a p-n junction.

Abstract: A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Abstract: A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad.

Abstract: Micro-fluid ejection heads have anti-reflective coatings. The coatings destructively interfere with light at wavelengths of interest during subsequent photo imaging processing, such as during nozzle plate imaging. Methods include determining wavelengths of photoresists. Layers are applied to the substrate and anodized. They form an oxidized layer of a predetermined thickness and reflectivity that essentially eliminates stray and scattered light during production of nozzle plates. Process conditions include voltages, biasing, lengths of time, and bathing solutions, to name a few. Tantalum and titanium oxides define further embodiments as do layer thicknesses and light wavelengths.

Abstract: A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.

Abstract: A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

Abstract: A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.

Abstract: A method for forming a through silicon via (TSV) in a substrate may include forming a dielectric layer on the substrate; forming an opening through the dielectric layer and into the substrate using a single mask over the dielectric layer; expanding the opening in the dielectric layer, undercutting the single mask, to form an expanded upper portion; removing the single mask; and filling the opening, including the expanded upper portion, with a conductor. A resulting structure may include a substrate; a dielectric layer over the substrate; and a self-aligned through silicon via (TSV) extending through the dielectric layer and the substrate.

Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.

Abstract: A plasma processing method includes modifying a resist pattern of the substrate; and trimming the modified resist pattern through a plasma etching. The modifying includes: supplying the processing gas for modification from the processing gas supply unit to the inside of the processing chamber while the substrate having a surface on which the resist pattern is formed is mounted on the lower electrode; supplying the high frequency power from the high frequency power supply to generate a plasma of the processing gas for modification; and supplying the negative DC voltage from the DC power supply to the upper electrode.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: A method for controlling critical dimension (CD) of etch features in an etch layer disposed below a functionalized organic mask layer disposed below an intermediate mask layer, disposed below a patterned photoresist mask, which forms a stack is provided. The intermediate mask layer is opened by selectively etching the intermediate mask layer with respect to the patterned photoresist mask. The functionalized organic mask layer is opened. The functionalized organic mask layer opening comprises flowing an open gas comprising COS, forming a plasma, and stopping the flowing of the open gas. The etch layer is etched.

Abstract: A method for adjusting the geometry of photomask patterns is provided. Such adjusted pattern can be employed to achieve pattern doubling in subsequent layers. A patterned photoresist mask is provided over an underlayer. A polymer layer is placed over the mask. The mask is selectively trimmed to generate individual mask features having an increased aspect ratio. Subsequent pattern layers can be formed on the trimmed mask pattern to generate a hard mask having increased pattern density. The hard mask is selectively etched and the material of the trimmed mask pattern is removed. The underlayer is then etched to achieve pattern transfer from the hard mask to the underlayer to achieve a final double density pattern.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Abstract: A method for manufacturing a semiconductor device includes the steps of: loading a substrate into a reaction chamber; supplying reactive gases into the reaction chamber and processing the substrate; and unloading the processed substrate from the reaction chamber, wherein the step of processing the substrate includes: a first film formation step of setting the substrate to a first temperature and forming a first silicon film including impurity atoms on the substrate and a second film formation step of setting the substrate to a second temperature, which is lower than the first temperature, and forming a second silicon film that includes no impurity atoms or has an impurity concentration lower than that of the first silicon film on at least the first silicon film.

Abstract: Methods for selectively placing carbon nanotubes on a substrate surface by using functionalized carbon nanotubes having an organic compound that is covalently bonded to such carbon nanotubes. The organic compound comprises at least two functional groups, the first of which is capable of forming covalent bonds with carbon nanotubes, and the second of which is capable of selectively bonding metal oxides. Such functionalized carbon nanotubes are contacted with a substrate surface that has at least one portion containing a metal oxide. The second functional group of the organic compound selectively bonds to the metal oxide, so as to selectively place the functionalized carbon nanotubes on the at least one portion of the substrate surface that comprises the metal oxide.

Abstract: A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film.

Abstract: A method for increasing the Seebeck coefficient of a semiconductor involves creating a reaction cell including a semiconductor in a pressure-transmitting medium, exposing the reaction cell to elevated pressure and elevated temperature for a time sufficient to increase the Seebeck coefficient of the semiconductor, and recovering the semiconductor with an increased Seebeck coefficient.

Abstract: A building material product and a method of making building material products, having increased resistance to granule rub off and staining. The building material product comprises a substrate having embedded granules and an acrylic latex coating positioned on the granules, where the polymer of the acrylic latex coating has the repeating structural unit [CH2—C(R1)(R2)], where R1 is hydrogen or C1-C8 alkyl; R2 is hydrogen, cyano or —COOR; and R is a linear or branched hydrocarbon containing 1-22 carbon atoms, with the proviso that R1 and R2 are both not hydrogen. The method includes applying this acrylic latex water based composition to a granule embedded substrate.

Abstract: Disclosed is a printed wiring board which attains aims of printed wiring boards required for realizing high-speed, high-frequency semiconductor devices, namely a printed wiring board having low dielectric constant, low dielectric loss tangent and low linear expansion coefficient. Also disclosed is a composite woven fabric suitably used as a base material for such a printed wiring board. Specifically disclosed is a composite woven fabric containing quartz glass fibers and polyolefin fibers, in which the ratio of the quartz glass fibers to the composite woven fabric is set at 10 vol % or more and 90 vol % or less. It is preferred that the quartz glass fibers each have a filament diameter of 3 ?m or more and 16 ?m or less, and the composite woven fabric has a thickness of 200 ?m or less.

Abstract: Disclosed is the preparation of sintered cordierite-based glass-ceramic bodies via a procedure which uses three all natural starting materials which are white sand, kaolin clay and magnesite. These three raw materials are combined in relative amounts which form, upon subsequent mixing and heating, a specific mixture of oxides of silicon, aluminum and magnesium. Upon melting at 1500-1550° C., this combination of raw materials forms transparent brown glass which after solidification by quenching is then crushed and reduced to grains having a median particle size less than 65 microns. These brown glass grains are consolidated, for example by compaction, to form a green body for sintering. Sintering of the green body at temperatures between about 1000° C. and 1375° C. for from 2 to 5 hours produces glass-ceramic bodies containing a polycrystalline material which comprises mostly material of the cordierite crystal structure.

Abstract: Improved process for the preparation of an unsupported, heterogeneous olefin polymerization catalyst, comprising an organometallic compound of a transition metal of Group 3 to 10 of the Periodic Table (IUPAC) or of an actinide or lanthanide in the form of solid particles comprising the steps of a) preparing a solution of an aluminoxane and an ionic complex M-X, M being an alkali or earth alkali metal and X being a halide or pseudo halide, in a molar ratio of Al of the aluminoxane to M of the ionic complex between 80:1 and 300:1, b) mixing said solution with an organometallic compound of a transition metal of Group 3 to 10 of the Periodic Table (IUPAC) or of an actinide or lanthanide in a molar ratio of M of the ionic complex to the transition metal of the organometallic compound between 1:1 and 4:1, yielding a second solution, c) dispersing said second solution obtained in step b) in a solvent immiscible therewith to form an emulsion in which said second solution of step b) forms the dispersed phase in the fo

Abstract: Provided are a solid catalyst for propylene polymerization which includes titanium, magnesium, halogen and an internal electron donor mixture of two or more compounds wherein the internal electron donor mixture includes at least one selected from the bicycloalkanes or bicycloalkenes and at least one selected from diethers and succinates, and a method for preparing propylene using the same. As disclosed, it is possible to prepare polypropylene having an excellent stereoregularity with a high production yield.