Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.

Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Abstract: A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.

Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: Transistor devices are formed with a nitride cap over STI regions during FEOL processing. Embodiments include forming a pad oxide layer on a substrate, forming an STI region in the substrate so that the top surface is level with the top surface of the pad oxide, forming a nitride cap on the STI region and on a portion of the pad oxide layer on each side of the STI region, implanting a dopant into the substrate, deglazing the nitride cap and pad oxide layer, removing the nitride cap, and removing the pad oxide layer. Embodiments include forming a silicon germanium channel (c-SiGe) in the substrate prior to deglazing the pad oxide layer. The nitride cap protects the STI regions and immediately adjacent area during processes that tend to degrade the STI oxide, thereby providing a substantially divot free substrate and an STI region with a zero step height for the subsequently deposited high-k dielectric and metal electrode.

Abstract: A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask.

Abstract: Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify (i.e., decrease or increase) the threshold voltage within that upper portion relative to the threshold voltage in the lower portion and, thereby to selectively modify (i.e., decrease or increase) device drive current. In the case of a multiple semiconductor fins, the use of implant regions, the dopant conductivity type in the implant regions and/or the sizes of the implant regions can be varied from fin to fin within a multi-fin MUGFET or between different single and/or multi-fin MUGFETs so that individual device drive current can be optimized. Also disclosed herein are embodiments of a method of forming the semiconductor structure.

Abstract: A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.

Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

Abstract: To attain a comparatively high breakdown voltage at a high avalanche strength and with the physical size simultaneously being as small as possible, the invention proposes constructing a transistor device in a semiconductor material region in which a first source/drain region is used as a source region and in which the source region has a comparatively reduced surface charge or surface charge density.

Abstract: Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One method for fabricating a semiconductor device structure involves the steps of forming a gate structure overlying the semiconductor substrate, forming recesses in the semiconductor substrate about the gate structure, forming a stress-inducing semiconductor material in the recesses, and forming a silicon material in the recesses overlying the stress-inducing semiconductor material. In an exemplary embodiment, the silicon material formed in the recesses is epitaxially-grown on the stress-inducing semiconductor material.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.

Abstract: A phase change memory cell, e.g. a line-cell (2), and fabrication thereof, the cell comprising: two electrodes (6, 8); phase change memory material (10) and a dielectric barrier (12). The dielectric barrier (12) is arranged to provide electron tunnelling, e.g. Fowler-Nordheim tunnelling, to the phase change memory material (10). A contact (15) made of phase change memory material may also be provided. The dielectric barrier (12) is substantially uniform e.g. of substantially uniform thickness, e.g. ?5 nm.

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract: To provide a manufacturing method of a semiconductor device in which, even when the semiconductor device is formed over an SOI substrate which uses a glass substrate, an insulating film and a semiconductor film over the glass substrate are not peeled by stress applied by a conductive film in formation of the conductive film for forming a gate electrode.

Abstract: Provided is a method for transferring, onto a second substrate, at least one of functional regions arranged and joined to a first separation layer that is disposed on a first substrate and that becomes separable by a treatment, in which regions on the second substrate where the functional regions are to be transferred have a second separation layer that becomes separable by a treatment. The method includes a step of joining the first substrate to the second substrate by bonding such that the functional regions contact the second separation layer; a step of separating the functional regions from the first substrate at the first separation layer; and a step of, before or after the step of separation, forming separation grooves penetrating through the second substrate and the second separation layer from a surface of the second substrate, the surface being opposite to a surface having the second separation layer thereon.

Abstract: A photovoltaic device uses a single crystal or polycrystalline semiconductor layer which is separated from a single crystal or polycrystalline semiconductor substrate as a photoelectric conversion layer and has a SOI structure in which the semiconductor layer is bonded to a substrate having an insulating surface or an insulating substrate. A single crystal semiconductor layer which is a separated surface layer part of a single crystal semiconductor substrate and is transferred is used as a photoelectric conversion layer and includes an impurity semiconductor layer to which hydrogen or halogen is added on a light incidence surface or on an opposite surface. The semiconductor layer is fixed to a substrate having an insulating surface or an insulating substrate.

Abstract: A wafer is divided into individual devices along division lines formed on the front side of the wafer. The devices are respectively formed in a plurality of regions partitioned by the division lines. A protective member is provided on the front of the wafer, and the back of the wafer is ground to a predetermined thickness. A laser beam is applied to the wafer from the back side of the wafer along the division lines with the focal point of the laser beam set inside the wafer at a position corresponding to each division line, thereby forming a plurality of modified layers inside the wafer along the division lines. The wafer is divided along the modified layers into the individual devices, and the back side of the wafer is ground to remove the modified layers and reduce the thickness of each device to the finished thickness.

Abstract: Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool.

Abstract: A wafer dividing method including a step of applying a laser beam to a wafer along division lines with the focal point of the laser beam set inside the wafer, thereby forming modified layers inside the wafer along the division lines; a step of attaching an adhesive tape to the wafer, the adhesive tape having a base sheet and an adhesive layer; a dividing step of applying an external force to the wafer by expanding the adhesive tape, thereby dividing the wafer along the division lines to obtain a plurality of device chips; and a debris catching step of heating the adhesive tape to thereby soften the adhesive layer such that it enters the space between any adjacent ones of the device chips obtained by the dividing step, thereby catching debris generated on the side surface of each device chip in the dividing step to the adhesive layer by adhesion.

Abstract: In a conventional adhesive sheet laminated with a die attachment film, the die attachment film sometimes drops off from the die chip at the time of pick-up after die chip formation by dicing a wafer. The present invention provides an adhesive including a (meth)acrylate ester polymer, a urethane acrylate oligomer having 4 or more vinyl groups, and silicone microparticles. Another aspect of the invention, provides a process for producing electronic components, the process including: a wafer-pasting step of pasting a wafer on a surface of a die attachment film of an adhesive sheet; a dicing step of dicing the wafer into die chips; and a pick-up step of peeling the die attachment film from the adhesive layer after the dicing step, and picking up the die chip together with the die attachment film.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.

Abstract: A method of manufacturing a semiconductor device includes the steps of loading a substrate into a processing chamber; processing the substrate by supplying plural kinds of reaction substances into the processing chamber multiple number of times; and unloading the processed substrate from the processing chamber, wherein at least one of the plural kinds of reaction substances contains a source gas obtained by vaporizing a liquid source by a vaporizing part; in the step of processing the substrate, vaporizing operation of supplying the liquid source to the vaporizing part and vaporizing the liquid source is intermittently performed, and at least at a time other than performing the vaporizing operation of the liquid source, a solvent capable of dissolving the liquid source is flowed to the vaporizing part at a first flow rate; and at a time other than performing the vaporizing operation of the liquid source and every time performing the vaporizing operation of the liquid source prescribed number of times, the sol

Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

Abstract: An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask.

Abstract: Composite films comprising two-dimensional hole arrays, and related methods of preparing hole arrays.

Abstract: A silicon carbide substrate having a substrate surface is prepared. An insulating film is formed to cover a part of the substrate surface. A contact electrode is formed on the substrate surface, so as to be in contact with the insulating film. The contact electrode contains Al, Ti, and Si atoms. The contact electrode includes an alloy film made of an alloy containing Al atoms and at least any of Si atoms and Ti atoms. The contact electrode is annealed such that the silicon carbide substrate and the contact electrode establish ohmic connection with each other. Thus, in a case where a contact electrode having Al atoms is employed, insulation reliability of the insulating film can be improved.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.

Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.

Abstract: A method of forming a high density structure may include the steps of providing a substrate wherein the high density structure is to be formed with a release liner, the release liner being self-removable; forming at least one cavity in the substrate through the release liner, the at least one cavity forming at least a part of the high density structure; at least partially filling the at least one cavity with a filler material; sintering the thus formed structure; and removing the release liner from the substrate.

Abstract: A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.

Abstract: A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

Abstract: A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Abstract: A method for producing an electrical component (1) is proposed, in which a ceramic base body (5) that contains a through-hole contact (10) and at least one metallization surface (20C) electroconductively connected to the through-hole contact is provided in a method step A). On the surface of the base body, an electrically insulating first material is arranged in layer form at least above the through-hole contact in method step B), and thereafter an electrically conductive second material is applied above through-hole contact (10) in method step C). Then a solder contact (30B) that electroconductively connects through-hole contact (10) through passivation layer (25B), which is formed from the first material by sintering, is formed by hardening in method step D).

Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.

Abstract: Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

Abstract: A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle.

Abstract: A micellar solution is used to seal pores exposed at the bottom and sidewall surfaces of a structure etched in or through a porous low dielectric constant material. The micellar solution is also effective to clean away etch residues from the etched structure.

Abstract: During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 ? to about 500 ?, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.