Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of o semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.

Abstract: There is disclosed a high temperature pressure sensing system which includes a SOI, silicon carbide, or gallium nitride Wheatstone bridge including piezoresistors. The bridge provides an output which is applied to an analog to digital converter also fabricated using SOI, silicon carbide, or gallium nitride materials. The output of the analog to digital converter is applied to microprocessor, which microprocessor processes the data or output of the bridge to produce a digital output indicative of bridge value. The microprocessor also receives an output from another analog to digital converter indicative of the temperature of the bridge as monitored by a span resistor coupled to the bridge. The microprocessor has a separate memory coupled thereto which is also fabricated from SOI, silicon carbide, or gallium nitride materials and which memory stores various data indicative of the microprocessor also enabling the microprocessor test and system test to be performed.

Abstract: A semiconductor device according to one embodiment of the present invention includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate and having a conductive property, and a semiconductor element mounted on the wiring layer. In the semiconductor device, the insulating substrate is composed of cBN or diamond.

Abstract: The semiconductor module includes a base and at least one circuit substrate. The at least one circuit substrate has a supporting substrate and a semiconductor element supported by the supporting substrate. The base and/or the supporting substrate has a structure for fitting the at least one circuit substrate with the base.

Abstract: An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract: Disclosed is a silicon carbide substrate which has less high frequency loss and excellent heat dissipating characteristics. The silicon carbide substrate (S) is provided with a first silicon carbide layer (1), which is composed of a polycrystalline silicon carbide, and a second silicon carbide layer (2), which is composed of polycrystalline silicon carbide formed on the surface of the first silicon carbide layer. The second silicon carbide layer (2) has a high-frequency loss smaller than that of the first silicon carbide layer (1), the first silicon carbide layer (1) has a thermal conductivity higher than that of the second silicon carbide layer (2), and on the surface side of the second silicon carbide layer (2), the high-frequency loss at a frequency of 20 GHz is 2 dB/mm or less, and the thermal conductivity is 200 W/mK or more.

Abstract: A solid state light emitting semiconductor device including a substrate, a mesa epitaxy stacking structure, an insulating layer, a first type electrode and a second type electrode is provided. The mesa epitaxy stacking structure includes a first type semiconductor layer, an active layer and a second type semiconductor layer arranged in order. A concave area is formed in the middle of the mesa epitaxy stacking structure to expose a portion of the first type semiconductor layer. The insulating layer covers the exposed surface of the first type semiconductor layer around the mesa epitaxy structure, sidewalls of the mesa epitaxy stacking structure and a portion of surface of the second type semiconductor layer. The first type electrode is located on the exposed first type semiconductor layer in the concave area, and is surrounded by the second type electrode located on the insulating layer around the mesa epitaxy stacking structure.

Abstract: A light emitting diode is provided by the present invention which includes a pn junction-type light emitting unit having a light emitting layer (10) composed of n layers of a strained light emitting layer (12) and n?1 layers of a barrier layer (13), wherein when a barrier layer exists, the light emitting layer (10) has a structure in which one strained light emitting layer (12) and one barrier layer (13) are laminated alternately, n represents an integer of 1 to 7, and the thickness of the light emitting layer (10) is not more than 250 nm.

Abstract: Display substrates are disclosed. In one aspect, display substrates include a first signal line, a second signal line, a first detour signal line and a second detour signal line. The first signal line includes a first region and a pair of second regions disposed on opposite sides of the first region. The pair of second regions are spaced apart from the first region. The second signal line crosses the first signal line. The second signal line includes a third region and a pair of fourth regions disposed on opposite sides of the third region. The pair of fourth regions are spaced apart from the third region. The first detour signal line electrically connects the pair of second regions to each other. The second detour signal line electrically connects the pair of fourth regions to each other. Related methods are also disclosed.

Abstract: An LED package module includes a circuit board, a metal board, a plurality of chips, a plurality of wires and a molding component. The metal board directly covers the whole upper surface of the circuit board, wherein the metal board is provided with a plurality of chip-mounting pads and a plurality of openings arranged adjacent to the chip-mounting pads so as to expose the wiring area of the circuit board. The chips are respectively arranged on each of the chip-mounting pads. The wires electrically connect chips and the wiring area of the circuit board. The molding component respectively covers each chip, wires and the wiring area.

Abstract: This invention relates to a lighting device comprising a light transmissive light outlet unit (102), and light emitting diodes (104) generating light which is emitted through the light outlet unit. The lighting device further comprises a conductive layer structure (114), which is arranged as a coating on a portion of an inner surface of the light outlet unit. The light emitting diodes are mounted on and electrically connected with the conductive layer structure.

Abstract: A luminescent light source including a blue light emitting diode (LED) chip, a red LED chip, and a wavelength converting material is provided. The blue LED chip and the red LED chip respectively emit a first light and a second light. A ratio of peak intensity of the second light to peak intensity of the first light ranges from 0.36 to 0.56. The wavelength converting material is disposed around the blue LED chip or the red LED chip and emits a third light. A wavelength of the third light ranges from a wavelength of the first light to a wavelength of the second light.

Abstract: A light-emitting microelectronic device including a first N-type transistor (T1) and a second P-type transistor (T2), the respective gates of which are formed opposite one another, either side of an intrinsic semiconductor material region.

Abstract: A semiconductor light emitting device and a fabrication method thereof are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A reflective structure is formed on the light emitting structure and includes a nano-rod layer comprised of a plurality of nano-rods and air filling space between the plurality of nano-rods and a reflective metal layer formed on the nano-rod layer.

Abstract: A semiconductor light emitting device include an n-type semiconductor layer, an active layer disposed on the n-type semiconductor layer, and a first p-type semiconductor layer disposed on the active layer. The first p-type semiconductor layer has an uneven structure formed on a surface thereof. A second p-type semiconductor layer has an impurity concentration higher than that of the first p-type semiconductor layer. The second p-type semiconductor layer is disposed on the first p-type semiconductor layer and has an uneven structure formed on a surface thereof. A reflective metal layer is formed on the second p-type semiconductor layer.

Abstract: Disclosed is a light emitting device including a light emitting structure including a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a first electrode layer, a second electrode layer disposed between the light emitting structure and the first electrode layer, and an insulating layer surrounding the edge of the second electrode layer under the second conductive type semiconductor layer, the insulating layer being disposed between the second electrode layer and the first electrode layer, wherein the first electrode layer passes through the second electrode layer, the second conductive type semiconductor layer and the active layer, and contacts the first conductive type semiconductor layer, and the second electrode layer comprises a plurality of first reflective layers that contact the second conductive type semiconductor layer and are spaced from one another by a predetermined distance.

Abstract: A wavelength conversion sheet filled with a large amount of phosphor, enabling the phosphor to be easily dispersed uniformly and in a large amount near the surface of an LED element. Specifically, the sheet includes: a layer formed from a heat-curable resin composition, which contains 100 parts by mass of a resin component and 100 to 2,000 parts by mass of a particulate phosphor in which the proportion of particles having a sphericity of 0.7 to 1.0 is not less than 60% of all the particles, and which exists in a plastic solid or semisolid state in an uncured state at normal temperature, wherein the average particle diameter of the phosphor is not more than 60% of the thickness of the layer formed from the heat-curable resin composition, and the maximum particle diameter thereof is not more than 90% thereof.

Abstract: A method of manufacturing a light emitting device (LED) package includes forming a reflector using nano-imprinting to increase an intensity of light extracted toward an external environment by increasing an angle of a reflector.

Abstract: An optoelectronic component comprising an optoelectronic semiconductor chip (104) having a contact side (106) and a radiation coupling-out side (108) situated opposite; a chip carrier (102), on which the semiconductor chip (104) is applied via its contact side (106); a radiation conversion element (110) applied on the radiation coupling-out side (108); and a reflective potting compound (112), which is applied on the chip carrier (102) and laterally encloses the semiconductor chip (104) and the radiation conversion element (110); wherein the potting compound (112) adjoins an upper edge of the radiation conversion element (110) in a substantially flush fashion, such that a top side of the radiation conversion element (110) is free of the potting compound (112).

Abstract: A method of manufacturing a down-conversion substrate for use in a light system includes forming a first crystallography layer including one or more phosphor materials and, optionally, applying at least one activator to the crystallography layer, heating the crystallography layer at high temperature to promote crystal growth in the crystallography layer, and drawing out the crystallography layer and allowing the crystallography layer to cool to form the down-conversion substrate. A light system includes an excitation source for emitting short wavelength primary emissions; and a down-conversion substrate disposed in the path of at least some of the primary emissions from the excitation source to convert at least a portion of the primary emissions into longer-wavelength secondary emissions, wherein the substrate includes one or more crystallography layers, wherein each crystallography layer includes one or more phosphor materials, and optionally at least one activator.

Abstract: A semiconductor light-emitting element (1) is provided which includes a semiconductor layer (10), an n-type electrode (18) which is provided on an exposed surface (12a) of an n-type semiconductor layer, wherein an exposed surface is exposed by removing a part of the semiconductor layer (10), a transparent conductive film which is provided on the semiconductor layer (10) and a p-type electrode (17) which is provided on the transparent conductive film; a light-reflecting layer (39) is provided between the semiconductor layer (10) and the transparent conductive film, wherein at least part of the light-reflecting layer overlaps with the p-type electrode (17) in the planar view; the p-type electrode (17) comprises a pad portion (P) and a linear portion (L) which linearly extends from the pad portion (P) and has an annular structure in the planar view; the n-type electrode (18) exists in an inner area which is surrounded by the linear portion (L) and exists on a straight line (L1) which goes through a center (17a)

Abstract: Provided is a metal foil laminate that: has heat resistance; has high reflectance in the visible light range; has little decrease in reflectance in environments with a high-temperature thermal load; is compatible with large surface areas; and can be used for printed circuit boards for mounting LEDs that have excellent adhesion with metals. The metal foil laminate is characterized in that: a laminate has metal foil on at least one side of a resin layer (A) containing a polyorganosiloxane and an inorganic filler; the 90° peel strength between said resin layer (A) and said metal foil is at least 0.95 kN/m, and the mean reflectance at wavelengths of 400 to 800 nm on the surface that is exposed when the resin layer (A) is exposed by peeling and removing said metal foil is at least 80%; and the decrease in the reflectance at a wavelength of 470 nm after being treated with heat for 10 minutes at 260° C. is not more than 5%.

Abstract: The application provides an optoelectronic device structure, comprising a semiconductor stack, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode electrically connecting with the first conductivity type semiconductor layer, and further comprising a first extension electrode; a second electrode electrically connecting with the second conductivity type semiconductor layer; and a plurality of electrical restraint contact areas between the semiconductor stack and the first extension electrode, wherein the plurality of electrical restraint contact areas is distributed in a variable interval.

Abstract: A substrate includes a first lead frame, a second lead frame, and a resin layer. The first lead frame includes a heat sink and a plurality of electrodes for external connection. The second lead frame is laminated on the first lead frame and includes a plurality of wirings for mounting light emitting elements. The resin layer is filled between the first lead frame and the second lead frame. The plurality of wirings are arranged above the heat sink. The plurality of electrodes and part of the plurality of wirings are joined with each other.

Abstract: Standardized photon building blocks are used to make both discrete light emitters as well as array products. Each photon building block has one or more LED chips mounted on a substrate. No electrical conductors pass between the top and bottom surfaces of the substrate. The photon building blocks are supported by an interconnect structure that is attached to a heat sink. Landing pads on the top surface of the substrate of each photon building block are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors on the interconnect structure are electrically coupled to the LED dice in the photon building blocks through the contact pads and landing pads. The bottom surface of the interconnect structure is coplanar with the bottom surfaces of the substrates of the photon building blocks.

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract: A first group III nitride semiconductor layer has a low carbon concentration region having a carbon concentration of less than 1×1017 cm?3, and located in a region under an edge of a gate electrode closer to a drain electrode, a thickness d2 of the low carbon concentration region satisfies Vm/(110·d1)?d2<Vm/(110·d1)+0.5 where d1 is a thickness of a nitride semiconductor layer including the first group III nitride semiconductor layer and the second group III nitride semiconductor layer, and Vm is an operating breakdown voltage, and a ratio of Ron to Ron0, which is an index of a current collapse value, satisfies Ron/Ron0?3 where Ron0 is an on-state resistance in a relaxed state, and Ron is an on-state resistance measured 100 ?s after a transition from an off state to an on state under an operating voltage Vm.

Abstract: Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length.

Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W1 and a second opening having a second width W2 less than the first width. The patterned mask layer defines a multi-fin device region and an inter-device region, wherein the inter-device region is aligned with the first opening; and the multi-fin device region includes at least one intra-device region being aligned with the second opening.

Abstract: A solid-state image pickup device including a photoelectric conversion element, a floating diffusion, and an element isolation region that are disposed above a first semiconductor region has a second semiconductor region of a first conductivity type disposed on the first semiconductor region. An interface between the first semiconductor region and a portion of the second semiconductor region corresponding to the photoelectric conversion element is located at a first depth, whereas the interface between the first semiconductor region and a portion of the second semiconductor region disposed under the element isolation region and the floating diffusion is located at a second depth smaller than the first depth.

Abstract: The present invention provides a semiconductor device structure and a method for manufacturing the same. The method comprises: providing a semiconductor substrate, forming a first insulating layer on the surface of the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a stripe-type trench embedded in the first insulating layer and the semiconductor substrate; forming a channel region in the trench; forming a gate stack line on the channel region and source/drain regions on opposite sides of the channel region. Embodiments of the present invention are applicable to manufacture of semiconductor devices.

Abstract: The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.

Abstract: The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor.

Abstract: A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21?, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25?, wherein the first n-type semiconductor layer 21?, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25? are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21? and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25?.

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.

Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: A semiconductor memory device includes a substrate, a conductive layer provided on a major surface of the substrate, a stacked body, a memory film, and a channel body. The stacked body includes multiple insulating layers alternately stacked with multiple electrode layers on the conductive layer. The memory film includes a charge storage film provided on side walls of holes made to pierce the stacked body. The channel body includes a pair of columnar portions and a linking portion. The pair of columnar portions is provided on an inner side of the memory film inside the holes. The linking portion is provided inside the conductive layer to link lower ends of the pair of columnar portions. The electrode layers are tilted with respect to the major surface of the substrate. The columnar portions of the channel body and the memory film pierce the tilted portion of the electrode layers.

Abstract: A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

Abstract: A non-volatile semiconductor memory device comprises a tunnel insulating film on a semiconductor substrate, a charge storage film on the tunnel insulating film, a blocking insulating film on the charge storage film, a control gate electrode arranged on the blocking insulating film, and source/drain regions formed on the semiconductor substrate on the both sides of the control gate electrode, that the charge storage film is a silicon nitride film produced according to the catalytic chemical vapor deposition technique and that the ratio between the constituent elements: N/Si falls within the range of from 1.2 to 1.4.

Abstract: To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.

Abstract: A diode (23) is arranged near a transistor (25) to protect from ESD. The diode comprises a well (5) of a first conductivity type and a doped region (4) of a second conductivity type in opposition to the first conductivity type. The transistor comprises a doped well (2) and a doped region (1) of the first conductivity type. The well (2) of the transistor is doped lower than the well (5) of the diode.

Abstract: A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

Abstract: A trench MOSFET with closed cells having split trenched gates structure in trenched gates intersection area in cell corner is disclosed. The invented split trenched gates structure comprises an insulation layer between said split trenched gates with thick thermal oxide layer in center portion of the trenched gates intersection area, therefore further reducing Qgd of the trench MOSFET without increasing additional Rds.

Abstract: A semiconductor device provides a MOSFET having first and second regions. In the first region, a plurality of unit cells of the MOSFET device are provided. At the end of the plurality of the unit cells, a termination cell is provided. An n type layer underlies the unit cells, between the unit cells and an underlying electrode. In the unit cell region, this n doped layer is dually doped with impurities at two different densities, whereas, adjacent the termination cell, a different paradigm is provided. In one aspect, only one of the two n doped layers extends along a side of the termination cell. In a second aspect, the termination unit is in contact with an oppositely doped layer as compared to the impurities in the dual doped layer. In this way, breakdown voltage may be maintained while on-resistance is simultaneously reduced.