Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.

Abstract: A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

Abstract: A semiconductor device with a super-junction structure is provided, including: a semiconductor substrate having a first conductivity type; an epitaxial layer having the first conductivity type formed over the semiconductor substrate; a first doping region having the first conductive type formed in a portion of the epitaxial layer; a second doping region having a second conductivity type formed in a portion of the of the epitaxial layer; a third doping region having the second conductivity type formed in a portion of the of the epitaxial layer, wherein the doping region partially comprises doped polysilicon materials having the second conductivity type; a gate dielectric layer formed over the epitaxial layer, partially overlying the well region; and a gate electrode formed over a portion of the gate dielectric layer.

Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration.

Abstract: A semiconductor device having a trench gate and method for manufacturing is disclosed. One embodiment includes a first semiconductor area and a second semiconductor area, a semiconductor body area between the first semiconductor area and the second semiconductor area, and a gate arranged in a trench and separated from the semiconductor body by an insulation layer, wherein the trench has a top trench portion which extends from the semiconductor surface at least to a depth which is greater than a depth of the first semiconductor area, wherein the trench further has a bottom trench portion extending subsequent to the top trench portion at least up to the second semiconductor area, and wherein the top trench portion has a first lateral dimension and the bottom trench portion has a second lateral dimension which is greater than the first lateral dimension.

Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.

Abstract: A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.

Abstract: A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.

Abstract: An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.

Abstract: An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor.

Abstract: SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two cross coupled inverters and two pass gate transistors. A first insulating layer is deposited overlying the dummy gate electrodes and gaps between the dummy gate electrodes are filled with a second insulating layer. The second insulating layer is etched to form inter-gate openings exposing portions of the substrate. The first insulating layer is etched to reduce the thickness of selected locations thereof, and the dummy gate electrodes are removed. A gate electrode metal is deposited and planarized to form gate electrodes and local interconnections coupling the gate electrodes of one inverter to a node between the pull up and pull down transistors of the other inverter and to a source/drain of one of the pass gate transistors.

Abstract: Semiconductor devices and methods of making semiconductor devices are provided. Boron diffusion into source/drain regions is restricted by a vertical and lateral confinement area formed on the surfaces of the source/drain regions. In an aspect, a silicon-carbon layer formed on the surface of the channel region suppresses boron diffusion toward a first source/drain region and toward at least a second source/drain region.

Abstract: Semiconductor devices are provided.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

Abstract: An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation , GIDL and junction leakage.

Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Abstract: A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.

Abstract: The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures.

Abstract: Systems and methods for conductive pillars are provided. In one embodiment, a system comprises an electrical board comprising an electrical device, and a packaged die, the packaged die bonded to the electrical board. The packaged die comprises a substrate layer, the substrate layer comprising a recessed area, a conductive trace, wherein a portion of the conductive trace is formed in the recessed area, and an epitaxial device layer bonded to the substrate layer. The device layer comprises a MEMS device, and an epitaxial conductive pillar, wherein a first side of the epitaxial conductive pillar is electrically connected to the conductive trace and the second side of the epitaxial conductive pillar is electrically connected to the electrical board, wherein the epitaxial conductive pillar extends through the epitaxial device layer to electrically couple the conductive trace to an interface surface on the epitaxial device layer.

Abstract: The micro-electromechanical semiconductor component is provided with a first semiconductor substrate, which has an upper face, and a second semiconductor substrate, which has an upper face. Both semiconductor substrates are bonded resting on the upper faces thereof. A cavity is introduced into the upper face of at least one of the two semiconductor substrates. The cavity is defined by lateral walls and opposing top and bottom walls, which are formed by the two semiconductor substrates. The top or the bottom wall acts as a reversibly deformable membrane and an opening extending through the respective semiconductor substrate is arranged in the other of said two walls of the cavity.

Abstract: A semiconductor component includes a substrate, a molded package, and a semiconductor chip. The semiconductor chip is suspended on the molding compound above the substrate in the molded package in such a way that a cavity mechanically decouples the semiconductor chip from the substrate. The cavity extends along an underside facing the substrate.

Abstract: Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor.

Abstract: A capacitive pressure sensing semiconductor device is provided, which has pressure resistance against pressure applied by a pressing member and can detect the pressure surely and efficiently. The pressure sensing semiconductor device includes a pressure detecting part, which detects pressure as a change in capacitance, and a package that receives the pressure detecting part within. The pressure detecting part includes a first electrode and a second electrode disposed to oppose the first electrode, with a determined distance therebetween. Capacitance is formed between the first electrode and the second electrode, and changes according to a change in said distance caused by pressure transmitted to the first electrode by a pressing member. The package also includes a pressure transmitting member that transmits, to the first electrode of the pressure detecting part, the pressure applied by the pressing member.

Abstract: A Microelectromechanical System (MEMS) microphone includes a printed circuit board, a MEMS die, and an integrated circuit. The MEMS die is disposed on a top surface of the printed circuit board. The integrated circuit is disposed at least partially within the printed circuit board and produces at least one output signal. The output signals of the integrated circuit are routed directly into at least one conductor to access pads at the printed circuit board and the access pads are disposed on a bottom surface of the printed circuit board that is opposite the top surface.

Abstract: A capacitive pressure sensor includes: a semiconductor substrate having a reference pressure chamber formed therein; a diaphragm which is formed in a front surface of the semiconductor substrate and has a ring-like peripheral through hole penetrating between the front surface of the semiconductor substrate and the reference pressure chamber and defining an upper electrode and a plurality of central through holes; a peripheral insulating layer which fills the peripheral through hole and electrically isolates the upper electrode from other portions of the semiconductor substrate; and a central insulating layer which fills the central through holes.

Abstract: The micro-electromechanical device has a substrate. Integrated into the substrate is a micromechanical component that has a bending element which can be bent reversibly and which has a first end connected to the substrate and extends from the first end over a free space. The bending element has at least one web having two side edges, the course of which is defined by depressions introduced into the bending element and adjacent to the side edges. In order to form a homogenization region located within the web, in which mechanical stresses occurring during bending of the bending element are substantially equal, the mutual spacing of the side edges of the web decreases, as viewed from the first end of the bending element. The device further comprises at least one microelectronic component that is sensitive to mechanical stresses and embedded in the web in the homogenization region of the latter.

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract: Systems and methods are described herein for detecting particles emitted by nuclear material. The systems comprise one or more semiconductor devices for detecting particles emitted from nuclear material. The semiconductor devices can comprise a charge storage element comprising several layers. A non-conductive charge storage layer enveloped on top and bottom by dielectric layers is mounted on a substrate. At least one top semiconductor layer can be placed on top of the top dielectric layer. A reactive material that reacts to particles, such as neutrons emitted from nuclear material, can be incorporated into the top semiconductor layer. When the reactive material reacts to a particle emitted from nuclear material, ions are generated that can alter the charge storage layer and enable detection of the particle.

Abstract: An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed.

Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.

Abstract: A method of an embodiment comprises forming a dielectric layer on a first side of an image sensor substrate, and exposing the dielectric layer to ultraviolet (UV) radiation. The image sensor substrate comprises a photo diode. A structure of an embodiment comprises a substrate and a charge-less dielectric. The substrate comprises a photo diode. The charge-less dielectric layer is on a first side of the substrate, and a total charge of the charge-less dielectric results in an average voltage drop of less than 0.2 V across the charge-less dielectric layer.

Abstract: An image sensor includes a substrate formed of a material having a light absorption coefficient higher than that of silicon, and a photoelectric conversion element formed on the substrate for photoelectrically converting incident light.

Abstract: A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap filling polymer layer opposite to the photo-diodes and a second polymer arranged on the interconnect layers covers and planarizes and passivates the color filter layers. On top of the planarizing polymer there is a plurality of micro-lenses opposite to the color filters, and a third polymer layer is deposited on the micro-lenses for passivating the micro-lenses. According to the invention the polymer materials are comprised of a siloxane polymer which gives thermally and mechanically stable, high index of refraction, dense dielectric films exhibiting high-cracking threshold, low pore volume and pore size.

Abstract: A lensfree imaging and sensing device includes an image sensor comprising an array of pixels and a substantially optically transparent layer disposed above the image sensor. Nano-sized features that support surface plasmon waves are populated on the substantially optically transparent layer separating the image sensor from the nano-sized features. The nano-sized features may include apertures through a substantially optically opaque layer (e.g., metal layer) or they may include antennas. An illumination source is provided that is configured to illuminate a sample. At least one processor is operatively coupled to the image sensor. Changes to the detected transmission pattern at the image sensor are used to sense conditions at or near the surface containing the nano-sized features. Conditions may include binding events or other changes to the index of refraction occurring near the surface of the device.

Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The semiconductor apparatus includes a body part having a first surface and a second surface facing each other, a first trench formed into the first surface of the body part, a second trench formed into the second surface of the body part, an opening connecting the first trench and the second trench to each other, a first adhesion enhancer, such as a rough surface, formed on a bottom surface of the first trench, and a second adhesion enhancer, such as a rough surface, formed on the second surface of the body part.

Abstract: A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.

Abstract: Disclosed herein is a solid-state imaging element including: a semiconductor layer; a plurality of photoelectric conversion sections arranged within the semiconductor layer; and a pixel separating section disposed in a shape of a same width from a light receiving surface of the semiconductor layer to an opposite surface of the semiconductor layer from the light receiving surface in a position of separating the photoelectric conversion sections from each other for each pixel, the pixel separating section being formed by a material including an impurity.

Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.

Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.

Abstract: A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

Abstract: A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.

Abstract: A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.