Abstract: An LED device comprises a substrate, a circuit, two LED dies, a dam and a reflector. The dam divides the substrate into a first area and a second area, wherein one of the two LED dies is disposed on the first area and the other is disposed on the second area. The dam insulates radiant lights emitted from the two LED dies, whereby interference between the radiant lights can be prevented. Four separate electrodes are provided on the substrate, wherein one LED die is connected to two electrodes and the other LED die is electrically connected to the other two electrodes.

Abstract: Solid state lighting (SSL) devices (e.g., devices with light emitting diodes) with reduced dimensions (e.g., thicknesses) and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first region and a second region laterally spaced apart from the first region and an insulating material between and electrically isolating the first and second regions. The SSL device also includes a conductive material between the first and second regions and adjacent the insulating material to electrically couple the first and second regions in series.

Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a contact on one of the first or second semiconductor materials. The contact includes a first conductive material and a plurality of contact elements in contact with one of the first or second conductive materials. The contact elements individually include a portion of a second conductive material that is different from the first conductive material.

Abstract: A light emitting diode chip includes an electrically conductive substrate, a reflecting layer disposed on the substrate, a semiconductor structure formed on the reflecting layer, an electrode disposed on the semiconductor structure, and a plurality of slots extending through the semiconductor structure. The semiconductor structure includes a P-type semiconductor layer formed on the reflecting layer, a light-emitting layer formed on the P-type semiconductor layer, and an N-type semiconductor layer formed on the light-emitting layer. A current diffusing region is defined in the semiconductor structure and around the electrode. The slots are located outside the current diffusing region.

Abstract: A high luminance semiconductor light emitting device and fabrication method thereof, wherein a metallic reflecting layer is formed using a non-transparent semiconductor substrate. The device includes a light emitting diode structure on a GaAs substrate structure bonded together using a first and a third metal layers. The substrate includes a GaAs layer, a first metal buffer layer on a surface of the GaAs layer, the first metal layer on the first metal buffer layer, and a second metal buffer layer and a second metal layer at a back side of the GaAs layer. The diode structure includes the third metal layer, a metal contact layer on the third metal layer, a p-type cladding layer on the metal contact layer, a multi-quantum well layer on the p-type cladding layer, an n-type cladding layer on the multi-quantum well layer, and a window layer on the n-type cladding layer.

Abstract: A semiconductor light emitting device has a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer and a second conductive semiconductor layer on the active layer. An oxide layer is disposed around the first semiconductor layer and is provided between the substrate and active layer. The first semiconductor layer has an uneven pattern along the side edge.

Abstract: A semiconductor light emitting diode (1, LED), comprising a first and a second electrode (40, 11) for applying a voltage across an active region (4) for generation of light, a light emitting surface (6), and a plurality of photonic crystals (101, 102). Further, at least two photonic crystals (101, 102) of a first and a second type are adapted to extract light from the active region (4) and differ from each other with respect to at least one lattice parameter. Each of said at least two photonic crystals (101, 102) are associated with a respective far field pattern, wherein an arrangement of said plurality of photonic crystals (101, 102) is provided to arrange said at least two photonic crystals (101, 102). In this manner, a far field pattern is created by combining the respective far field patterns associated with each of said at least two photonic crystals (101, 102).

Abstract: A thin-film LED includes an insulating substrate, an electrode on the insulating substrate, and an epitaxial structure on the electrode.

Abstract: Disclosed is a light emitting device. The light emitting device includes a light emitting structure layer including a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer, a first light extracting structure formed on an outer portion of the first conductive type semiconductor layer and having a plurality of side surfaces and a plurality of upper surfaces formed in a step structure, and a transmissive layer on the first light extracting structure of the first conductive type semiconductor layer.

Abstract: An optoelectronic semiconductor chip having a semiconductor layer sequence with a plurality of layers arranged over one another includes an active layer with an active region which emits electromagnetic radiation in an emission direction when in operation, a first grating layer on the active layer which, in an emission direction, has a plurality of stripes in the form of grating lines extending perpendicularly to the emission direction with spaces arranged therebetween, and a second grating layer on the first grating layer which covers the stripes of the first grating layer and the spaces and which comprises a transparent material applied by non-epitaxial application.

Abstract: A light emitting diode and a method for fabricating the same are provided. The light emitting diode includes: a transparent substrate; a semiconductor material layer formed on the top surface of a substrate with an active layer generating light; and a fluorescent layer formed on the back surface of the substrate with controlled varied thicknesses. The ratio of light whose wavelength is shifted while propagating through the fluorescent layer and the original light generated in the active layer can be controlled by adjusting the thickness of the fluorescent layer, to emit desirable homogeneous white light from the light emitting diode.

Abstract: Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate.

Abstract: Disclosed is a light emitting device including a light emitting structure comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a first electrode disposed on the first conductive type semiconductor layer, a second electrode disposed on the second conductivity type semiconductor layer, and a low temperature oxide film disposed on the light emitting structure, with an irregular thickness.

Abstract: An LED base plate enabling the LED to emit high luminance white light. The base plate has a reflective surface, and protrusions disposed on the reflective surface have top portions formed with curved surfaces. The protrusions have bottom widths of 2 to 4 micrometers and heights of 1.2 to 1.8 micrometers, with adjacent protrusions having spaces of 0.6 to 3 micrometers. An InGaN epitaxy layer is coated on the reflective surface of the base plate and emits ultraviolet of wavelength in the range of 380 to 410 nanometer when the InGaN epitaxy layer is electrified. Ultraviolet light reflected by the reflective surface of the base plate and the protrusions stimulates and mixes fluorescent compounds of zinc oxide and yttrium aluminum garnet to generate complementary light of ultraviolet light. High luminance white light scatteringly emitted is used for illumination.

Abstract: A light emitting device comprises a flip-chip light emitting diode (LED) die mounted on a submount. The top surface of the submount has a reflective layer. Over the LED die is molded a hemispherical first transparent layer. A low index of refraction layer is then provided over the first transparent layer to provide TIR of phosphor light. A hemispherical phosphor layer is then provided over the low index layer. A lens is then molded over the phosphor layer. The reflection achieved by the reflective submount layer, combined with the TIR at the interface of the high index phosphor layer and the underlying low index layer, greatly improves the efficiency of the lamp. Other material may be used. The low index layer may be an air gap or a molded layer. Instead of a low index layer, a distributed Bragg reflector may be sputtered over the first transparent layer.

Abstract: An organic light emitting diode display includes a substrate, an organic light emitting diode provided on the substrate and including a first electrode, an organic emission layer, and a second electrode, a packed layer on the organic light emitting diode, and a protective layer on the packed layer, the protective layer including at least one of a graphene oxide and a graphene nitride.

Abstract: A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.

Abstract: An organic light-emitting display device is provided that has prolonged service life, lowered wiring resistance that can lower power consumption, and that is easy to manufacture. In a first embodiment, a moisture capturing layer is provided between an upper electrode and a lower electrode. A second embodiment includes a metal substrate, an organic light-emitting element on the substrate and an upper transparent electrode connected to the substrate through a contact hole. In a third embodiment, a method is provided for forming a first organic compound including a light-emitting layer, heating the first organic compound in vacuo, and forming a second organic compound.

Abstract: Disclosed is a light emitting device having a plurality of light emitting cells and a package having the same mounted thereon. The light emitting device includes a plurality of light emitting cells which are formed on a substrate and each of which has an N-type semiconductor layer and a P-type semiconductor layer located on a portion of the N-type semiconductor layer. The plurality of light emitting cells are bonded to a submount substrate. Accordingly, heat generated from the light emitting cells can be easily dissipated, so that a thermal load on the light emitting device can be reduced. Meanwhile, since the plurality of light emitting cells are electrically connected using connection electrodes or electrode layers formed on the submount substrate, it is possible to provide light emitting cell arrays connected to each other in series.

Abstract: A heterostructure contains an IC and an LED. An IC and an LED are initially provided. The IC has at least one first electric-conduction block and at least one first connection block. The IC electrically connects with the first electric-conduction block. The first face of the LED has at least one second electric-conduction block and at least one second connection block. The LED electrically connects to the second electric-conduction block. Subsequently, the first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block. The first electric-conduction block is electrically connected with the second electric-conduction block and forms a heterostructure. The system simultaneously provides functions of heat radiation and electric communication for the IC and LED resulting in a high-density, multifunctional heterostructure.

Abstract: A nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, a light emitting semiconductor layer, a first metal pad, a second metal pad, and a first magnetic material layer is provided. The light emitting semiconductor layer is disposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer. The first metal pad is electrically connected to the n-type nitride semiconductor layer. The second metal pad is electrically connected to the p-type nitride semiconductor layer. The first magnetic material layer is disposed between the first metal pad and the n-type nitride semiconductor layer. A distribution area of the first magnetic material layer parallel to a (0001) plane of the n-type nitride semiconductor layer is greater than or equal to an area of the first metal pad parallel to the (0001) plane.

Abstract: A semiconductor device may include a doped semiconductor region wherein a dopant concentration of the semiconductor region is modulated over a plurality of intervals. Each interval may include at least one portion having a relatively low dopant concentration and at least one portion having a relatively high dopant concentration. A plurality of delta doped layers may be included in the plurality of intervals. Related methods are also discussed.

Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.

Abstract: A method of fabricating a Light Emitting Diode with improved light extraction efficiency, comprising depositing a plurality of Zinc Oxide (ZnO) nanorods on one or more surfaces of a III-Nitride based LED, by growing the ZnO nanorods from an aqueous solution, wherein the surfaces are different from c-plane surfaces of III-Nitride and transmit light generated by the LED.

Abstract: A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate.

Abstract: An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: A semiconductor device includes a first transistor including a GaN-based semiconductor stacked structure formed over a substrate, a first gate electrode having a plurality of first fingers over the semiconductor stacked structure, a plurality of first drain electrodes provided along the first fingers, and a plurality of first source electrodes provided along the first fingers; a second transistor including the semiconductor stacked structure, a second gate electrode having a plurality of second fingers over the semiconductor stacked structure, the second drain electrodes provided along the second fingers, and a plurality of second source electrodes provided along the second fingers; a drain pad provided over or under the first drain electrodes, and coupled to the first drain electrodes; a source pad provided over or under the second source electrodes, and coupled to the second source electrodes; and a common pad coupled to the first source electrodes and the second drain electrodes.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, an HEMT stack spaced apart from the substrate, and a pseudo-insulation layer (PIL) disposed between the substrate and the HEMT stack. The PIL layer includes at least two materials having different phases. The PIL layer defines an empty space that is wider at an intermediate portion than at an entrance of the empty space.

Abstract: A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.

Abstract: A pH sensor is provided. The pH sensor comprises a substrate and an ion sensitive field effect transistor (ISFET) die comprising an ion sensing part that responds to pH, wherein the ISFET die is located over the substrate. The pH sensor also comprises a protective layer formed over at least a portion of an outer surface of the ISFET die and at least a portion of the substrate. Further, the pH sensor comprises a cover member mechanically coupled to the protective layer, wherein the cover member houses the ISFET die and the substrate, and wherein the cover member defines an opening proximate to the ion sensing part.

Abstract: A transistor includes a semiconductor body having a channel formed in the semiconductor body; a high dielectric constant gate insulator layer disposed over a surface of an upper portion of the channel; and a gate metal layer disposed over the high dielectric constant gate insulator layer. The channel contains Carbon implanted through the gate metal layer, the high dielectric constant gate insulator layer and the surface to form in the upper portion of the channel a Carbon-implanted region having a substantially uniform concentration of Carbon selected to establish a voltage threshold of the transistor.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.

Abstract: A method for manufacturing a semiconductor device, includes: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween. There can be provided a method capable of manufacturing a semiconductor device having high element density, high performance and high reliability, with high yield.

Abstract: In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Abstract: Disclosed are devices, among which is a device that includes a transistor and a contact. The transistor includes two terminals that may be formed in respective legs. The contact includes a first portion extending vertically, and a second portion extending perpendicularly with respect to the first portion. The second portion is wider than the first portion.

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract: The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.

Abstract: Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET transistor gate dielectric smiling, or bird's beaks, are adjustable by re-oxidation processing. An additional re-oxidation process is performed by opening a poly-silicon layer prior to forming an inter-poly oxide dielectric provided for the floating gate transistors.

Abstract: A semiconductor structure includes a semiconductor substrate having thereon a plurality of deep trenches and a plurality of pillar structures between the deep trenches, wherein each of the plurality of pillar structures comprises an upper portion and a lower portion. A doping region is formed in the lower portion. A diffusion barrier layer is disposed on a sidewall of the lower portion.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant.

Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A semiconductor device includes a substrate comprising a semiconductor material. The substrate has a surface that defines a surface normal direction and includes a P-N junction comprising an interface between a first region and a second region, where the first (second) region includes a first (second) dopant type, so as to have a first (second) conductivity type. The substrate includes a termination extension region disposed adjacent to the P-N junction and having an effective concentration of the second dopant type that is generally the effective concentration of the second dopant type in the second doped region. The substrate includes an adjust region disposed adjacent to the surface and between the surface and at least part of the termination extension region, where the effective concentration of the second dopant type generally decreases when moving from the termination extension region into the adjust region along the surface normal direction.

Abstract: A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region.

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.