Abstract: A tool for testing a magnetic disk for use in a magnetic disk drive. The tool detects surface defects or asperities by detecting a change in electrical resistance corresponding to a temperature change in a thermally sensitive layer. The apparatus includes a slider body having a thermally insulating layer formed on an air bearing surface of the slider body and a thermal sensor layer formed on the thermally insulating layer. The thermally insulating layer prevents thermal heat spikes in the thermal sensor layer (such as resulting from contact with an asperity) from dissipating quickly into the slider body itself. The thermal sensor layer is a material that exhibits a change in electrical resistance in response to a change in temperature and is preferably a PTC thermistor material which exhibits a large change in electrical resistance when a transition temperature has been reached.

Abstract: A system for detecting inductive objects includes an inductive sensor circuit for detecting changes in an electromagnetic field (“EMF”) environment and an integrated circuit (“IC”) device. The inductive sensor circuit generates an oscillating analog waveform with an envelope that indicates changes in the EMF environment. The oscillating waveform is coupled to the digital input pin of the IC. A digital interface circuit in the IC is coupled to the digital input pin and is configured for detecting if the oscillating waveform exceeds high and low threshold voltage levels. The detecting results in a digital pulse which represents changes in the EMF environment. In another implementation, a timer input capture pin can be used to detect the waveform envelope decay by storing the time when the waveform crosses a threshold value during a time period. A reduced capture time after the time period expires indicates a change in the EMF environment.

Abstract: A sensor assembly is provided for use in tracking a medical device. The sensor assembly comprises a magnetoresistance sensor capable of providing position and orientation information. In certain implementations, the magnetoresistance position and orientation sensor is originally configured for connection to a substrate using one type of interconnect approach but is modified to be connected using a different interconnect approach.

Abstract: Closed-loop current sensor comprising a magnetic circuit, a magnetic field sensor, and a compensation circuit configured to generate a magnetic field opposing a magnetic field created by an electrical current to be measured flowing in one or more primary conductors (10) extending through a central opening (38) of the magnetic circuit. The magnetic circuit comprises a magnetic core (4) made of at least two core parts (28a, 28b) assembled together to form a substantially closed magnetic circuit, wherein a second branch (32) of the magnetic circuit comprises inner (40a, 40b) and outer (42a, 42b) wall portions joined by one or more lateral wall portions (46a, 46b, 46a?, 46b?) at least partially surrounding a cavity portion (44) receiving the magnetic field sensor (8) therein, the lateral and outer wall portions extending from one or both lateral edges of the inner wall portion.

Abstract: Present embodiments are directed towards a magnetic resonance imaging method. In one embodiment, the method includes (a) performing a first magnetic resonance imaging sequence including: (i) a first preparatory composite spin locking pulse sequence having a spin lock pulse bounded by similarly oriented spin tipping pulses; and (ii) an acquisition pulse sequence to acquire first magnetic resonance data. The method further includes (b) performing a second magnetic resonance imaging sequence including: (i) a second preparatory composite spin locking pulse sequence having a spin lock pulse bounded by oppositely oriented spin tipping pulses; and (ii) an acquisition pulse sequence to acquire second magnetic resonance data. The method also includes (c) storing the first and second magnetic resonance data.

Abstract: A method of testing a sample comprising the steps of: applying an excitation to the sample; detecting a response signal from the sample; processing a first part and a second part of the response signal; and determining from the second part of the response signal information with which to enhance the first part of the response signal.

Abstract: A magnetic resonance system, comprising at least one SQUID, configured to receive a radio frequency electromagnetic signal, in a circuit configured to produce a pulsatile output having a minimum pulse frequency of at least 1 GHz which is analyzed in a processor with respect to a timebase, to generate a digital signal representing magnetic resonance information. The processor may comprise at least one rapid single flux quantum circuit. The magnetic resonance information may be image information. A plurality of SQUIDs may be provided, fed by a plurality of antennas in a spatial array, to provide parallel data acquisition. A broadband excitation may be provided to address a range of voxels per excitation cycle. The processor may digitally compensate for magnetic field inhomogeneities.

Abstract: In order to make it possible to set the optimal breath-holding imaging conditions according to the subject without extension of an imaging time or the sacrifice of image quality, one scan is divided into one or more breath-holding measurements and free-breathing measurements on the basis of the imaging conditions of a breath-holding measurement, which are input and set according to the subject, and a region of the k space measured in the breath-holding measurement is controlled. Preferably, in the breath-holding measurement, low-frequency data of the k space is measured. Moreover, preferably, imaging conditions of the breath-holding measurement include the number of times of breath holding or a breath-holding time, and the operator can set any of these values.

Abstract: A power amplifier unit for a magnetic resonance device includes at least two power amplifier modules. Symmetrical output signals from the at least two power amplifier modules are fed to a shared balun. The shared balun is provided on a printed circuit board (PCB) and is realized in a unit with the at least two power amplifier modules. The balun is configured to asymmetrize a sum signal.

Abstract: In some embodiments, apparatus and systems, as well as methods, may operate to launch a set of currents into a corresponding set of existing well casings; monitor, in a well under construction, changes in at least one of a magnetic field or an electric field perturbed by the set of currents after each one of the set is launched; and determine a location of the well under construction in relation to the set of existing well casings. In some embodiments, the activities include inducing current into a drillstring located in a well under construction; monitoring, at a set of existing well casings, changes in at least one of a magnetic field or an electric field perturbed by the current after the current is induced; and determining a location of the well under construction in relation to the set of existing well casings. Additional apparatus, systems, and methods are disclosed.

Abstract: The present invention relates to a chuck mechanism of a charge/discharge testing device for flat-rechargeable batteries and has a proposition to provide a chuck mechanism that makes it possible to lighten conventionally needed troublesome works, that is, for example, works of storing and fixing a large number of flat-rechargeable batteries in a container, and that is capable of surely chucking the flat-rechargeable batteries (electrodes).

Abstract: A battery circuit includes a monitoring circuit, an integrator circuit, and a comparator. The monitoring circuit can be used to monitor a cell and generate a monitoring signal indicating a cell voltage of the cell. The integrator circuit accumulates a difference between the monitoring signal and a first predetermined threshold over a time period to generate an integrating output. The comparator compares the integrating output to a second predetermined threshold and generates a control signal.

Abstract: A circuit used for determining a cell number of several battery cells. The circuit includes a detection block and a controller, and operates in a first detection mode and a second detection mode. The detection block is coupled to each of the battery cells. In the first detection mode, the detection block provides a terminal voltage signal indicative of a terminal voltage of a battery cell. In the second detection mode, the detection block provides a cell voltage signal indicative of a cell voltage of the battery cell. The controller compares the terminal voltage signal with a first threshold in the first detection mode and compares the cell voltage signal with a second threshold in the second detection mode, and provides a cell count signal indicative of the cell number based on the terminal voltage signal and the cell voltage signal.

Abstract: A method for detecting an in-situ fast transient event within a processing chamber during substrate processing is provided. The method includes a set of sensors comparing a data set to a set of criteria (in-situ fast transient events) to determine if the first data set includes a potential in-situ fast transient event. If the first data set includes the potential in-situ fast transient event, the method also includes saving an electrical signature that occurs in a time period during which the potential in-situ fast transient event occurs. The method further includes comparing the electrical signature against a set of stored arc signatures. If a match is determined, the method yet also includes classifying the electrical signature as a first in-situ fast transient event and determining a severity level for the first in-situ fast transient event based on a predefined set of threshold ranges.

Abstract: Disclosed is a field device which determines whether or not an abnormality which was detected is the type of abnormality which may not allow the output of a burn-out H signal, and sets a signal output for the abnormality to a burn-out L signal when the type of abnormality was one which may not allow the output of a burn-out H signal. For example, an abnormality in the D/A converter or the power supply. Therefore, a burn-out L signal is always output for an abnormality judged likely not to be able to output a burn-out H signal, and the certainty of reporting an abnormality when burn-out H is set is enhanced.

Abstract: A bus terminal is isolated from ground potential during normal operation of the vehicle. A first current is applied to the bus terminal. A current level detector is arranged to detect a first level of the first current, or a corresponding observed voltage level, that exists or flows from the bus terminal to ground. A compensator is configured to compensate for a range in the detected first level by applying a corresponding compensating voltage level to a first resistor coupled to the current level detector. An electronic data processor is capable of estimating a first isolation level between the bus terminal and ground based on the detected first level.

Abstract: A test system for testing a unit such as multiple solid oxide fuel cells. The test system includes a thermal test chamber in which a non-contact electrostatic voltage probe is mounted to scan the solid oxide fuel cells. The test system includes a detector coupled to the voltage probe to produce an output signal or display based on the measured voltages. The measured voltages are processed to compute a representative voltage for each fuel cell and to identify any defective fuel cells based on the measured voltages. The test system may be used during manufacture of solid oxide fuel cell stacks for cost effective testing to lower manufacturing costs.

Abstract: An arc fault circuit interrupter test circuit is disclosed. The test circuit incorporates a controller along with at least one power transistor, a current sense circuit and a voltage sense circuit. When the power transistor is operated, the current flowing through the transistor is sensed, and if the current is not at least equal to a threshold value, the voltage at which the power transistor is operated is increased.

Abstract: An electrical interconnection integrated device is described, comprising: a plurality of electrical terminals connectable to an integrated electronic circuit on a chip common to said interconnection device; at least an inside electrical device provided with a respective input connected to a first terminal of said plurality and a respective output; a fault detecting logic module having a first input connected to said output of the inner electrical device and provided with a detecting terminal for supplying a fault detecting signal.

Abstract: To detect accurately an insulation fault in a load circuit, Power supply lines and an electric heater (a load circuit) are connected by a detecting portion to detect a detected voltage (detected value) in accordance with the magnitude of a leakage current Id that flows through a ground between the power supply lines and the electric heater, and an evaluation as to whether or not there is a breakdown of insulation of the electric heater relative to the ground is performed by an evaluating portion based on the detected value obtained when the relay contact points are open.

Abstract: In an printed circuit board on which an integrated circuit die is mounted, an array of plated through holes (PTHs) are formed which include conductive power and ground PTH structures which are connected to provide power and ground reference voltages to the integrated circuit die, and isolated current sensing PTH structures which are formed within sensing proximity to the conductive power and ground PTH structures for sensing current switching activity in the conductive power and ground PTH structures by inductively converting dynamic current changes in the conductive power and ground PTH structures into a measurable voltage signal.

Abstract: A position detecting device includes: a position indicator operable to resonate at a first frequency, upon receipt of an excitation signal, to oscillate at a second frequency different from the first frequency so as to generate an oscillation signal, and to transmit the oscillation signal thus generated; and a position detector operable to generate the excitation signal and to transmit the excitation signal to the position indicator, and configured to perform band pass filtering and amplitude detection upon the oscillation signal received thereby for generating a processed signal, and to obtain information corresponding to position of the position indicator relative to the position detector based on the processed signal. A frequency range of the band pass filtering includes the second frequency and excludes the first frequency.

Abstract: A measuring device has a micro-electromechanical capacitive sensor which has electrodes which move toward and away from each other for measurement of a mechanical deflection of a test mass. The measuring device has a charge integrator which has an operating amplifier which has at least one amplifier input connected to the sensor and an amplifier output which is fed back to the amplifier input via an integration capacitor. The amplifier input is connected via a high-resistance electrical resistor to a terminal for an electrical common-mode reference potential. In addition to the amplifier input, the operating amplifier has an auxiliary input. The amplifier output is connected to the auxiliary input via a deep pass.

Abstract: The invention relates to a device for determining at least one parameter of at least one medium, said medium being introducible into at least one measuring path. An electric and/or electromagnetic field can be partially coupled into or out of the medium by passing at least one electric and/or electromagnetic signal into the measuring path. The measuring path comprises at least one line arrangement having at least two elementary cells arranged along the measuring path, said elementary cells comprising at least one electric path from at least one input to at least one output and comprising at least one respective capacitative element. The electrical properties of the capacitative element can by be modified by the medium. The electric and/or the electromagnetic signal can be applied to the input of a first elementary cell and the output of the first elementary cell can be connected to the input of a second elementary cell.

Abstract: This invention offers an electrostatic capacity type touch sensor that can be calibrated in a short period of time at a moment when a finger of operator or the like does not touch a touch pad. An absolute value of a difference (AD0?AD2) between a first output voltage AD0 and a third output voltage AD2 is compared with a first threshold value Vtr1 in step S10. When the difference (AD0?AD2) between the output voltages is smaller than the first threshold value Vtr1, it is judged that the finger of operator or the like does not touch the touch pad, and it is judged which of an offset in a second output voltage AD1 and an offset in the third output voltage AD2 is smaller than the other. When the offset in the second output voltage AD1 is smaller than the offset in the third output voltage AD2, the modification to the second calibration data X1 is permitted.

Abstract: A capacitance detector includes: a first capacitor with fixed base capacitance and variable capacitance; a second capacitor charged with base charge corresponding to the base capacitance; third and fourth capacitors which receive capacitance distribution from the first or second capacitor; a first switching means for charging the first and second capacitors to a first fixed voltage and charging the third and fourth capacitors to a second fixed voltage in a first section and for charging the first and second capacitors to the second fixed voltage and charging the third and fourth capacitors to the first fixed voltage in a second section; a second switching means for separating the first and second capacitors from the third and fourth capacitors and for connecting the first and second capacitors to the third and fourth capacitors; and a differential amplifier to which first and second voltages corresponding to equalized charge are differentially input.

Abstract: This is a method for analyzing the purity of water at the outlet from a purification device. It includes the following steps: a) sending the liquid at the outlet from the filter means to a resistivity measuring cell to determine its resistivity ?UPW; b) establishing a reference mode by exposing a portion of the liquid to said oxidation means (2) during a given number of significantly different time periods; c) determining by regression the resistivity at infinity ??REF of said liquid in this reference mode; d) establishing an analysis mode by causing said liquid to be analyzed to pass through the resistivity measuring cell; e) determining the resistivity at infinity ?? of said liquid in this analysis mode by successive iterations; and f) calculating the quantity of organic compounds contained in the purified liquid from this resistivity at infinity ?? and at least the values ?UPW and ??REF.

Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.

Abstract: A test head manipulator system comprising a base structure, a main arm unit configured to support a test head and to be moved relative to the base structure, an actuator having a range of motion of L, and an enhancement mechanism positioned between the main arm unit and the actuator and configured such that movement of the actuator a first distance causes the main arm unit to move a second distance that is greater than the first distance. Additionally, a fluid control system for controlling a test head manipulator system. The pneumatic control system includes a regulator configured to controllably provide an output pressure to the main fluid actuator, and a second fluidly controlled actuator configured to adjust the regulator to modify the output pressure provided to the main fluid actuator. The second actuator is configured to be positively positioned in at least four operating modes with each operating mode causing the regulator to provide a different output pressure to the main fluid actuator.

Abstract: A semiconductor device is designed to facilitate analyzing a position and a cause of the failure of an integrated circuit adopting a polyphase clock. To this end, the semiconductor device is provided with an error detecting unit that detects that a problem of the operation occurs in the integrated circuit, a clock state holding unit that holds the information of phases in a predetermined term of a two- or more-phase clock and an output unit that outputs the information of the phases in the predetermined term of the two- or more-phase clock when the error detecting unit detects that the problem of the operation occurs in the integrated circuit.

Abstract: A device and method for monitoring the material health of a structure, providing a miniaturized MEMS Kelvin probe within a housing, wherein the Kelvin probe comprises a conductive plate formed of a stable metal and positioned substantially parallel to the structure; a piezoelectric vibrator for vibrating the conductive plate; and an electrical circuit connected to the conductive plate and the structure, wherein the conductive plate and the structure form a capacitor. The device is contained in one small, lightweight package that can be placed at one or more locations of interest. The sensor can be left in-place for continuous monitoring or for active testing at desired intervals, or be brought to the aircraft at desired intervals.

Abstract: An embodiment of the present disclosure provides a method of manufacturing an array substrate, comprising at least a step of forming a TFT pattern in a pixel region and correspondingly forming a TFT testing pattern in a testing region, wherein before forming a passivation layer to cover the pixel region and the testing region, a step of removing a gate insulation layer thin film above a testing line lead in the TFT testing pattern.

Abstract: A short dummy test structure is disclosed, including a grounded shield layer above a substrate, at least two signal test pads, and a signal transmission line above the grounded shield layer and between the two signal test pads, wherein the signal transmission line is electrically coupled to the grounded shield layer. In one embodiment, the signal transmission line has a smaller total length than a total length of a corresponding signal transmission line and a device-under-test (DUT) of a test structure including the DUT. A de-embedding apparatus and method of de-embedding utilizing such a short dummy test structure are also disclosed.

Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

Abstract: In a connection structure of an electronic component and a wired circuit board, the electronic component includes a plurality of external terminals. The wired circuit board includes a metal supporting board, an insulating base layer formed on the metal supporting board, and a conductive pattern formed on the insulating base layer. The conductive pattern includes a plurality of terminal portions for connection with the plurality of external terminals. The electronic component and the wired circuit board are disposed such that the plurality of external terminals and the plurality of terminal portions face each other. The wired circuit board is bent such that the conductive pattern is warped, and by the reaction force of the warping, the terminal portions and the external terminals are abutted, and the electronic component and the wired circuit board are electrically connected.

Abstract: The method of detecting the failure of the excitation circuit of a polyphase alternator controlled by a regulator comprises the following steps: a) electrical information (Iexc) is continuously taken from the excitation circuit (1); b) the electrical information taken in step a) is continuously compared with a predetermined threshold value (Iref); c) a logic state (LT) is continuously determined according to the result of the comparison made in step b); and d) if the logic state (LT) determined in step c) persists for a time at least equal to a predetermined delay time (6), an electrical continuity fault of said excitation circuit is signalled. This method is particularly suitable for machines having a rotor equipped with permanent magnets or having a high remanence of the magnetic circuit of the rotor.

Abstract: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor.

Abstract: A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs.

Abstract: A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level.

Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

Abstract: The present invention provides embodiments of an apparatus that includes a pad configurable for connection to a voltage source that provides a first voltage and a buffer connected to the pad. The buffer includes a plurality of transistors that have nominal breakdown voltages that are less than the first voltage. The buffer is configured to maintain voltage differentials on the plurality of transistors that are less than the break-down voltage of the plurality of transistors during pull-down of a pad voltage from the first voltage to a selected low voltage level or during pull-up of the pad voltage from the selected low voltage level to the first voltage.

Abstract: A multi-stage digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, a plurality of drivers, and an output stage. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The drivers are coupled to the RF clock, and arranged for producing a plurality of intermediate signals, wherein at least one driver of the drivers is responsive to at least one bit of the digital ACW signal. The output stage is coupled to the intermediate signals, and arranged for producing an output signal.

Abstract: An integrated circuit includes a first plurality of transistors and a second plurality of transistors coupled together to form a standard cell that performs a logic function. Each of the first plurality of transistors is more critical to a speed of operation of the standard cell than any of the transistors of the second plurality of transistors. Each of the first plurality of transistors has a gate length longer than a gate length of any of the transistors of the second plurality of transistors.

Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.

Abstract: A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.

Abstract: A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.

Abstract: Systems and methods for circuits that self-correct errors due to variations in fabrication processes, voltages, and temperature (PVT), as well as input timing errors. In an exemplary embodiment, a method for improving output signal quality in a complementary logic circuit is provided. An n-type transistor in the complementary logic circuit is digitally enabled or biased with a first variable power supply. A p-type transistor in the complementary logic circuit is digitally enabled or biased with a second variable power supply, providing a voltage different from that of the first variable power supply, to mitigate a difference in the switching times between the p-type transistor and the n-type transistor.

Abstract: A device having a voltage mode driver with tunable amplitude and resistance that supports a predetermined output resistance and output amplitude is described herein. The voltage mode driver includes multiple configurable drivers. The voltage mode driver is controlled by a control module. Resistance tuning is controlled by the number of active configurable drivers and amplitude tuning is controlled by setting the high or low drive state of each active configurable driver. The slew rate of the device is controlled by delaying the setting of the high or low drive state of an active configurable driver by a predetermined interval.