Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.

Abstract: There is offered a switching device control circuit that can accurately estimate a temperature of a power device to execute thermal shutdown without increasing the number of terminals. The control circuit has an output unit controlling an operating current flowing through an IGBT based on an input signal, a temperature detection unit outputting a detection signal when a temperature of the control circuit rises above a second preset temperature that is set corresponding to a first preset temperature of the IGBT after the IGBT commences its operation, and an output control unit controlling the output unit so as to turn off the IGBT in response to the detection signal.

Abstract: Disclosed herein is a solidstate switch driving circuit for a vehicle. The solidstate switch driving circuit includes an oscillation circuit, a constant voltage circuit, a first Field Effect Transistor (FET), a second FET, a third FET configured, a first time constant circuit, a first time constant circuit, a reverse voltage protection diode, a solidstate power switch, and a second time constant circuit. The first time constant circuit is connected to the drain of the second FET and the drain of the third FET. The reverse voltage protection diode has an N pole and a P pole. The solidstate power switch selectively turns on and off power applied to the load. The second time constant circuit has one side connected to the first time constant circuit and the reverse voltage protection diode, and another side connected to a gate of the solidstate power switch.

Abstract: An integrated circuit for switching a transistor is disclosed. In some embodiments, an operational amplifier is configured to drive a transistor, and slew rate control circuitry is configured to control the slew rate of the transistor source voltage during turn on. The transistor source voltage is employed as feedback to the operational amplifier to facilitate closed loop control of the transistor source voltage during switching of the transistor.

Abstract: A clock generator with comparator error compensation includes an amplifier which develops an error voltage based on a difference between a sample voltage of a charge voltage and a predetermined reference voltage. The charge voltage develops a clock signal, such as a sawtooth waveform. A comparator compares the charge voltage with the error voltage to develop a compare signal. A sample and discharge control network is operative to develop the sample voltage in response to the compare signal, and then to switch between charging and discharging of the charge voltage. The amplifier develops the error voltage to ensure that the charge voltage switches at a level of the reference voltage to eliminate comparator errors, such as switching delay or input offset voltage. A second comparator and another amplifier may be provided to control switching in both directions, such as for developing a triangular waveform or the like.

Abstract: A digital power-on reset circuit for an electronic device includes at least one reset register and a comparator circuit. The power-on reset circuit is incorporated into the electronic device and the comparator circuit is configured to compare values in the at least one reset register with at least one predetermined value when a power-on reset state is determined and generate a reset signal when the values do not match the at least one predetermined value.

Abstract: An electronic device includes a DC-DC converter for voltage conversion in a slave mode an in a master mode and including a phase locked loop. The phase locked loop comprises a controlled oscillator, a filter having an integration capacitor coupled to a control input of the controlled oscillator, a charge pump, and a phase frequency detector. In the slave mode, the controlled oscillator, the filter, the charge pump and the phase frequency detector are coupled to operate as the phase locked loop. There is a comparator coupled with an input to a control input of the controlled oscillator and with an output to the charge pump. In the master mode, the comparator is configured to control the charge pump in response to a control signal at the control input of the controlled oscillator when the phase frequency detector is switched off so as to perform a modulation of the control signal at the control input of the controlled oscillator by charging and discharging the integration capacitor.

Abstract: A phase-locked loop apparatus (PLL apparatus) and a tuning voltage providing circuit thereof are provided. The PLL apparatus is for receiving an input signal and producing an output signal according to the received input signal. The PLL apparatus includes a voltage-controlled oscillator (VCO), a loop filter and a tuning voltage providing circuit. The VCO receives a control voltage and produces the output signal according to the received control voltage. The loop filter has a resistor-capacitor network and the network receives the control voltage and is coupled to a reference voltage. The tuning voltage providing circuit receives the output signal and the input signal and provides a tuning voltage to the resistor-capacitor network according to the input signal and the output signal.

Abstract: An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example.

Abstract: A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.

Abstract: A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit digital values. Each multi-bit value is indicative of a time difference between an edge of FR and a corresponding edge of FV. The PDC decoder portion includes sequential logic elements that are clocked to capture the multi-bit digital values. In order to prevent metastability, the timing of when the sequential logic elements are clocked to capture the multi-bit digital values is adjusted as a function of the phase difference between FR and FV. In one specific example, if the phase difference is small then the falling edge of FR is used to clock the sequential logic elements, whereas if the phase difference is large then the rising edge of FR is used.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: A latch device is provided with a driver and a shadow latch. The driver has an input to accept a binary driver input signal, an input to accept a clock signal, and an input to accept a shadow-Q signal. The driver has an output to supply a binary Q signal equal to the inverse of the driver input signal, in response to the driver input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the driver input signal, and an input to accept the clock signal. The shadow latch has an output to supply the shadow-Q signal equal to the inverted Q signal, in response to the driver input signal and clock signal.

Abstract: The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.

Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.

Abstract: A method for generation of high frequency, non-overlapping clocks may include receiving input clock signals at a clock input node of a circuit. Multiple feedback signals may be received at a number of input feedback nodes of the circuit. At a startup node, a startup signal of the circuit may be received, and, in response to receiving the startup signal, an output clock may be generated at a predefined portion of at least one of the received input clock signals. A stable high frequency output clock may be generated at an output stage by utilizing the feedback signals received by the input feedback nodes.

Abstract: A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.

Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a difference between a supply voltage and a first input voltage and a constant current supply. The current passing through the voltage controlled resistance circuit is based upon a difference between the voltage supply and a second input voltage. The first transistor may be configured to mirror the current passing through the voltage controlled resistance circuit.

Abstract: Disclosed is a signal distribution device which is provided with: supply lines (5) for supplying input signals to switching elements in signal distribution circuits; and distribution lines (6) for distributing the input signals to output terminals via the switching elements. The corresponding one of the supply lines (5) and at least one of the distribution lines (6) each have an extension section (5a) and an extension section (5b) which extend in an extending direction of a control line (13). A selection signal for switching on/off the associated switching element is applied to the control line (13). The extension sections (5a and 5b) are formed at positions that do not overlap the edge portions of the control line (13) in the extending direction thereof.

Abstract: The active rectifier circuit and related method of operation disclosed herein is self-powered and improves the efficiency and reliability of photovoltaic solar power systems by replacing the conventional bypass and blocking rectifiers used in such systems. The circuit includes a power MOSFET used as a switch between the anode and cathode terminals, and control circuitry that turns on the MOSFET when the anode voltage is greater than the cathode voltage. The method of operation utilizes resonance to produce a large periodic voltage waveform from the small anode-to-cathode dc voltage drop, and then converts the period voltage waveform to a dc voltage to drive the gate of the power MOSFET.

Abstract: An apparatus includes a sensor array with a plurality of active pixels. Each active pixel in the sensor array includes: a three transistor (3T) sensor with a source follower transistor, and a detection diode coupled in series to a parasitic capacitor at a sensing junction. A gate of the source follower transistor amplifier is coupled to the sensing junction. The apparatus includes an insulator layer over the sensor array. The insulator layer provides a variable capacitance to the sensing junctions of underlying active pixels in response to portions of an object being proximate to the insulator layer. The variable capacitance is used to detect an image of the object.

Abstract: Methods and apparatus for matching voltages between two or more circuits within an integrated circuit is disclosed. The apparatus includes a comparator circuit, comparing supply voltages to first and second circuits. The comparator outputs a variable error voltage based on the comparison, the error voltage related to the difference in voltages. The error voltage is supplied to a variable current control circuit that variably sinks one of the supply voltages to a common potential in order to increase the IR drop in the circuit supplying voltage to one of the first and second circuits, thereby affording voltage adjustment in order to match the first and second circuits. A corresponding method is also disclosed.

Abstract: A controlled charge pump comprises a clock operated charge pump having an output terminal to provide an output voltage. A first sub-circuit is coupled to the output terminal of the clocked operated charge pump and adapted to provide a first control signal in response to a comparison of the output voltage with a first reference signal. A second sub-circuit is coupled to the clocked operated charge pump and provides a second control signal in response to a comparison of a switch current within the clocked operated charge pump with a second reference signal. A clock skip controller is adapted to control the mode of operation of the clocked operated charge pump in response to that first and second control signals.

Abstract: Disclosed is a charge pump having first and second outputs and at least one capacitor. A plurality of switches are coupled to the at least one capacitor for selectively coupling the at least one capacitor between a high voltage node and a low voltage node, and for selectively coupling the at least one capacitor to the first output and the second output. A switch controller is adapted to generate control signals for the plurality of switches to selectively couple the at least one capacitor between the high voltage node and the low voltage node during charging, and to selectively couple the at least one capacitor to the first output and the second output during discharging that output a first voltage pulse from the first output and a second voltage pulse from the second output such that the first voltage pulse and the second voltage pulse are asymmetrical and coincidental.

Abstract: Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Abstract: A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage.

Abstract: A filter network having a variable cut-off frequency can be controlled in a way that allows the cut-off frequency to be changed gradually to avoid undesirable transient effects. An impedance network (such as a resistor network) that provides a plurality of impedance values is provided. Logic, and a corresponding method, are provided to change the impedance value gradually, such as on a step-wise basis, to change the cut-off frequency gradually. The size of the impedance step and the duration of the step can be preprogrammed, and may be different for different types of events that trigger the need for a frequency change. It may also be possible for those preprogrammed values to be initial values only, with the values changing under programmed control during the frequency changing process. Other values, such as the initial and target impedance values that determine the initial and target frequency, also may be programmable.

Abstract: A high frequency circuit device includes: two transmission lines having ends which are opposed to each other and are spaced from each other; a capacitor that is mounted on the end of one of the two transmission lines and has a lower face electrode acting as a mount face and an upper face electrode positioned higher than the lower face electrode; a resistor element that is provided on a region between the ends of the two transmission lines and connects the ends of the two transmission lines; and a connection conductor electrically connecting the upper face electrode of the capacitor and the other of the two transmission lines.

Abstract: A signal processing apparatus is provided that comprises a signal path including first and second signal processing stages for processing a signal. A switch, in a first state couples and in a second state de-couples an output of the first signal processing stage to an input of the second signal processing stage. An auxiliary stage coupled to the output of the first signal processing stage generates a control signal dependent to a DC level at the output of the first signal processing stage, on a DC level in the auxiliary stage, and indicates a DC offset at an output of the second signal processing stage. A calibration circuit, responsive to the control signal, adjusts a DC level in the signal path preceding the output of the first signal processing stage when the switch is in the second state.

Abstract: Various embodiments are described herein for a multi-channel class-D amplifier and an associated processing method. In general, the multi-channel class-D amplifier comprises a signal source that provides a plurality of input signals and generates synchronization information; and a plurality of class-D amplifier channel modules, each class-D amplifier channel module being configured to process a corresponding input signal from the plurality of input signals according to the synchronization information to produce an output signal. The switching frequencies employed by the plurality of class-D amplifier channel modules are substantially similar to one another and the processing of the plurality of input signals is offset in time across the plurality of class-D amplifier channel modules.

Abstract: An exemplary embodiment discloses a digital control block for dynamically regulating power consumption of the transmitter; and a first driver amplifier circuit comprising a plurality of bias-modes each corresponding to a power consumption level in the transmitter, the digital control block to instruct the first driver amplifier circuit to operate in a selected bias-mode to regulate power consumption of the transmitter.

Abstract: In various embodiments, a pilot signal generation circuit is provided having an operational amplifier buffer connected via a first resistor to receive a source reference voltage. A differential amplifier is connected at a first input to receive the source reference voltage and at a second input to an output of the operational amplifier buffer. A first shunt transistor is connected to shunt the source reference voltage at the operational amplifier buffer in response to pulse width modulated signal. A second shunt transistor is connected to the differential operational amplifier so as to shunt the source reference voltage in response to an output of the first shunt transistor. The output of the differential amplifier provides a pulse width modulated bipolar signal at precision voltage levels in response to the pulse width modulated signal.

Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.

Abstract: A variable gain amplifier circuit includes output nodes, a plurality of amplifiers, and a detection circuit. The amplifiers are coupled in parallel with each other between the output nodes and a reference node and selectively assume an operating state in accordance with a control signal. The detection circuit outputs a detection signal according to the magnitude of an input signal to each amplifier. Each amplifier includes a first transistor, a second transistor, and a bias circuit. The first transistor receives, at its control electrode, the input signal or a signal proportional to the input signal. The second transistor is series-coupled to the first transistor between the first reference node and an output node. The bias circuit applies a DC voltage of a magnitude according to the detection signal to a control electrode of the second transistor.

Abstract: The present invention is directed to systems and methods for reducing the distortion of power amplifiers. In particular, methods and systems are described that enable a determination of a pre-distortion correction signal to be determined, which when added to the nominal signal, a reduction in the distortion of the power amplifier results. In addition, methods and systems are described that enable calibration of individual power amplifiers to be accomplished for use with the above described approach. More specifically, the methods and systems are described for use in a MIMO application. These approaches may be applied to on-chip power amplifiers, off-chip power amplifiers, or any combination thereof.

Abstract: A class-D power amplifier includes a switching power source section, a synchronization signal generation section and a class-D power amplifying section. The synchronization signal generation section takes out of the switching power source section a clock signal having a second frequency which is “n” times of a first frequency. The class-D power amplifying section includes a comparator which compares an input signal with a feedback signal, a second switching section which switches a power source fed from the synchronization signal generation section, a filter section which smoothes an output signal from the second switching section, and a combining section which combines a delayed output signal with a clock signal from the synchronization signal generation section to generate the feedback signal.

Abstract: An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

Abstract: A power amplifier using N-way Doherty structure with adaptive bias supply power tracking for extending the efficiency region over the high peak-to-average power:ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.

Abstract: A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

Abstract: A spread spectrum oscillator includes a high frequency oscillator circuit configured to oscillate at a first frequency, and a low frequency oscillator circuit configured to oscillate at a second frequency and resistively coupled to a current summing node of the high frequency oscillator circuit. The first frequency is higher than the second frequency.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal oscillating at a frequency in response to a first control signal and a second control signal. The second circuit may be configured to generate the second control signal in response to (i) an input voltage and (ii) the output signal. The second circuit (i) generates the second control signal by comparing a peak voltage of the output signal to the input voltage and (ii) adjusts an amplitude of the control signal in response to the comparison.

Abstract: There is provided an oscillation drive device that forms an oscillation loop with a vibrator for exciting a driving vibration on the vibrator.

Abstract: A driver circuit includes a comparator (drive signal generation section) that generates a drive signal based on a signal obtained by converting an oscillation current of a vibrator that has been input via a first signal line into a voltage using an I/V conversion circuit (current/voltage conversion section), and supplies the drive signal to the vibrator via a second signal line, an oscillation detection circuit (oscillation detection section) that detects whether or not the oscillation current has reached a predetermined value after the vibrator has started to oscillate, a startup oscillation circuit (startup oscillation section) that assists an oscillation operation of the vibrator until the oscillation current reaches the predetermined value, and a switch that separates a capacitor from the second signal line until the oscillation current reaches the predetermined value, and connects the capacitor to the second signal line when the oscillation current has reached the predetermined value.

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract: There is provided a communication system including a transmitter and a receiver, each including a communication circuit unit that processes a high-frequency signal for transmitting data, a band-pass filter, and a high frequency coupler, a distributed constant line connecting the high frequency coupler and the band-pass filter of the transmitter, and a distributed constant line connecting the high frequency coupler and the band-pass filter of the receiver, wherein an electrical length of the distributed constant line of the transmitter is different from an electrical length of the distributed constant line of the receiver.

Abstract: A transmission medium includes inductive couplers, signal lines and conductors. Each of the signal lines is configured to receive a respective one of multiple input signals. Each of the signal lines extends through at least one of the inductive couplers and is configured to inductively transmit one of the input signals to the at least one of the inductive couplers. Each of the conductors is configured to extend through at least two of the inductive couplers. The conductors include a first conductor and a second conductor. The inductive couplers are configured to inductively transmit the input signals to the conductors to generate a first current and a second current. The first current flows in the first conductor and towards an output of the first conductor. The second current flows in the second conductor and towards an input of the second conductor.