Abstract: A coaxial cable connector system is provided. The system includes a coaxial cable connector, the connector having an internal physical parameter sensing circuit configured to sense a physical parameter of the connector and a status output component. The system further includes a data reader located externally to the connector. The reader includes a receiver element, a memory unit, a transmitter element, and a decision logic unit. The receiver element receives information about the connector, via the status output component, from the physical parameter sensing circuit. The memory unit stores predefined threshold limits of the physical parameter of the connector. The transmitter element is adapted to send the information over a network. The decision logic unit is adapted to compare the received information with the threshold limits and, if the received information exceeds the threshold limit, transmits the information over the network.

Abstract: An in-vehicle communication system is disclosed. The in-vehicle communication system is configured to connect a short range wireless communication link between an in-vehicle apparatus and a portable device, and predicts a battery level threshold reach time, which is a time when a battery level of a battery of the portable device reaches below a threshold. When it is determined that the battery level threshold reach time is prior to a vehicle travel end time, the in-vehicle communication system notifies the passenger of prompt battery charge information to prompt the passenger to charge the battery of the portable device.

Abstract: Methods, systems, and products are disclosed for interfacing with a power line network. Electrical power is received, and a voltage of the electrical power is monitored. When the voltage is inadequate, then an alternate power source is automatically connected. A frequency of electrical power provided by the alternate power source is monitored, and high frequency data signals are separated from low frequency power signals.

Abstract: Techniques for detecting a signal quality decrease are disclosed. A sensor or probe may be used to obtain a plethysmograph or photoplethysmograph (PPG) signal from a subject. A wavelet transform of the signal may be performed and a scalogram may be generated based at least in part on the wavelet transform. One or more characteristics of the scalogram may be determined. The determined characteristics may include, for example, energy values and energy structural characteristics in a pulse band, a mains hum band, and/or a noise band. Such characteristics may be analyzed to produce signal quality values and associated signal quality trends. One or more signal quality values and signal quality trends may be used to determine if a signal quality decrease has occurred or is likely to occur.

Abstract: An automatically operating injection device with an occlusion alarm unit and a method for determining an injection occlusion are disclosed. The method includes generating a plurality of evaluation forces based on a series of force measurements and based on an evaluation time period; determining whether an occlusion exists based on either an evaluation of the plurality of evaluation forces or whether one or more of the series of force measurements exceeds a force threshold; and providing an injection occlusion alarm if an occlusion is determined to exist.

Abstract: A lifting device sensor unit is disclosed. In one embodiment, the sensor unit comprises a housing configured to removably couple about a load line of a lifting device. A first global navigation satellite system (GNSS) receiver is coupled with the housing and is configured for determining a sensor unit position in three dimensions. A load monitor is coupled with the housing and is configured for monitoring a load coupled with the load line, including monitoring a load position and a load orientation of the load. A wireless transceiver is coupled with the housing and is configured for wirelessly providing information including the load position, the load orientation, and the sensor unit position, to a display unit located apart from the sensor unit.

Abstract: An electronic apparatus including: a first device that includes a first display portion, the first display portion displaying information concerning the operation of the first device; and a second device that includes a second display portion, the second display portion displaying the information which the first display portion has displayed, depending on at least one of the second device having been attached to the first device, the first device having supplied an electric power to the second device, and the first device and the second device having communicated mutually.

Abstract: A database for storing intersection data efficiently is disclosed. The database stores two or more points for each approach to the intersection along with the intersection control type. A third point can be used to help define the geometry of each approach. The database can be used with a warning system or any other vehicle system. The system may use approach point and intersection control type information to provide warnings to drivers of the motor vehicle when the motor vehicle is approaching the intersection at such a speed that the motor vehicle cannot safely stop. Methods for distributing the database information are also disclosed. The methods include pre-installed databases, dealer installed databases and on-demand distribution of intersection information.

Abstract: A method of identifying an intersection for a collision warning system is disclosed. The method includes steps of selecting an identified intersection where a driver intends to turn from a set of potential intersections. The collision warning system is then controlled according to the identified intersection.

Abstract: Disclosed is a roadside-to-vehicle communication system which allows a vehicle, which is traveling within a roadside-to-vehicle communication area, to receive signal information from a roadside device multiple times. The roadside-to-vehicle communication system includes determination means for determining whether or not new information is added to the signal information transmitted from the roadside device, and update means for, only when the determination means determines that the new information is added to the signal information, updating the signal information which is used on the vehicle side. With this configuration, it is possible to reduce the processing load on the signal information even when the signal information is received multiple times through roadside-to-vehicle communication.

Abstract: An invention regarding traffic management is disclosed. A system that tells motorist how fast to go in order to make it through a traffic signal while it is green serves one or more lanes in one or more directions. A Fast Lane On Warning (FLOW) sequencer is in synchronization with traffic phases sequencer (sequencing Red, Green, Yellow, Left Turn and the like) with both sequencers having service cycle period Pi but with start times of both sequencers offset from one another. The FLOW sequencer outputs data, particularly status of signal or “Signal Phase And Timing: SPAT” through wireless means to a mobile receiver/calculator/readout aboard the approaching vehicle. The receiver/calculator/readout also receives data of its location or whereabouts, particularly its distance to the intersection.

Abstract: A system and method of parking assist includes a detection device located in a rear portion of a vehicle. The detection device acquires data representative of a viewable area behind the vehicle. The detection device is in communication with a park assist controller. A first viewable area that includes an area where a tow device is located when attached to the rear portion of the vehicle is monitored, where the first viewable area is associated with a first field of view (FOV). If the tow device is detected within the first viewable area, the park assist controller switches between the first FOV to a second field of view (FOV) associated with a second viewable area, where the second viewable area does not include the area where the tow device is located. Feedback is provided to a display indicating if an obstacle is located within the second FOV.

Abstract: The system allows a reliable and automatic detection of moving vehicles and advantageously also identification of the moving vehicles. A WPAN node device (advantageously a ZigBee node device) is installed on a vehicle to be detected when the vehicle is moving. Three WPAN node devices (advantageously three ZigBee node devices) are installed on the ground. One of the three WPAN node devices has a wide radio coverage area and acts as an “exciter” of the vehicle WPAN node device. Another one of the three WPAN node devices has a wide radio coverage area and acts as the “parent” of the vehicle WPAN node device. A further one of the three WPAN node devices has a narrow radio coverage area and acts as a “detector” of the vehicle WPAN node device. The three radio coverage areas are sized and located so that a moving vehicle to be detected enters the area of the “exciter” before entering the area of the “parent” and before entering the area of the “detector”.

Abstract: Improved power management for a vehicle locating unit is achieved by receiving a transmission from a communication source, each transmission including at least one message frame having a data field and at least one auxiliary field; entering a wake mode upon indexing the assigned message frame of the receiver in the transmission; matching the pattern of bits of at least one auxiliary field of the indexed frame with one or more stored patterns of bits expected for that auxiliary field; and returning to the sleep mode as soon as a mismatch is determined or processing the message if no mismatch occurs.

Abstract: A navigation device includes a communication module 11 for transmitting and receiving a signal to and from external communication equipment, a tone signal identifying unit 42 for identifying a push tone signal sent thereto via the communication module 11 from the external communication equipment, and a voice recognition unit 41 for performing voice recognition on a voice signal sent thereto via the communication module 11 from the external communication equipment by using information identified by the tone signal identifying unit 42.

Abstract: Switching circuitry comprising a bank of actuatable switches connected in parallel between a supply terminal and a decoding terminal, each switch being connected in series with a component which, when the switch is actuated, applies to the second terminal an analog signal having a value unique to that switch.

Abstract: In response to receiving an input string to be compressed, a plurality of diverse lossless compression techniques are applied to the input string to obtain a plurality of compressed strings. The plurality of diverse lossless compression techniques include a template-based compression technique and a non-template-based compression technique. A most compressed string among the plurality of compressed strings is selected. A determination is made regarding whether or not the most compressed string was obtained by application of the template-based compression technique. In response to determining that the most compressed string was obtained by application of the template-based compression technique, the most compressed string is compressed utilizing the non-template-based compression technique to obtain an output string and outputting the output string.

Abstract: Digital methods and systems for signal processing and filtering are provided. The methods and corresponding systems provide asynchronous conversion of sampling rate frequencies and utilize advanced multistage phasor filters for converting an input signal having a first sampling rate into an output signal sampled in an arbitrary sequence of sampling times. The conversion process provides a sequence of sets of complex numbers representing a filtered version of the input signal. More specifically, the conversion process includes the calculation of values of the output signal by multiplying (e.g., scaling) the sets of complex numbers by a corresponding set of complex phasors, the complex phasors corresponding to the timing of the arbitrary time sequence to obtain a corresponding set of real results with the value of the output signal being the sum of the real results.

Abstract: A system and method that process encoded data, wherein the encoded data is an encoded video stream. The encoded data may be buffered and the characteristics of the buffered encoded data may be determined and used to select a decoding table from a plurality of decoding tables. An encoded word may then be decoded using the selected decoding table. The output of the decoding table may be the corresponding decoded word and the size of the encoded word. The size of the encoded word may be utilized to shift the buffered encoded data. The decoded word may be sent to the appropriate portion of the system.

Abstract: An embodiment of a bit converter includes a substitution module and an output module. The substitution module substitutes a decision result representing one of “0” and “1” for input bit information based on a substitution rule for bit information for converting a bit string of a predetermined pattern into a predetermined code word. The output module outputs the decision result of the bit information substituted by the substitution module, to a decoder configured to decode the decision result into the predetermined code word.

Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.

Abstract: A calibration method disclosed herein calibrates at least one of a capacitive load and a charging current controlling a charge-to-digital timer (CDT). In general, the disclosed calibration method measures multiple calibration phases based on start and stop signals separated by a known time difference, and therefore having a known phase, and adjusts at least one of the capacitive load and the charging current of the CDT based on the measured calibration phases. In so doing, the disclosed calibration method reduces power dissipation and peak supply currents over the frequency range of the CDT.

Abstract: A method of digitizing an analog electrical signal combines optical and electronic techniques in order to improve the resolution, sampling rate, input frequency range, or flexibility. It implements an optical interferometric modulator, which modulates an input optical signal by the input electrical signal combined with a calibration signal. A set of two or more photoreceivers receiving the output optical signals from the optical modulator produce output electrical signals, which are digitized and processed in a DSP to produce a digitized version of the electrical input signal, and a digitized calibration signal value is used to optimize the input electrical signal digitization. The method and the device can be used in many fields including instrumentation, communications, and imaging.

Abstract: Systems, methods, and circuits provide a time to digital converter comprising a sigma-delta modulator. The sigma-delta based time to digital converter may receive an analog signal representing a phase error between a reference clock signal and a feedback clock signal and generate a digital signal representing the phase error. The sigma-delta modulator may comprise a subtractor, an integrator, a feedback path, and a quantizer. The subtractor may receive the analog signal and subtract a feedback signal from the analog signal and the integrator may integrate the output of the subtractor. The sigma-delta modulator may accumulate a voltage or a charge over a capacitor as pulses are received from the analog signal and after a number of clock cycles, the capacitor may be discharged to generate a pulse in an output signal.

Abstract: Dual digital to analog converters (DACs) with codeword parsing. With respect to a codeword that is provided to a DAC, a processing module (e.g., a rollover processor) operates to divide, partition, etc. the codeword into different respective sub-codewords as may be provided to two or more DAC's. Adaptation with respect to differently generated sub-codewords with respect to different respective codewords may be made in terms of any one or more of a variety of characteristics, including sub-codeword width (e.g., the number of bits included within a sub-codeword), quantization steps, etc. Moreover, such adaptation may be in consideration of any one or more local and/or remote operating characteristics of one or more devices, communication links, etc. within a communication system or network. Different respective sub-codewords undergo processing by different respective DAC's in generating respective analog signals for combination in generating a final or output analog signal.

Abstract: A multi-DAC system includes a plurality of DACs arranged in parallel for converting a digital signal to an analog signal, each DAC path having a different analog phase response. The system further includes a circuit for multiplying the digital signal input to at least some of the DACs by a multiplicand sufficient to shift a peak of a frequency response of the multi-DAC system to a non-DC frequency. For example, a series of +1 and/or ?1 digital values can be used to multiply the digital signal so that the signal has the same number of bits pre and post multiplication. The multiplicand can include a constant series of +1 or ?1 digital values, or a time-varying series of +1 and ?1 digital values. In each case, the peak frequency response of the multi-DAC system can be shifted away from DC to a multiple of the sampling frequency of the DACs.

Abstract: A DA conversion device includes a current output type DA converter, a high-speed operational amplifier operating at a low voltage and configured to generate a voltage corresponding to an output current from the DA converter, and a buffer amplifier connected to an output terminal of the high-speed operational amplifier and operating at a high voltage. The device also includes positive and negative floating power supplies separated from a power supply system and provided as power supplies for driving the DA converter and the high-speed operational amplifier. A midpoint between potentials at the floating power supplies is connected to an output terminal of the buffer amplifier to cause the DA converter and the high-speed operational amplifier to operate mainly based on an output voltage from the buffer amplifier.

Abstract: A dual resistor ladder DAC includes a coarse ladder including a plurality of coarse ladder resistors and a fine ladder including a plurality of MOS transistors coupled between first and second conductors. A first group of parallel-connected bit-shifting transistors is coupled between the first and third conductors. A second group of parallel-connected MOS bit-shifting transistors is coupled between the third and top conductors. A third group of parallel-connected bit-shifting transistors is coupled between bottom and fourth conductors. A fourth group of parallel-connected bit-shifting transistors is coupled between the second and fourth conductors. Parallel-connected bit-shifting transistors are turned either on or off in response to a plurality of bit-switching bits of a binary number to be converted. One of the bottom, first, second, third, and top conductors is coupled to a DAC output conductor in response to the plurality of bit-switching bits.

Abstract: There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.

Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.

Abstract: In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.

Abstract: Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Abstract: A method and system for detecting the presence of subsurface objects within a medium is provided. In some embodiments, the imaging and detection system operates in a multistatic mode to collect radar return signals generated by an array of transceiver antenna pairs that is positioned across the surface and that travels down the surface. The imaging and detection system pre-processes the return signal to suppress certain undesirable effects. The imaging and detection system then generates synthetic aperture radar images from real aperture radar images generated from the pre-processed return signal. The imaging and detection system then post-processes the synthetic aperture radar images to improve detection of subsurface objects. The imaging and detection system identifies peaks in the energy levels of the post-processed image frame, which indicates the presence of a subsurface object.

Abstract: Systems and methods for improving display quality for at range weather data of smaller antenna size radar weather systems. A processor receives a column of quantized reflectivity data associated with an antenna from a radar system. The processor adjusts the column of quantized reflectivity data based on estimated quantized reflectivity data associated with a beam pattern for an antenna that is larger than the antenna associated with the received column of quantized reflectivity data.

Abstract: Provided is a position information providing system which can reduce a time required for acquiring position information. An indoor transmitter is adapted to provide position information by using a second positioning signal compatible with a first positioning signal which is a spread spectrum signal from each of a plurality of satellites. The indoor transmitter includes an EEPROM which stores therein position data for identifying an installation location thereof, an FPGA operable to generate a second positioning signal including the position data as a spread spectrum signal, and a transmitting section operable to transmit the spread spectrum signal. The second positioning signal is generated to repeat the same content in a cycle shorter than that of the first positioning signal.

Abstract: A pseudo-satellite transmitter includes a GPS unit, a transmission power control unit, and a plurality of antennas. The GPS unit generates a GPS signal of a pseudo-satellite. The transmission power control unit generates a plurality of GPS signals having different power levels based on the GPS signal generated by the GPS unit and a distance from a shadow area to the pseudo-satellite transmitter. Each antenna is configured to wirelessly transmit the GPS signals with different power levels output from the transmission power control unit to a corresponding one of a plurality of shadow areas according to the distance from the shadow area to the corresponding antenna.

Abstract: Methods and apparatuses are provided that may be used by one or more devices within in wireless communication network to request and/or provide code phase related information signals associated with various Satellite Positioning Systems (SPSs).

Abstract: The effects of shock and vibration on a navigation receiver processing satellite signals received from global navigation satellites are reduced by controlling the frequency and the phase of the individual numerically controlled oscillator in each individual satellite channel. The frequency is controlled by an individual frequency control signal based on individual correlation signals generated in an individual satellite channel. The phase is controlled by a common phase control signal or a combination of a common phase control signal and an individual phase control signal. The common phase control signal is based on all the correlation signals generated in all the satellite channels processed by a separate common broadband quartz loop (SCBQL). An individual phase control signal is based on the individual correlation signals generated in an individual satellite channel.

Abstract: A communication device is described comprising an antenna arrangement, an orientation determining device configured to determine the orientation of the antenna arrangement, and a controller configured to control the directivity of the antenna arrangement based on the determined orientation of the antenna arrangement.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: Location inference using selected beacons. Data is received representing a set of beacons observed by a computing device. The beacons are located within a first geographic area. A subset (e.g., a clique) of the beacons is selected based on a coverage area of each of the beacons, where each of the beacons in the selected subset has a coverage area that overlaps with the coverage area of each of the other beacons in the selected subset. Using known or estimated positions of the beacons, a second geographic area is defined based on the selected subset of beacons and the beacon reference data and the coverage areas associated therewith. The second geographic area, smaller than the first geographic area, represents an approximate location of the computing device. In some embodiments, the computing device is calculated to be within the second geographic area with 95% probability.

Abstract: A patch antenna for receiving high frequency wireless signal and a rectenna using the same, more particularly, an impedance-matched patch antenna adopting a slot capacitive coupling structure and a rectenna capable of generating electrical energy from the wireless signals having different frequency band. A rectenna for receiving an A.C. wireless signal carrying electrical energy and converting the wireless signal into a D.C. electrical energy, is comprised of: a patch antenna for receiving the wireless signal comprising an dielectric substrate, a patch that is formed at the upper area of the surface of the dielectric substrate and providing the first frequency response characteristics, a ground plane formed on the other surface of the dielectric substrate, and an impedance matching means providing the second frequency response characteristics; and a rectifying unit that converts the wireless signal, received via the patch antenna, into a D.C. electrical energy by rectifying the wireless signal.

Abstract: An antenna designing method and a data single board of a wireless terminal are disclosed. The method provided by the embodiments of the present invention includes: dividing a semi-closed area without other metal wirings on a data card single board of the wireless terminal; and arranging an antenna wiring and a metal coupling piece in the semi-closed area, where the antenna wiring and the metal coupling piece are parallel and overlap one another, a gap exists between the metal coupling piece and the data card single board, and the metal coupling piece is coupled with the data card single board via the gap. An embodiment of the present invention also provides a data card single board of a wireless terminal. According to the embodiments of the present invention, a Specific Absorption Rate (SAR) value of the antenna is reduced, and a working bandwidth of a broadband is realized.

Abstract: The invention provides a wireless chip which can secure the safety of consumers while being small in size, favorable in communication property, and inexpensive, and the invention also provides an application thereof. Further, the invention provides a wireless chip which can be recycled after being used for managing the manufacture, circulation, and retail. A wireless chip includes a layer including a semiconductor element, and an antenna. The antenna includes a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer, and has a spherical shape, an ovoid shape, an oval spherical shape like a go stone, an oval spherical shape like a rugby ball, or a disc shape, or has a cylindrical shape or a polygonal prism shape in which an outer edge portion thereof has a curved surface.

Abstract: The present example provides a co-location insensitive multi-band antenna. The antenna may be co-located with an antenna operated at another band and tends to reject interference from that antenna. The co-location insensitive multi-band antenna tends to provide a compact design that may be printed on a printed wiring board, on a case of a radio, such as a cellular telephone or may be self supporting. In general, the desired in band performance and out of band signal rejection may be achieved by a meander line coupled to a upper band patch. The meander line tends to provide a good lower band match, and the upper band patch tends to provide a good high band match, or resonance. The upper band patch also tends to cause a sharp roll off in return loss before the high band, that tends to reject frequencies from a co-located antenna transmitting below the high band.

Abstract: An electronic device case having an antenna pattern embedded therein according to an aspect of the invention may include: a radiator having an antenna pattern portion transmitting and receiving a signal and a connection terminal portion allowing the signal to be transmitted to and received from a circuit board of an electronic device; a connection portion partially forming the radiator and connecting the antenna pattern portion and the connection terminal portion to be arranged in different planes; a radiator frame manufactured by injection molding on the radiator so that the antenna pattern portion of the radiator is provided on one side of the radiator frame and the connection terminal portion is provided on the other side thereof; and a case frame covering the one side of the radiator frame on which the antenna pattern portion is provided so that the antenna pattern portion is embedded between the case frame and the radiator frame.

Abstract: A wideband antenna for use portable radio devices, and methods for operating the same. In one embodiment, a monopole antenna is used within a laptop computing device. The antenna comprises a monopole radiator coupled to an auxiliary ground plane element, and is placed substantially outside of the footprint of the computer display ground plane. In one implementation, the auxiliary ground element is configured not to have electrical connections to the ground plane of the laptop. In another implementation, a solid state switch selectively connects an antenna parasitic element to the main ground thus enabling selective control of the antenna lower frequency operating band.

Abstract: A mobile communication terminal including a wireless communication unit configured to communicate with at least one other terminal; a body including a metal frame having a specified length and a width; a power feeding portion formed on an internal circuit board in the terminal and configured to supply RF signals; and an antenna portion disposed inside the terminal. Further, the antenna portion includes a shorting arm overlapping and being separated from the metal frame, and electrically connected to the metal frame at a first location offset from a middle of an edge of the metal frame; and a feeding arm disposed in parallel to the shorting arm, and electrically connected to the power feeding portion at a second location offset from the middle.

Abstract: An antenna duplexer includes a transmission filter and a reception filter both coupled with an antenna terminal. The transmission filter has a lower pass band than the reception filter. The transmission filter includes a first series resonator coupled with a first terminal, a second series resonator connected to the first series resonator at a first node, a first parallel resonator connected to a first port of the first series resonator, a second parallel resonator connected to a first node and the first parallel resonator at a second node, a third parallel resonator connected to the first node, a fourth parallel resonator connected to the third parallel resonator at a third node, a first inductance element coupled with the second node and a ground, and a second inductance element coupled with the third node and the ground. The second inductance element has a lower inductance than the first inductance element.

Abstract: Provided is a loop antenna. The loop antenna includes a first antenna element embodied as a coaxial cable, a second antenna element embodied as a line and connected to one end of the first antenna element in series, a third antenna eLement embodied as a line, having one end connected to a ground plane and the other end connected to the other end of the first antenna element in series, and a power feeding cable for supplying power to the second antenna element.