Abstract: In an organic light-emitting display apparatus and a method of manufacturing the same, a pad region of the organic light-emitting display apparatus comprises a protrusion layer including a plurality of protrusion portions formed on a substrate so as to protrude, a pad lower electrode and a pad upper electrode, the pad lower electrode including a protrusion portion formed along a protrusion outline of the protrusion layer and a flat portion formed along the substrate, and the pad upper electrode being formed on the flat portion of the pad lower electrode. A source/drain electrode layer is formed on the pad upper electrode, an organic layer is formed on the source/drain electrode layer, and a counter electrode layer is formed on the protrusion portion of the pad lower electrode and the organic layer. The counter electrode layer follows the protrusion outline of the protrusion layer on the protrusion portion.

Abstract: Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a first thin insulating layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The first thin insulating layer is formed on the active layer. The second conductive type semiconductor layer is formed on the thin insulating layer.

Abstract: A light emitting device of the present invention has a package constituted by a molded article having a light emitting face, a bottom face that is contiguous with the light emitting face, and a rear face that is on the opposite side from the light emitting face, and a pair of leads that are partially embedded in the molded article, protrude from the bottom face, and have ends that bend toward either the light emitting face or the rear face, and a light emitting element that is disposed on one of the pair of leads, the molded article has a front protruding part that protrudes on the light emitting face side, and a rear protruding part that protrudes on the rear face side, between the leads on the bottom face.

Abstract: A semiconductor light emitting device includes a substrate and a plurality of light emitting cells arranged on the substrate. Each of the light emitting cells includes a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light. An interconnection structure electrically connects the first-conductivity-type and the second-conductivity-type semiconductor layers of one light emitting cell to the first-conductivity-type and the second-conductivity-type semiconductor layers of another light emitting cell. A light conversion part is formed in a light emitting region defined by the light emitting cells and includes a red and/or a green light conversion part respectively having a red and/or a green light conversion material.

Abstract: Embodiments of circuits, methods and systems for a voltage-controlled current source are disclosed. In some embodiments, the voltage-controlled current source may be a three-terminal device having separated gate structures. Other embodiments may also be described and claimed.

Abstract: A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions.

Abstract: A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

Abstract: A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.

Abstract: There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer.

Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.

Abstract: A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

Abstract: The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: A system according to an embodiment of the present invention includes one or more first optical sensors and one or more second optical sensors. The first optical sensor(s) each include a photodetector region and a plurality of first slats over the photodetector region. The second optical sensor(s) each include a photodetector region and a plurality of second slats over the photodetector region, wherein the second slats have a different configuration than the first slats. For example, the second slats can be orthogonal relative to the first slats. For another example, the first slats can slant in a first direction, and the second slats can slant in a second direction generally opposite the first direction. Currents produced by the first optical sensor(s) and the second optical sensor(s), which are indicative of light incident on the optical sensors, are useful for distinguishing between movement in at least two different directions.

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract: Various aspects of the technology provide for a converter circuit such as a dc-dc voltage converter or buck converter. The circuit includes a enhancement mode control Field Effect Transistor (FET) fabricated using gallium arsenide and an depletion mode sync FET fabricated using gallium arsenide. A drain of the sync FET may be coupled to a source of the control FET and an inductor may be coupled to the source of the control FET and the drain of the sync FET.

Abstract: An image sensor includes an active region including a photoelectric conversion region and a floating diffusion region, which are separated from each other, defined by a device isolation region on a semiconductor substrate, and a transfer transistor including a first sub-gate provided on an upper surface of the semiconductor substrate and a second sub-gate extending within a recessed portion of the semiconductor substrate on the active region between the photoelectric conversion region and the floating diffusion region, wherein the photoelectric conversion region includes a plurality of photoelectric conversion elements, which vertically overlap each other within the semiconductor substrate and are spaced apart from the recessed portion.

Abstract: A solid-state imaging device includes a substrate, a dielectric layer on the substrate, and an array of pixels, each of the pixels includes: a pixel electrode, an organic layer, a counter electrode, a sealing layer, a color filter, a readout circuit and a light-collecting unit as defined herein, the photoelectric layer contains an organic p-type semiconductor and an organic n-type semiconductor, the organic layer further includes a charge blocking layer as defined herein, an ionization potential of the charge blocking layer and an electron affinity of the organic n-type semiconductor present in the photoelectric layer have a difference of at least 1 eV, and a surface of the pixel electrodes on a side of the photoelectric layer and a surface of the dielectric layer on a side of the photoelectric layer are substantially coplanar.

Abstract: A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.

Abstract: Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A semiconductor device with mini silicon-oxide-nitride-oxide-silicon (mini-SONOS) cell is disclosed. The semiconductor device includes: a semiconductor substrate; a shallow trench isolation (STI) embedded in the semiconductor substrate; a logic device partially overlapping the STI; and a SONOS cell formed in the overlapped region of the logic device and the STI.

Abstract: An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.

Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

Abstract: A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor.

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract: A manufacturing method provides a semiconductor device having a semiconductor body defining a source region, a body region, a drift region and a diode region. The drift region has a first drift region section and a second drift region section. The diode region is buried within the drift region, and has a semiconductor type opposite to the drift region to form a diode. The diode region is separated from the gate electrode by the first drift region section extending from the diode region in a vertical direction. The gate electrode is adjacent the body region and insulated from the body region by a gate dielectric. A source electrode is electrically connected to the source region, the body region and the diode region. A semiconductor region of a doping type opposite to the doping type of the drift region is arranged between the first drift region section and the source electrode.

Abstract: A transistor includes a substrate including a trench, an insulation layer filled in a portion of the trench, the insulation layer having a greater thickness over an edge portion of a bottom surface of the trench than over a middle portion of the bottom surface of the trench, a gate insulation layer formed over inner sidewalls of the trench, the gate insulation layer having a thickness smaller than the insulation layer, and a gate electrode filled in the trench.

Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

Abstract: Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions.

Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

Abstract: Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include a trench in a substrate. The semiconductor devices may also include a bulk electrode within opposing sidewalls of the trench. The semiconductor devices may further include a liner electrode between the bulk electrode and the opposing sidewalls of the trench. The liner electrode may include a sidewall portion between a sidewall of the bulk electrode and one of the opposing sidewalls of the trench.

Abstract: According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region.

Abstract: A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such that the second gate electrode is located at the drain side of the first gate electrode and the second gate electrode is isolated from the first gate electrode by an insulation film, and wherein the first and second gate electrodes are formed respectively on a first gate insulation film and a second gate insulation film having an increased thickness as compared with the first gate insulation film.

Abstract: A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

Abstract: A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

Abstract: In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus.

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Abstract: A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.

Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.

Abstract: A semiconductor device includes a channel layer formed over a substrate, a gate formed over the channel layer, junction regions formed on both sides of the channel layer to protrude from the substrate, and a buried barrier layer formed between the channel layer and the junction regions.

Abstract: A semiconductor device includes a drift region of a first doping type, a junction between the drift region and a device region, a compensation region of a second doping type, and at least one field electrode structure arranged between the drift region and the compensation region. The at least one field electrode includes a field electrode and a field electrode dielectric adjoining the field electrode. The field electrode dielectric is arranged between the field electrode and the drift region and between the field electrode and the compensation. The field electrode dielectric includes a first opening through which the field electrode is coupled to drift region and a second opening through which the field electrode is coupled to the compensation region.

Abstract: A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

Abstract: A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.

Abstract: An integrated multi-axis mechanical device and integrated circuit system. The integrated system can include a silicon substrate layer, a CMOS device region, four or more mechanical devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, on which any number of CMOS and mechanical devices can be configured. The mechanical devices can include MEMS devices configured for multiple axes or for at least a first direction. The CMOS layer can be deposited on the silicon substrate and can include any number of metal layers and can be provided on any type of design rule. The integrated MEMS devices can include, but not exclusively, any combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices.

Abstract: Disclosed herein is an apparatus comprising a metal shunt and a planar semiconductor material in electrical contact with the metal shunt, the metal shunt located on a surface of the semiconductor material, thereby defining a semiconductor/metal interface for passing a flow of current between the semiconductor material and the metal shunt in response to an application of an electrical bias to the apparatus, wherein a portion of that semiconductor material surface is not covered by the metal shunt, wherein the semiconductor material and the metal shunt lie in different planes that are substantially parallel planes, the semiconductor/metal interface thereby being parallel to the plane of semiconductor material, and wherein, when under the electrical bias, the semiconductor/metal interface is configured to exhibit a change in resistance thereof in response to a perturbation. Such an apparatus can be used as a sensor and deployed as an array of sensors.