Patents Issued in January 28, 2014
  • Patent number: 8638551
    Abstract: The present invention relates to a card reader having communicating function which includes: a top cover; a bottom cover having a first open slot at one side; a printed circuit board; a first memory insertion slot allowing a first removable memory card to be inserted; a processor for controlling the access of first removable memory card; a wireless communication module; a card reader controller; a connector; a charging circuit; a rechargeable battery; and a voltage regulation circuit; such that a portable electronic device is able to access the data in the first removable memory card with a wireless means, or a mainframe is able to access the data in the first removable memory card through the connector.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 28, 2014
    Assignee: Power Quotient International Co., Ltd.
    Inventors: Chia-Hsin Tsai, Jen-Fu Chen
  • Patent number: 8638552
    Abstract: A docking station for a Macintosh laptop computer having a receiving sleeve and a base plate, the receiving sleeve including a spring lever to guide the inserted laptop to interconnect with a series of specifically arranged connecting heads, said connecting heads configurable to a specific Macintosh laptop computer upon a parallelepiped contact plate disposed within the receiving sleeve. The spring lever is a cylindrical member having a first and second finger projected radially therefrom that rotate the cylindrical member when a laptop is inserted into the receiving sleeve, in turn rotating a third finger upward which engages an eject button. A Macintosh laptop computer is thus rapidly and easily interconnected with peripheral devices by placement into the receiving sleeve.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: January 28, 2014
    Inventor: Erick N. Tuero
  • Patent number: 8638553
    Abstract: A data center includes one or more racks, one or more computing devices coupled to at least one of the racks, and one or more air moving devices. The computing devices include heat producing components. The computing devices may be inclined in the rack such that the lower ends of the computing devices are at a lower elevation than the higher ends of the computing devices. The air moving devices can move air from the lower end of the inclined computing devices to the higher end of the inclined computing devices such that heat is removed from heat producing components in the inclined computing devices.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: January 28, 2014
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael P. Czamara, Osvaldo P. Morales, Pete G. Ross
  • Patent number: 8638554
    Abstract: An air duct includes a top plate, two side plates extending from two lateral sides of the top plate, a baffle plate extending from the top plate and located between the side plates, and a torsion spring connected between the top plate and the baffle plate. The top plate and the side plates cooperatively define an air passage in the air duct. The baffle plate includes a first end pivotally connected with the top plate and an opposite second end. The second end of the baffle plate is rotatable relative to the top plate. The torsion spring includes two arms abutting against the top plate and the baffle plate, respectively. When the baffle plate is rotated relative to the top plate under an external force, the torsion spring resists such force.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: January 28, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chao-Ke Wei
  • Patent number: 8638555
    Abstract: An exterior cover for a laptop computer having a display portion and a keyboard portion is disclosed. The exterior cover includes a first rigid planar element for placement on an outside surface of the display portion. The first rigid planar element includes a raised edge along a perimeter of the first rigid planar element, wherein the raised edge extends toward the display portion. The first rigid planar element further includes a plurality of tabs located on the raised edge, wherein each tab extends from the raised edge for gripping the display portion. The exterior cover further includes a second rigid planar element for placement on an outside surface of the keyboard portion. The second rigid planar element includes a raised edge extending toward the keyboard portion. The second rigid planar element further includes a plurality of tabs for gripping the keyboard portion.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: January 28, 2014
    Assignee: Tech Shell, Inc.
    Inventor: Haile Bekele
  • Patent number: 8638556
    Abstract: In some aspects, a portable electronic device is provided having a slidable upper housing movable relative to a lower housing between an open position and a closed position, and a front bezel. The front bezel holds the components of the portable electronic device together and covers up at least some of the fasteners used to attach components of the portable electronic device.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 28, 2014
    Assignee: BlackBerry Limited
    Inventors: Aaron Robert Allen, Paul Brian Koch, Marko Antonio Escalante, Douglas Wayne Moskowitz, Sacha Benjamin Holland
  • Patent number: 8638557
    Abstract: A mobile electronic device holder includes an upper holder frame shell, a bottom holder frame shell attached to the bottom side of the upper holder frame shell, three first clamping members respectively slidably mounted in respective sliding ways of the bottom holder frame shell for holding a mobile electronic device, a gear wheel rotatable to move the first clamping members in and out of the upper and bottom holder frame shells, a retractable second clamping member slidably mounted in one sliding way of the bottom holder frame shell and adjustable to one of a series of length.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: January 28, 2014
    Inventor: Wen-Feng Tsai
  • Patent number: 8638558
    Abstract: In an electronic unit accommodated in a containing device so as to be adjacent to another electronic unit accommodated in the containing device, the electronic unit includes: a housing that is formed into a tub shape, that is provided with a plate comprising an air blowing hole, and that is closed by said another electronic unit when the electronic unit and the other electronic unit are accommodated in the containing device; and an interrupting portion that interrupts power supply to the electronic unit when said another electronic unit is detached from the containing device and the housing of the electronic unit is opened.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 28, 2014
    Assignee: Fujitsu Limited
    Inventors: Hideyo Takada, Shingo Ochiai
  • Patent number: 8638559
    Abstract: A cooling system for a memory module comprises a heat conduction assembly for conducting heat from the memory module to liquid-cooled mounting blocks. In one embodiment, each heat conduction assembly includes a frame having opposing first and second supports, first and second heat spreader plates each extending from the first support to the second support, and a pair of flattened heat pipes each extending along a respective one of the heat spreader plates from the first support to the second support. The liquid-cooled mounting blocks releasably support the heat conduction assembly over a memory module socket with the memory module between the heat spreader plates.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard M. Barina, Vinod Kamath, Chunjian Ni, Derek I. Schmidt, Mark E. Steinke, James S. Womble
  • Patent number: 8638560
    Abstract: A sliding apparatus for a dual slide-type portable communication device, which includes a locking unit selectively formed in sliding members and configured to restrict movement of a first sliding member in a direction substantially perpendicular to a lengthwise direction of a body housing when the first sliding member is slid in a lengthwise direction of the body housing and to restrict movement of the first and second sliding members when the first and second sliding members are slid in a direction substantially perpendicular to a lengthwise direction of the body housing. The body housing and a sliding housing configured to be slid on the body housing in a lengthwise direction of the body housing or in a direction substantially perpendicular to the lengthwise direction of the body housing.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Hun Seo, Jee-Young Jung, Sung-Ho Ahn
  • Patent number: 8638561
    Abstract: An electrical enclosure wherein an electrical component can be moved between various positions (e.g., connected, disconnected, test, etc.) without opening an enclosure door. The electrical enclosure supports a component for movement between a withdrawn position, a test position, and an inserted position. A handle is accessible by an operator from an exterior of the enclosure and is configured to move the component between the respective positions without having to open the enclosure. The handle is integral with the enclosure and thus an operator needs no special tool or other device to effect movement of the electrical component between its respective positions.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 28, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Gregory David Lehtola, Dean Meyer, Arnaldo Hiroyuki Omoto, Paul Krause, Fabio Kazuo Ito, Steven J. Bauer, Jr., Joao Jorge Martins Freitas
  • Patent number: 8638562
    Abstract: The present invention provides a combinative power device. In one aspect, the combinative power device of the present invention includes an AC-to-DC module including a first joint portion; and a DC-to-DC module having a second joint portion and coupled to the AC-to-DC module by the second joint portion with the first joint portion electrically, wherein the DC-to-DC module acts as a removable module which can be removable from the AC-to-DC module to enable the AC-to-DC module to cooperate with different types of the DC-to-DC module.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: January 28, 2014
    Assignee: Phihong Technology Co., Ltd.
    Inventor: Yung Sung Chen
  • Patent number: 8638563
    Abstract: An exemplary electronic device includes a case, an inner body and a pivotable arm pivotally connected on the inner body by a pivot. The case defines an opening at a first lateral side thereof and a latching hole at a second lateral side thereof adjacent to the opening. The inner body is inserted in the case through the opening. The pivotable arm includes a frame engaged in the latching hole of the case, a latching member pivotally connected to the frame by the pivot, and a resilient member. The latching member includes an inner end and an outer end at opposite sides of the pivot. The outer end of the latching member is engaged in the latching hole. The resilient member abuts against the inner end of the latching member such that the inner end of the latching member biases the inner body.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: January 28, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Tang Peng, Hai-Chen Zhou
  • Patent number: 8638564
    Abstract: An apparatus may include a housing forming an enclosure having an edge seatable on a printed circuit board (PCB). The enclosure edge may include an edge portion. The housing may be configured to transfer a force applied to the housing to a surface mount component mounted on the PCB to dismount the surface mount component. The apparatus may include a dye inlet formed by the housing and configured to conduct a dye into the enclosure. Another apparatus may include at least one gasket mounted to the enclosure edge to contact the major surface of the PCB adjacent to the surface mount component for forming a seal with the PCB. A method may include enclosing a surface mount component in an enclosure formed in a nozzle apparatus, introducing a dye into the enclosure, and applying a force to the nozzle apparatus to dismount the surface mount component.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Daniel J Buschel, Wai M Ma, Donald A Merte
  • Patent number: 8638565
    Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Sewald, Markus Kirsch
  • Patent number: 8638566
    Abstract: A method of forming an assembly for tool-less backplane retention and insertion thereof into a housing including a housing mating device through which an installation path for an assembly is defined with a space in which a first part is positioned is provided. The method includes coupling a hub and a backplane body having opposing faces on which a second part and a backplane mating device are respectively disposed. The coupling includes inserting a backplane mating device protruding from one of the opposing faces of the backplane body through a hub mating device defined in the hub. The method further includes forcing a first stage of a two-stage mating device, which includes first and second elastically coupled stages and which extends from the hub, to elastically hook onto the backplane body during a near-completion of the insertion.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeremy S. Bridges, Norman B. Desrosiers, Michael D. French, Dean F. Herring, Daniel P. Kelaher, John P. Scavuzzo, Paul A. Wormsbecher
  • Patent number: 8638567
    Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sungjun Chun, Anand Haridass, Roger D. Weekly
  • Patent number: 8638568
    Abstract: A mounted circuit card is disclosed that has a housing with a circuit card assembly (“CCA”) attached to the housing with adhesive along at least an edge portion of the CCA, where the assembly includes at least one jagged edge portion of the CCA in contact with the adhesive, or at least one channeled portion of the housing in contact with the adhesive, or a combination of both a jagged edge portion of the CCA and channeled portion of the housing in contact with the adhesive.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 28, 2014
    Assignee: Steering Solutions IP Holding Corporation
    Inventors: Wayne Thomas, Ryan Yaklin, Timothy J. Wandrey, Jason M. Easlick, Jeremy Breault, Peter C. Younglao
  • Patent number: 8638569
    Abstract: A first connector has a plurality of terminals arranged in the direction along a first pattern, and the first pattern is connected to a terminal disposed far from an image sensor in the plurality of terminals of the first connector. A second connector has a plurality of terminals arranged in the direction along a second pattern, and the second pattern is connected to a terminal disposed closer to an image processing circuit in the plurality of terminals of the second connector.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: January 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigeaki Sotsu
  • Patent number: 8638570
    Abstract: An electromagnetic interference (EMI) shield apparatus includes a shell, a hub, a shield member, a partition plate, a resilient member, and a cover. The hub is rotatably mounted within the shell. The shield member is wrapped around the hub. The partition plate is fastened to and rotatable together with the hub. The cover covered on an open end of the shell. The resilient member is connected between the partition plate and the cover to drive the hub to rotate to reel the shield member. The shield member is made of EMI shield material.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 28, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Lei Liu
  • Patent number: 8638571
    Abstract: This invention relates to circuits and methods for controlling a resonant power converter. Control of the power converter may comprise comparing an output voltage or current of the converter to at least one reference voltage or current; enabling primary side switching signals based on a first selected result of the comparison; and disabling primary side switching signals based on a second selected result of the comparison; wherein a primary side switching signal for each primary side switch includes at least one off-on-off transition.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: January 28, 2014
    Assignee: SPARQ Systems Inc.
    Inventors: Darryl J. Tschirhart, Praveen K. Jain
  • Patent number: 8638572
    Abstract: A power converter controller includes a drive circuit coupled to control switching of a power switch coupled to an energy transfer element and an input of the power converter. An output voltage sensor including first and second pulse sampler circuits is coupled to capture first and second peak voltages, respectively, that are representative of a second peak of a ringing voltage of a feedback signal representative of an output of the power converter. The first pulse sampler circuit is coupled to capture the first peak voltage at a first time in the feedback signal. The second pulse sampler circuit is coupled to capture the second peak voltage at a second time in the feedback signal. The drive circuit is coupled to receive a change signal from the output voltage sensor in response to the first and second peak voltages.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: January 28, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Alex B. Djenguerian, Arthur B. Odell, Henson Wu
  • Patent number: 8638574
    Abstract: A semiconductor control device can include a current detection signal input terminal, a feedback signal input terminal, a driving signal output terminal and a voltage adjusting circuit that delivers a voltage similar to a voltage of a primary winding of the flyback transformer to the current detection signal input terminal. The device can also include an oscillator circuit connected to the feedback signal input terminal; a one-shot circuit connected to the oscillator circuit, an RS flip-flop circuit that generates a driving signal to be delivered to the driving signal output terminal. A bottom detection section can receive a one-shot signal from the one-shot circuit, the current detection signal, and an output signal from the RS flip-flop circuit, and detect a bottom of the current detection signal to set the RS flip-flop circuit based on the detected bottom detection signal.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: January 28, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Takato Sugawara
  • Patent number: 8638575
    Abstract: In one embodiment, a startup circuit for a power supply is provided. The startup circuit comprises a resistance coupled between a voltage source and a first node. A first capacitor, coupled to the first node, is operable to be charged by current flowing through the resistance. A first transistor has an emitter, a base, and collector, wherein the collector is coupled to the voltage source and the base is coupled to the first node. A diac circuit, coupled to the emitter of the first transistor, is operable to fire to turn on the first transistor, thereby allowing discharge of the first capacitor through the base-emitter junction of the first transistor. A second capacitor is operable to be charged by current related to a discharge voltage resulting from the firing of the diac circuit. The second capacitor operable to store charge to provide VCC voltage to a controller of the power supply.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: January 28, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Richard A. Dunipace
  • Patent number: 8638576
    Abstract: A voltage source converter having a plurality of cell modules connected in series, each cell module including a converter unit having an ac-side and a dc-side, and the voltage source converter includes a control unit adapted to control the converter units, where at least one of the cell modules includes a second redundant converter unit having an ac-side which is connected in parallel with the ac-side of the first converter unit and the control unit is configured to substantially synchronously control the first and the second converter units.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: January 28, 2014
    Assignee: ABB Technology AG
    Inventors: Falah Hosini, Mauro Monge
  • Patent number: 8638577
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
  • Patent number: 8638578
    Abstract: A power converter including a charge pump employable in a power adapter. In one embodiment, the charge pump includes a voltage divider with a first diode having a terminal coupled to a terminal of a first capacitor and a second diode having a terminal coupled to a terminal of a second capacitor and another terminal coupled to another terminal of the first capacitor. The charge pump also includes a third diode coupled across the second diode and the second capacitor, and a charge pump power switch coupled across the first capacitor and the second diode.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: January 28, 2014
    Assignee: Power System Technologies, Ltd.
    Inventor: Xiaoyang Zhang
  • Patent number: 8638579
    Abstract: The invention relates to a control method applicable to structures for converting direct current/alternating current, dc/ac, especially for photovoltaic systems. The control method according to the invention enables the switching losses of the semiconductors to be reduced, thereby improving the efficiency of the conversion structure. The invention can also be applied to other fields of energy, such as the generation of energy by means of electrochemical cells or wind energy.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: January 28, 2014
    Assignee: Ingeteam Power Technology, S.A.
    Inventors: Javier Coloma Calahorra, Roberto González Senosian, Francisco Javier Ancín Jiménez, Luis Marroyo Palomo
  • Patent number: 8638580
    Abstract: Switching device controllers, drive circuits, power converters and related methods are disclosed. One example controller for a switching device includes a drive circuit for controlling the switching device and an auxiliary circuit coupled to the drive circuit. The auxiliary circuit includes an input for receiving a waveform having alternating first and second intervals. The auxiliary circuit is configured to energize the drive circuit during the first intervals and de-energize the drive circuit during the second intervals. One example method of energizing and de-energizing a drive circuit for a switching device includes receiving a waveform having alternating first and second intervals, energizing the drive circuit during the first intervals, and de-energizing the drive circuit during the second intervals.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 28, 2014
    Assignee: Astec International Limited
    Inventor: Robert H. Kippley
  • Patent number: 8638581
    Abstract: In an inverter includes two input lines for connection to a DC voltage source, two half-bridges connecting the two input lines, and two output lines for connection to an alternating current load or an AC power grid. Each half-bridge includes two pulse-operated switches with reverse connected diodes, each output line is connected to a center point of one of the half-bridges via an inductance, and the two output lines are connected to the same one of the input lines via a further pulse-operated switch behind the inductance with respect to the associated half-bridge.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: January 28, 2014
    Assignee: SMA Solar Technology AG
    Inventors: Peter Zacharias, Regine Mallwitz, Samuel Vasconcelos Araújo, Benjamin Sahan
  • Patent number: 8638582
    Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Dimitri Argyres
  • Patent number: 8638583
    Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Watanabe, Isamu Hayashi, Teruhiko Amano, Fukashi Morishita, Kenji Yoshinaga, Mihoko Akiyama, Shinya Miyazaki, Masakazu Ishibashi, Katsumi Dosaka
  • Patent number: 8638584
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: January 28, 2014
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Sri Rama Namala, Chang Hua Siau, David Eggleston
  • Patent number: 8638585
    Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaesoo Lee, Kangho Roh, Wonhee Cho, Hojun Shim, Youngjoon Choi, Jaehoon Heo, Je-Hyuck Song, Seung-Duk Cho, Seontaek Kim, Moonwook Oh, Jong Tae Park, Wonmoon Cheon, Chanik Park, Yang-sup Lee
  • Patent number: 8638586
    Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 28, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Tianhong Yan, Luca Fasoli
  • Patent number: 8638587
    Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: John K. De Brosse, William J. Gallagher, Yu Lu
  • Patent number: 8638589
    Abstract: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: January 28, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Hau-Yan Lu, Hsin-Ming Chen, Ching-Sung Yang
  • Patent number: 8638590
    Abstract: A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wuyang Hao, Jungwon Suh, Kangho Lee, Tae Hyun Kim, Jung Pill Kim, Seung H. Kang
  • Patent number: 8638591
    Abstract: A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: January 28, 2014
    Assignee: The Penn State Research Foundation
    Inventors: Vinay Saripalli, Dheeraj Mohata, Saurabh Mookherjea, Suman Datta, Vijaykrishnan Narayanan
  • Patent number: 8638592
    Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sayeed A. Badrudduza, Jack M. Higman, Sanjay R. Parihar
  • Patent number: 8638593
    Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: January 28, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takumi Takagi, Daisuke Sasaki, Masahiko Nishiyama, Masatoshi Hasegawa
  • Patent number: 8638594
    Abstract: Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: January 28, 2014
    Assignee: Altera Corporation
    Inventors: Shankar Sinha, Shih-Lin S. Lee, Peter J. McElheny
  • Patent number: 8638595
    Abstract: A global to local bit line interface circuit for domino static random access memory (SRAM) devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventor: Antonio R. Pelella
  • Patent number: 8638596
    Abstract: Systems and methods for saving repair cell address information in a non-volatile magnetoresistive random access memory (MRAM) having an array of MRAM cells are disclosed. A memory access circuit is coupled to the MRAM, and is configured to store failed cell address information in the MRAM.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: January 28, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jung Pill Kim, Taehyun Kim, Hari M. Rao
  • Patent number: 8638597
    Abstract: A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: January 28, 2014
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Kang Yong Kim, Young Pil Kim
  • Patent number: 8638598
    Abstract: An example embodiment is a method for determining a binary value of a memory cell represented by an electrical resistance level of the memory cell. The method includes iteratively charging shunt capacitors having different capacitances until a selected shunt capacitor causes the voltage to decay through the memory cell to a reference voltage within a predetermined time range. A binary value of the most significant bits of the memory cell is determined based on the selected shunt capacitor. The selected shunt capacitor is then charged to a second voltage and the binary value of the least significant bits of the memory cell is determined based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8638599
    Abstract: A semiconductor storage device has tunnel magnetoresistive elements in memory cells. The array includes a memory array having a plurality of memory cells; a plurality of read-word-lines and a plurality of write-word-lines; a plurality of read-bit-lines; a plurality of first write-bit-lines and a plurality of second write-bit-lines; a first driver; a read circuit; a second driver; and a write circuit. The memory cell has a mos transistor, of which one current electrode is coupled to the read-bit-line. A tunnel magnetoresistive element is coupled between a control electrode of the mos transistor and the read-word-line. A capacitive element is coupled to the tunnel magnetoresistive element and forms an RC circuit together with the tunnel magnetoresistive element.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Mihoko Akiyama
  • Patent number: 8638600
    Abstract: A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: January 28, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan
  • Patent number: 8638601
    Abstract: Magnetic wires that include cobalt, nickel, and platinum layers show improved domain wall motion properties, when the domain walls are driven by pulses of electrical current. These wires exhibit perpendicular magnetic anisotropy, thereby supporting the propagation of narrow domain walls. The direction of motion of the domain walls can be influenced by the order in which the platinum and cobalt layers are arranged.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stuart Stephen Papworth Parkin, Luc Thomas, See-Hun Yang
  • Patent number: 8638602
    Abstract: A storage subsystem implements a background process for selecting voltage reference values to use for reading data from a non-volatile memory array, such as an array of multi-level cell (MLC) flash memory. The process involves performing background read operations using specific sets of voltage reference values while monitoring the resulting bit error counts. The selected voltage reference values for specific pages or other blocks of the array are stored in a table. Read operations requested by a host system are executed using the corresponding voltage reference values specified by the table.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert L. Horn