Abstract: A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store no more than N?1 bits of data. The method further includes providing a block in the second region of the memory cell array. Each cell of the block in the second region is configured to store N bits of data. The method additionally includes configuring the data storage system so that when data is programmed to the memory cell array, N pages of the data are initially stored in N respective blocks of the first region of the memory cell array, and then the N pages of the data are stored in the block of the second region.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described technique includes monitoring read-back data from a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a single charge level, the two or more bits corresponding to two or more bit positions; determining estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data; and adjusting one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract: A programming technique which reduces program disturb in a non-volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

Abstract: Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.

Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.

Abstract: The invention provides a semiconductor storage device which can restrain the uneven high voltage applied to the storage unit and can provide the high voltage with high precision. The semiconductor storage device includes a storage unit array, a Y decoder circuit, a X decoder circuit, a sense amplifier circuit, a Y gate circuit, a high voltage generating circuit, a high voltage regulator circuit, and a voltage adjusting circuit. The voltage modifying data for adjusting the potential of the anode of the zener diode so as to adjust the high voltage applied to the storage unit array is written into the storage unit array. The voltage modifying data is used to adjust voltage by the voltage adjusting circuit.

Abstract: Integrated circuit memory devices include a plurality of vertically-stacked strings of nonvolatile memory cells having respective vertically-arranged channel regions therein electrically coupled to an underlying substrate. A control circuit is provided, which is configured to drive the vertical channel regions with an erase voltage that is ramped from a first voltage level to a higher second voltage level during an erase time interval. This ramping of the erase voltage promotes time efficient erasure of vertically stacked nonvolatile memory cells with reduced susceptibility to inadvertent programming of ground and string selection transistors (GST, SST).

Abstract: Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

Abstract: This disclosure describes techniques for using environmental variables to improve calibration of flash memory by adapting to changing threshold-voltage distributions. These techniques effectively increase the speed and/or accuracy at which flash memory can be written or read.

Abstract: Disclosed herein is a method of remarkably improving the memory characteristics of a non-volatile memory device and the device reliability of the MOSFET using graphene which is a novel material that has a high work function and does not cause the deterioration of a lower insulating film.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.

Abstract: A nonvolatile storage device includes: a plurality of memory mats each including a plurality of memory cells; a plurality of plate electrodes each provided for every individual one of the memory mats and each used for applying a voltage to the memory cells; a power-supply section configured to apply a voltage to each of the plate electrodes; a switch circuit having a plurality of switches provided between the power-supply section and each of the plate electrodes and between the plate electrodes; and a control section configured to control the switch circuit in order to disconnect the plate electrodes from the power-supply section and to connect the plate electrodes to each other in order to carry out electrical charging and discharging operations among the plate electrodes.

Abstract: A switching circuit comprises a control and bias stage configured for receiving a first input voltage signal, a second input voltage signal and a selection signal and for generating therefrom a first bulk bias signal substantially equal to the first input voltage signal or to the second input voltage signal depending on the selection signal. The switching circuit further comprises a switching stage connected to the control and bias stage, including a transistor having a bulk terminal, and configured for receiving the bulk bias signal and generating an output signal having the first input voltage signal when the selection signal indicates the selection of the first input voltage signal or having the second input voltage signal when the selection signal indicates the selection of the second input voltage signal. The bulk bias signal is electrically coupled to the bulk terminal of the transistor.

Abstract: An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages.

Abstract: A memory chip includes a plurality of storage elements. A method of controlling the memory chip includes receiving a plurality of target values from a memory controller. Each target value of the plurality of target values received from the memory controller corresponds to a respective one of the plurality of storage elements. The method further includes, for each storage element of the plurality of storage elements, adjusting a measurable parameter of the storage element until the measurable parameter of the storage element reaches the target value corresponding to the storage element received from the memory controller.

Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.

Abstract: A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

Abstract: A differential data strobe receiver is provided which is configured to receive a differential data strobe signal at a first strobe input and a second strobe input, wherein transitions of the differential data strobe signal indicate sample points for an associated data signal. The differential data receiver is configured to identify the transitions of the differential strobe signal by differentially comparing values of the differential strobe signal received at the first strobe input and the second strobe input. The differential data strobe receiver comprises strobe gating circuitry configured to generate a strobe gating signal, wherein the associated data signal can only be sampled in dependence on the differential data strobe signal when the strobe gating signal is asserted and strobe input termination circuitry configured selectively to provide a first termination connection for the first strobe input and a second termination connection for the second strobe input.

Abstract: According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines. The plurality of sense amplifiers is configured to detect a signal level of the corresponding bit lines. The timing generation circuit includes a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes. The timing generation circuit is configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing.

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract: Disclosed herein is a device that responds to mat selection information, which is used to select one of memory mats, and selects at least one defective address from a plurality of defective addresses which are stored, for example, in a fuse circuit. When the access address information is coincident with a selected defective address, a redundant memory cell is accessed for reading or writing data in place of a normal memory cell. In a refresh operation, on the other hand, a column addressing, including the above replacement of a normal memory cell with a redundant memory cell, is deactivated.

Abstract: A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.

Abstract: Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.

Abstract: A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time.

Abstract: A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.

Abstract: A semiconductor device has an antifuse element and a measurement unit. The antifuse element stores information according to whether the antifuse element is in the broken or unbroken state. The measurement unit determines a resistance value related to the resistance value of the broken antifuse element.

Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.

Abstract: A memory module is provided. The memory module includes die packages and a charge pump that is external the die packages. Each die package includes a flash memory device, and each of the flash memory devices includes bit lines and memory cells coupled to the bit lines. The charge pump provides a charge pump voltage that is selectively provided to the bit lines in each flash memory device in each of the die packages.

Abstract: A device includes a backup power supply configured to provide power to an external system upon loss of primary system power, the backup power provided by at least one capacitor; logic to create, while the capacitor is available as the backup power supply to the external system, a transient elevation of the capacitor's stored potential above a upper predetermined operating potential of the capacitor; logic to obtain measurements of the capacitor's output voltage during the transient elevation of the capacitor's stored potential; and logic to determine a capacitance of the capacitor from the measurements; the device comprising multiple capacitors in series; logic to discharge each capacitor in series individually from the others; and logic to monitor for overcharging of any of the capacitors in series, and, during charging of the capacitors in series, to operate the discharge logic for any capacitor in the series that is in danger of overcharging.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: To determine properties of a subterranean structure, information relating to dipole compressional data is collected based on measurements by a logging tool in a borehole. The information relating to the dipole compressional data is analyzed in multiple dimensions (e.g., multiple borehole axial planes) to determine the properties of the subterranean structure through which the borehole extends.

Abstract: Methods and transducers for producing acoustical signals having a spiral wavefront with omnidirectional magnitude and a phase that varies with angle and transducers for producing broadband omnidirectional reference signals for underwater navigation and communication.

Abstract: The trajectory of at least one marine animal emitting sound signals in the form of series of clicks, such as a cetacean, is passively determined. During successive processing time windows, raw analog signals are acquired from a plurality of hydrophones disposed in a marine environment and converted into digital data. Digital data filtering eliminates spurious noises and keeps the data, for each pair of hydrophones and each processing window, that corresponds to potential values (TDOAs) for the time-difference of arrival of the sound signals at two different hydrophones. For each hydrophone pair, the consistency of the TDOAs is checked and a number of filtered and mutually-consistent TDOAs are selected. Based on the filtered and mutually-consistent TDOAs, the successive instantaneous positions of the click sources are determined by means of nonlinear regression, and the trajectory of at least one marine animal in the environment is deduced in real time.

Abstract: A method of identifying and tracking a target is described, in which seismic data relating to a target is passively detected and processed using statistical means. The statistical manipulation of the data includes frequency information extraction, dynamical mixture model construction based on existing known data and identification of an unknown target by the convergence of this model to a state characteristic of that target.

Abstract: The globe-shaped clock for a city square includes a base for placement on a select public location in a town or city. The base includes a plurality of pointer rods radiating in both major and minor geographic directions. A spherical cage is mounted to the base, and the cage surrounds a rotating globe therein. The cage is topped by a clock spire having a frustoconical base and a plurality of major and minor pointer rods radiating towards both major and minor geographic directions. A plurality of illuminated, curved, longitude lines defines the spherical cage. The longitude lines illuminate sequentially in varying intensity depending on the time of day. An electronic control unit is provided to define the pattern of illumination. A plurality of display units surrounds the base in line with each longitude line and displays different time zones.

Abstract: The acoustic radiating membrane (1) is for assembly in a music box or a striking watch. The membrane includes a first sheet (2) having a certain number of cells (5), which is secured to a first face of a second sheet (3) which has no cells. The membrane may also include a third sheet (4) having a certain number of cells (6) which is fixed to a second face of the second sheet (3). The shape and dimension of the cells are adapted according to the type of material and the note or notes to be radiated by the membrane with uniform amplification within the audible frequency band. The cells (5, 6) of the first and third sheets are configured in a honeycomb arrangement to occupy most of the surface of the membrane, for the uniform amplification and efficient radiation of the note or notes produced.

Abstract: A write element for a thermally assisted magnetic head slider includes an air bearing surface facing to a magnetic recording medium; a first magnetic pole, a second magnetic pole, and coils sandwiched between the first and the second magnetic poles; a waveguide for guiding light generated by a light source module mounted on a substrate; and a plasmon unit provided around the first magnetic pole and the waveguide, which has a near-field light generating surface for propagating near-field light to the air bearing surface. The near-field light generating surface of the plasmon unit is apart from the air bearing surface with a first predetermined distance to form a first recess, and the first recess is filled in with a protective layer. The thermally assisted magnetic head slider can prevent the plasmon unit from protruding over the air bearing surface, thereby improving the performance of thermally assisted magnetic head.

Abstract: An optical information processing method and apparatus performs a light irradiating and receiving step, a signal processing step, and an adjusting step of a spherical aberration and a focus offset on the basis of shift amount of first and second control devices and a performance evaluation value. The performance evaluation values for first, second, third and fourth points in an x and y coordinate system are detected, in which an x-coordinate is one of the shift amount of the first control device and the shift amount of the second control device and a y-coordinate is the other, the first point, second and third points having the same y-coordinate and different x-coordinates with each other, the fourth point being provided on a first straight line passing through the first point and being different from the first point.

Abstract: Audio is adaptively associated with speakers, depending on the speaker configuration that is present. Each speaker it receives an audio assignment based on its individual spectral characteristics. As more speakers are added, content is adaptively associated with that you speaker, and taken away from the previous.

Abstract: An information erasing device includes a recording section where recording is performed with regard to a disk-shaped recording medium, and a control section which controls the recording section so that the recording section overwrites a part of a erasing target sector so as not to overlap in a radius direction of the disk-shaped recording medium.

Abstract: A control mechanism may control the height and/or position of a read/write head configured to interact with a rotating information storage surface. A topography detection mechanism may detect topography of a side read/write track while the read/write head is interacting with a current read/write track. A memory may store the detected topography. The control mechanism may adjust the height of the read/write head based on the stored topography. The topography detection mechanism may compute the detected topography from gap measurements using a dynamic filter including a model of read/write head dynamics. The control mechanism may be a reactionless control mechanism configured to apply a counterforce to offset movements of the read/write head and/or a slider.

Abstract: A machine readable information storage medium, a reproducing method and apparatus which reproduces data from the storage medium, and a recording method and apparatus for recording data on the storage medium. The information storage medium includes a control area which stores within a data structure information usable by the recording or reproducing apparatus to record or reproduce the data on or from the storage medium. The information stored within the data structure includes a version corresponding to a specification, a revision number of recording speed, and an extended part version field.

Abstract: Communications connectors are provided that include a plurality of input ports, a plurality of output ports and a plurality of conductive paths. Each of the conductive paths connects a respective one of the input ports to a respective one of the output ports. The conductive paths are arranged as a plurality of differential pairs of conductive paths that are each configured to carry a differential signal. These connectors further include a control signal input circuit that is configured to capacitively couple a phantom mode control signal onto at least a first and a second of the differential pairs of conductive paths.

Abstract: A station is disclosed that is configured for signal transmission in an Orthogonal Frequency Division Multiple Access (OFDMA) system. The station includes a processor configured to fix a subcarrier spacing to a predetermined value for one or more subframes in all available bandwidths. The station further includes a transmitter configured to transmit a signal having the fixed subcarrier spacing, regardless of a frame structure of the one or more subframes. According to certain embodiments, the predetermined value may be divided evenly by at least one channel raster. The predetermined value may be 12.5 KHz, according to certain embodiments. Alternatively, the predetermined value is 6.25 KHz for one or more low mobility mobile stations, and/or the predetermined value is 25 KHz for one or more high mobility mobile stations. The station may be a mobile station or a base station configured for uplink and downlink transmission.