Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.

Abstract: A nonvolatile memory element includes: a first electrode; a second electrode; and a variable resistance layer comprising a metal oxide positioned between the first electrode and the second electrode. The variable resistance layer includes: a first oxide layer having a resistivity ?x, on the first electrode; a second oxide layer having a resistivity ?y (?x<?y), on the first oxide layer; a third oxide layer having a resistivity ?z (?y<?z), on the second oxide layer; and a localized region that is positioned in the third oxide layer and the second oxide layer to be in contact with the second electrode and not to be in contact with the first oxide layer, and is, in resistivity, lower than the third oxide layer and different from the second oxide layer.

Abstract: A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to change a resistance value of a metal oxide layer from a resistance value corresponding to an initial state of the metal oxide layer to another resistance value; wherein when the resistance value corresponding to the initial state is R0, the resistance value corresponding to a write state is RL, the resistance value corresponding to an erase state is RH, another resistance value is R2, a maximum value of the current flowing when the initial voltage pulse is applied is IbRL, a maximum value of the current flowing when the write voltage pulse is applied is IRL, and a maximum value of the current flowing when the erase voltage pulse is applied is IRH, R0>RH>R2?RL, and |IRL|>|IbRL| are satisfied.

Abstract: The nonvolatile storage device includes a variable resistance element and a write circuit which writes data into the variable resistance element, wherein the variable resistance element has a property of changing from a first resistance state to a second resistance state when a pulse of a first voltage is applied to the variable resistance element, and changing from the second resistance state to the first resistance state when a pulse of a second voltage is applied to the variable resistance element, and the write circuit applies, to the variable resistance element, at least the pulse of the first voltage, a pulse of a third voltage, and the pulse of the first voltage in this order, when the variable resistance element is caused to change from the first resistance state to the second resistance state.

Abstract: Semiconductor memory devices are described. The semiconductor memory device includes a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to an internal node, an internal voltage generator configured to generate an internal voltage signal applied to the internal node in response to a power-up signal, and an initialization element configured to initialize the internal node in response to the power-up signal.

Abstract: A method comprises writing data to one or more static random access memory (SRAM) cells. Writing data to the one or more SRAM cells comprises applying a first data signal to at least one bit line electrically connected to the one or more SRAM memory cells, electrically disconnecting at least one of a first power supply terminal and a second power supply terminal of each of the one or more SRAM cells from a power supply and applying a word line signal to a word line electrically connected to the one or more SRAM cells. Thereafter, the at least one of the first power supply terminal and the second power supply terminal of each of the one or more SRAM cells is electrically connected to the power source.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell provided with a pair of storage nodes which store data in a complementary manner, a pair of bit lines that are driven in a complementary manner based on data written to the memory cell, a word line that selects a row of the memory cell, and a word line potential fixing circuit that fixes a potential of the word line so that the row of the memory cell is not selected when a power supply of the memory cell rises.

Abstract: A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.

Abstract: Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.

Abstract: A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.

Abstract: A semiconductor memory device including an array of memory cells (MC) formed on a substrate each realized from a load element and thyristor that define a switchable current path whose state represents a volatile bit value stored by the MC. At least one word line corresponding to a respective row of the array is formed on the substrate and coupled to MC current paths for the corresponding row. Bit lines corresponding to respective columns of the array are formed on the substrate and can be coupled to a modulation doped QW interface of the MC thyristors for the corresponding column. Circuitry is configured to apply an electrical signal to the word line(s) in order to generate current that programs phase change material of the MC load elements into one of a high or low resistive state according to state of the current path of the MCs for non-volatile backup purposes.

Abstract: An apparatus is described that is configured to modify a signal to at least substantially remove a noise portion from the signal. In one or more implementations, the apparatus is a collaborative filtering module that is configured to communicatively couple to a memory array having a plurality of memory cell blocks. The memory array is configured to furnish a signal representative of data stored within the plurality of memory cell blocks. The collaborative filtering module is configured to determine a noise distribution associated with the plurality of memory cell blocks and generate a noise prediction, which is based upon the noise distribution, when a read operation for the plurality of memory cell blocks is issued. The collaborative filtering module is also configured to modify the signal utilizing the noise prediction to at least substantially remove noise from the signal.

Abstract: A data reading method for a rewritable non-volatile memory module, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes applying a bias for reading data to a target word line electrically connected to a target memory cell and applying a bias for selecting bit lines to a target bit line electrically connected to the target memory cell. The method also includes applying a first bias to at least one word line adjacent to the target word line and applying a second bias to other word lines, and the first bias is lower than the second bias. The method further includes outputting a corresponding value according to a conduction state of a channel of the target memory cell. Accordingly, the method can effectively increase the gate controllability of the memory cell to prevent read errors.

Abstract: This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

Abstract: A method of executing wear leveling in a flash memory device includes determining whether a current temperature is in a normal operating temperature range of the flash memory device, and reprogramming data associated with data blocks to another location in a flash memory array when the current temperature is in the normal operating temperature range of the flash memory device, wherein the data is programmed in a temperature out of the normal operating temperature range of the flash memory device.

Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Abstract: A memory includes memory cells and a sense amplifier including a sense node that transmits a voltage according to a current flowing in one of the memory cells and detects logic of data based on the voltage of the sense node. A write sequence of writing data in a selected cell is performed by repeating write loops each including a write stage of writing data in the selected cell and a verify read stage of verifying that the data has been written in the selected cell by performing discharge from the sense node through the selected cell. The sense amplifier changes, according to a logic of data detected at the verify read stage in a first write loop, a period of discharge from the sense node to the selected cell at the verify read stage in a second write loop following the first write loop.

Abstract: Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.

Abstract: Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions of a termination circuit coupled to an output pin are selectively activated to change an impedance of the termination circuit to change the centerline voltage of the data signal driven to the output pin. One such apparatus includes pull-up impedances and pull-down impedances that can be activated to change the centerline voltage of the data signal. Additional embodiments are also described.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type, a second well region of the first conductivity type, a memory string, a bit line, a source line and a first transistor. The bit line is connected to one end of the memory string and the source line is connected to the other end of the memory string. The first transistor is arranged on the second well region, has first and second terminals and includes a gate insulating film with first film thickness. The first terminal of the first transistor is connected to the source line and the second terminal thereof is connected to the second well region.

Abstract: A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

Abstract: A memory array assembly and a method for performing a write operation without disturbing data stored in other SRAM cells are provided. The memory array assembly comprises a plurality of SRAM cells, a plurality of avoid-disturb cells, a plurality of sense amplifiers and a plurality of write drivers. The SRAM cells are arranged in rows and columns, wherein each column is coupled to an avoid-disturb cell, a sense amplifier, and a write driver. The avoid-disturb cell receives a select signal capable of assuming first or second states. An output of the sense amplifier is coupled to an input of the write driver when the select signal is in the first state. A data-in bus is coupled to the input of the write driver if the select signal is in the second state. The write driver then sends the output signal to the SRAM cell.

Abstract: A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.

Abstract: A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode.

Abstract: Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate.

Abstract: A semiconductor memory device includes, in part, a first data I/O block and a second data I/O block. During a write operation, the first data I/O block transmits input data supplied through a first pad to a first global I/O line, and further generates a write internal signal. The second data I/O block transmits the write internal signal to a second pad in response to a monitor enable signal. During a read operation, the first data I/O block supplies data from the first global I/O line to a first pad, and further generates a read internal signal. The second data I/O block transmits the read internal signal to the second pad in response to a monitor enable signal.

Abstract: A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.

Abstract: A semiconductor memory device includes a memory bank having a first cell block including a plurality of memory cells coupled to a first word line which can be activated in response to a row address signal, a second cell block including a plurality of memory cells coupled to a second word line, and a dummy cell block including a plurality of memory cells coupled to a third word line which can be activated in response to the row address signal. The first and second cell blocks share a first sense amplifier. The second cell block and the dummy cell block share a second sense amplifier. The first cell block is disposed adjacent to a first edge of the memory bank, and the dummy cell block is disposed adjacent to a second edge of the memory bank opposing the first edge.

Abstract: A bit line sense amplifier and a layout method therefor which can reduce coupling capacitance. The bit line sense amplifier is disposed between a first memory cell block and a second memory cell block adjacent to the first memory cell block and configured to include first and third switching elements substantially symmetrically formed in a first direction so that the drain terminals of the first and third switching elements face each other, second and fourth switching elements substantially symmetrically formed in the first direction so that the drain terminals of the second and fourth switching elements face each other, a first line configured to electrically couple the gate terminal of the first switching element and the drain terminal of the second switching element, and a second line configured to electrically couple the gate terminal of the third switching element and the drain terminal of the fourth switching element.

Abstract: A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Abstract: What is described is a twin screw extruder having two extruder screws (10, 34), each extruder screw (10) having a cylindrical core (12) and at least one web (14) running helically over the periphery of the outer cylinder face of the core (12), the surface of the web (14) comprising a peripheral side (18) and two flanks (22, 24), and a channel (30) being formed between adjacent web windings. The flanks (22, 24) of the web (14) have a waved progression in the peripheral direction.

Abstract: A universal dental impression material system uses a programmable device having containers for separately housing two or more components that form a dental impression material when mixed. A mixing chamber and a dispensing means respectively receive/mix the components and dispense the dental impression material. One or more viscosity modification zones are configured to apply viscosity manipulation to a component prior to mixing, to the components in the mixing chamber during mixing, and/or to the dental impression material in the dispensing means after mixing. A user interface accepts user input of desired properties, such as viscosity, color, work/set time and/or extrusion rate. A controller operatively coupled to the user interface is configured to control dispensing of the components to the mixing chamber, activation as needed of the viscosity modification zones, and dispensing from the dispensing means in response to the user input to achieve the desired properties.

Abstract: The present invention relates to a cosmetic raw material capsule for separating and accommodating cosmetic raw materials, including: an accommodating portion (110) for accommodating at least two cosmetic raw materials; a protective film (120) arranged on the accommodating portion (110) so as to cover and seal the accommodating portion (110); and a separation film (130) arranged on the accommodating portion (110) so as to separate at least two cosmetic raw materials. Thus, cosmetic raw materials required for producing cosmetics can be contained in a single container so as to enable the simple production of cosmetics.

Abstract: An electric bench mixer has a base, a column and a pivoting head. The tilt angle of the head and the configuration of the blades are optimalised to provide a wiping action of the blades against the interior of the ball as the head is pivoted. An ice cream making bowl and blade are also disclosed.

Abstract: The present invention is a method and an apparatus that can image objects immersed in optically opaque fluids using ultrasound in a confined space and in a harsh environment. If the fluid is not highly attenuating at frequencies above 1 MHz, where commercial ultrasound scanners are available, such scanners can be adapted for imaging in these fluids. In the case of highly attenuating fluids, such as drilling mud, then a low frequency collimated sound source is used.

Abstract: Streamer and method for deploying the streamer for seismic data acquisition related to a subsurface of a body of water. The method includes a step of releasing into the body of water, from a vessel, a body having a predetermined length together with plural detectors provided along the body; a step of towing the body and the plural detectors such that the plural detectors are submerged; and a step of configuring plural birds provided along the body, to float at a predetermined depth from a surface of the water such that a first portion of the body has a curved profile while being towed underwater.

Abstract: A method includes generating an ultrasound image based on the harmonic components in the received echoes using multi-stage beamforming and data generated therefrom. An ultrasound imaging system (100, 200) includes a transducer array (108) including a plurality of transducer elements configured to emit ultrasound signals and receive echoes generated in response to the emitted ultrasound signals. The ultrasound imaging system further includes transmit circuitry (110) that generates a set of pulses that actuate a set of the plurality of transducer elements to emit ultrasound signals. The ultrasound imaging system further includes receive circuitry (112), including a first beamformer (122) configured to process the received echoes, generating intermediate scan lines. Memory (126) stores the generated intermediate scan lines.

Abstract: A method is provided for deghosting marine seismic data. Marine seismic data is provided. The marine seismic data has a total acoustic wavefield that includes an upgoing acoustic wavefield and a downgoing acoustic wavefield. A deghosting operation to determine a part of the total acoustic wavefield corresponding to one of the upgoing acoustic wavefield and the downgoing acoustic wavefield is performed. The deghosting operation accounts for a varying vertical distance between a detector of a streamer and a sea surface. One of the upgoing and downgoing acoustic wavefields in the total acoustic wavefield is identified based on a result of the deghosting operation. The downgoing acoustic wavefield is removed from the total acoustic wavefield.

Abstract: The sources of microseismic hydraulic fracture events (“hydro-fracs”) are located for image mapping by the calculation of Green's functions G(x, z, t|x?, z?, 0) which is estimated using, e.g., RVSP, VSP, SWD and/or surface data, with the Green's functions used as migration kernels with greater accuracy than the prior art techniques, e.g. the diffraction limit, because all of the natural arrivals in the data are utilized.

Abstract: A sonar system and method of operating a sonar system are disclosed. In one embodiment, the sonar system comprises an array of transducers and a multiplexer configurable into a plurality of states. In one embodiment, the multiplexer, when in a first state, electrically couples a plurality of connections with the plurality of transducers via a first mapping and, in a second state, electrically couples the plurality of connections with the plurality of transducers via a second mapping.

Abstract: A method for detecting a spatial position of an indicator object by using sound waves. The method is adapted to be used with a sound wave transceiver device and a plurality of sound wave receiving devices. The method includes steps of: obtaining a relative position of the sound wave transceiver device to each one of the sound wave receiving devices; obtaining a plurality of reflection times respectively indicating time periods from the sound wave transceiver device emitting the sound wave to the sound wave transceiver device and the sound wave receiving devices receiving the reflected sound wave from the indicator object; and calculating a position of the indicator object according to the relative positions and the reflection times. A system for detecting a spatial position of an indicator object by using sound waves is also provided.

Abstract: A computer-readable recording medium storing an estimation program for causing a computer to execute a process, the process includes: executing sound image localization processing for each of pieces of sound data output by a plurality of sound sources; and specifying, on the basis of a change in orientation of a listener caused in accordance with the sound image localization processing, at least one of the plurality of sound sources related to the listener.

Abstract: A multilayer backing absorber for use with an ultrasonic transducer comprises a plurality of absorber elements, each absorber element having at least one metal layer and at least one adhesive layer, wherein the backing absorber is adapted to be coupled to a vibrating layer of the ultrasonic transducer.

Abstract: A wake up alarm providing device (10) is provided, comprising a sound producing unit (11) and a control unit (12), coupled to the sound producing unit (11). The sound producing unit (11) is arranged to provide an audible wake up signal during an alert period. The control unit (12) controls the wake up signal to comprise a diffuse sound during a first part of the alert period and to comprise a localized sound during a subsequent part of the alert period.

Abstract: There is provided a head-gimbal-assembly for use in heat-assist magnetic recording, excellent in the heat-release characteristic of a laser diode, by inhibiting effects of deterioration in lateral balance, and wind turbulence without adversely affecting efforts to lower a profile of a magnetic disk unit. For this purpose, a sub-mount with a laser diode attached thereto is mounted on either of the right and left lateral faces of a head slider. Further, of two lengths of lead wires for power supply to the laser diode, one length of the lead wire is routed to a lateral face of the head-slider, on the opposite side of a lateral face with the sub-mount attached thereto, after circling around the outer periphery of a head-slider electrode, formed on the gas-outlet side of the head slider.

Abstract: An apparatus including a near field transducer positioned adjacent to an air bearing surface, the near field transducer comprising silver (Ag) and at least one other element or compound; a first magnetic pole; and a heat sink positioned between the first magnetic pole and the near field transducer, wherein the heat sink includes: rhodium (Rh) or an alloy thereof; ruthenium (Ru) or an alloy thereof; titanium (Ti) or an alloy thereof; tantalum (Ta) or an alloy thereof; tungsten (W) or an alloy thereof; borides; nitrides; transition metal oxides; or palladium (Pd) or an alloy thereof.

Abstract: An apparatus including a near field transducer positioned adjacent to an air bearing surface, the near field transducer including an electrically conductive nitride; a first magnetic pole; and a heat sink, a diffusion barrier layer, or both positioned between the first magnetic pole and the near field transducer, wherein the heat sink, the diffusion barrier or both include rhodium (Rh) or an alloy thereof; ruthenium (Ru) or an alloy thereof titanium (Ti) or an alloy thereof tantalum (Ta) or an alloy thereof tungsten (W) or an alloy thereof borides; nitrides; transition metal oxides; or palladium (Pd) or an alloy thereof.

Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.

Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.

Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.