Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space. A second air gap is on a sidewall of the second metal line and in the space. A dielectric material is disposed in the space and between the first and the second air gaps. A third air gap is underlying the lower portion of the dielectric material, wherein the first air gap, the second air gap, and the third air gap are interconnected to form a continuous air gap.

Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers on the upper and lower surfaces of the insulation layer; and an extraction electrode formed so as to make contact with a section of the electrode layers that form electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section including short circuit sections that are short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by engulfing the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. Furthermore, the extraction electrode has at least two or more sections in contact with the electrode layer.

Abstract: The invention provides advances in the arts with useful and novel integrated packaging having inductor elements and adjacent magnetic material enhancing the inductance characteristics of the packaged inductor. Preferably the integrated packages also contain one or more ICs operable coupled to the inductor(s).

Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.

Abstract: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood of damage to the substrate, such as cracking thereof, is substantially mitigated.

Abstract: An integrated circuit apparatus is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires.

Abstract: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.

Abstract: A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip. Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure.

Abstract: A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.

Abstract: A reconstituted wafer level package for a versatile high-voltage capable component is disclosed. The reconstituted wafer package includes a dice substantially encapsulated by a mold material except for a first face. A dielectric layer is disposed on the first face of the dice. The package further includes an array of ball bumps formed on an exterior facing portion of the dielectric layer. Further, a field plate is disposed within the dielectric material and interposed between the first face of the dice and the ball bump array. The field plate may be spaced from the dice by a predetermined distance to prevent dielectric breakdown of the material of the dielectric layer.

Abstract: A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

Abstract: A semiconductor package includes a printed circuit board, a chip, a protection frame, and a covering layer. The chip is mounted on the printed circuit board and is electrically connected to the printed circuit board through a number of first bonding wires. The protection frame includes a sidewall surrounding the chip and the bonding wires and defines a number of through holes passing through an inner surface and an outer surface of the sidewall. The protection frame is filled with adhesive. The adhesive adheres to the inner surface and covers the chip and the boding wires. The covering layer is coated on the outer surface and covers the through holes.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.

Abstract: In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Abstract: Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.

Abstract: One embodiment provides a semiconductor device having: a core substrate having first and second surfaces and an accommodation hole penetrating therethrough; a semiconductor element accommodated in the accommodation hole so that a front surface thereof is on the first surface side; a first metal film formed on a back surface of the semiconductor element; a second metal film formed on the second surface of the core substrate; an insulating layer covering the first and second metal films; and a third metal film formed on the insulating layer, via parts thereof penetrating through the insulating layer to respectively reach the first and second metal films.

Abstract: A semiconductor device includes a substrate, an insulating substrate mounted on the substrate, a metal pattern formed on the insulating substrate, an electronic part mounted on the metal pattern across a bond, and a wire member, separate from a wiring wire, which contains a material repellent to the bond and is formed on the metal pattern and around the electronic part.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

Abstract: An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract: A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity ?1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity ?2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30??2??1?300 (Pa·s) and 3?T2?T1?7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1?S2.

Abstract: To protect victim bondwires in a packaged electronic component from crosstalk induced by noisy aggressor bondwires, shielding bondwires are configured between the victim bondwires and the aggressor bondwires. The shielding bondwires, on either side of the victim bondwires, are connected to the same reference voltage on the package side of the component and to each other on the die side of the component, e.g., via a metal connection mounted on the die. As configured in one embodiment, the shielding bondwires and metal connection form a two-dimensional Faraday cage that shields the victim bondwires from crosstalk induced by the aggressor bondwires.

Abstract: A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the first semiconductor chip, and a first sealing material which seals a gap between the first semiconductor chip and the first adhesive agent layer, wherein each height of the plurality of the first spacers is greater than height of the wire relative to an upper face of the first semiconductor chip.

Abstract: A semiconductor device has a semiconductor chip and a first interconnection tape. The semiconductor chip has a plurality of first electrode pads arranged on a first surface. The first interconnection tape is in contact with each of the plurality of first electrode pads such that the plurality of first electrode pads are electrically connected with each other.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: A method for manufacturing a microelectronic assembly including stacked first and second microelectronic components having a cavity therebetween including defining said cavity by means of a lateral wall forming a closed frame extending around a determined area of the first component except for an opening used as a vent; forming within the closed frame and opposite to the vent an obstacle capable of forming, in cooperation with the lateral wall, a bypass duct for the filling material; performing a flip-chip hybridization of the first and second components, a surface of the second component resting on the upper edge or end of the lateral wall formed on the first component to form said at least one cavity; injecting the filling material in liquid form between the two hybridized components to embed said at least one cavity and to make it tight by obstruction of the vent as said filling material solidifies.

Abstract: Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer.

Abstract: A semiconductor package includes a first semiconductor chip mounted to a substrate, a first encapsulant covering the first semiconductor chip and have first to fourth sidewall surfaces, and a chip stack mounted to the substrate and disposed on the first encapsulant. The chip stack includes a plurality of second semiconductor chips. A second encapsulant covers the chip stack. The second encapsulant may cover the first sidewall surface of the first encapsulant and expose the third sidewall surface of the first encapsulant.

Abstract: A system for generating energy from waste includes a generator device and an ejector device integrated in a pipe line unit. The generator device includes nozzle venture inlets. The ejector device is coupled with the generator device and includes a slit venture outlet to restore any velocity pressure loss in the pipe line unit and eliminate any back pressure buildup in the generator device.

Abstract: A system for generating electricity for powering an electric or hybrid motor vehicle uses a fan which is driven by the air flow created by the motion of the vehicle. In the event that the fan is unable to generate sufficient electricity, a controller operates an auxiliary gas powered motor for the generation of electricity for powering the electric or hybrid motor vehicle.

Abstract: A system for improving engine starting is disclosed. In one example, an engine starting is improved by providing a predictable load to the engine during engine starting. The predictable load may be provided by controlling alternator field voltage during the engine start.

Abstract: A subsurface power generating system in one embodiment includes a frame, an electric generator supported by the frame and operably connected to a first vertical rotor, another electric generator supported by the frame and operably connected to a second vertical rotor, a first louver operably connected to the first vertical rotor and including a front side, and a back side, and pivotable between a first position whereat the back side is in contact with a first pivot limiting structure, and a second position whereat the back side is not in contact with the first pivot limiting structure, and a second louver operably connected to the second vertical rotor and including a front side, and a back side, and pivotable between a third position whereat the back side is in contact with a second pivot limiting structure, and a fourth position whereat the back side is not in contact with the second pivot limiting structure.

Abstract: A power recovery system using the Rankine power cycle incorporating a two-phase liquid-vapor expander with an electric generator which further consists of a heat sink, a heat source, a working fluid to transport heat and pressure energy, a feed pump and a two-phase liquid-vapor expander for the working fluid mounted together with an electric generator on one rotating shaft, a first heat exchanger to transport heat from the working fluid to the heat sink, a second heat exchanger to transport heat from the heat source to the working fluid.

Abstract: Device and methods associated with underwater pumped-hydro energy storage are disclosed. An underwater pumped-hydro energy storage device includes a submersible tank that includes an inlet and an outlet. A pump is disposed at the outlet of the submersible tank to evacuate water from the submersible tank in a surrounding body of water. A valve is disposed at the inlet of the at least one submersible tank to control a flow of the water into the submersible tank from the surrounding body of water. Moreover, a turbine power unit is to generate output electrical power from the flow water into the submersible tank.

Abstract: A speed setting system that generates a speed control command for controlling the rotational speed of a stall-controlled wind turbine of a wind-powered machine. The speed setting system generates the speed command as a function of performance variation of the wind turbine due to environmental and/or other factors. The speed setting system utilizes a performance-compensation term that is slowly adjusted to compensate for relatively long-term performance variation. In one example, the performance-compensation term is adjusted only when the current power output of the wind turbine is at least 80% of the rated output power to ensure the wind speed is sufficiently high.

Abstract: A method and system for dissipating energy in a direct current (dc) bus of a doubly-fed induction generator (DFIG) converter during a grid event is described. In one aspect, the method comprises monitoring operating conditions of an electrical system, the electrical system comprising at least a DFIG generator and a line side converter and a rotor side converter connected by a dc bus having a dynamic brake connected thereto; detecting an overvoltage on the dc bus or a condition indicative of an overvoltage on the dc link is detected, the overvoltage on the dc bus or condition indicative of the overvoltage caused by a grid event; and causing energy in the dc link to be dissipated using the dynamic brake.

Abstract: The invention relates to a wave-power unit with a floating body (1) connected by flexible connection means (3) to a translator (6) reciprocating in a linear generator (2), The floating body (1) is arranged for floating on the sea and the stator (8) of the generator for anchoring on the sea bed, According to the invention the connection means is guided by a guiding device (9) through lower and upper openings, The part of the connection means (3) that momentary is within the guiding device (9) is thereby guided to be aligned with the translator movements adjacent the lower opening and to be allowed to be inclined adjacent the upper opening. The invention also relates to a use of the invented wave-power plant and to a method for producing electric energy.

Abstract: A power generation apparatus for generating power from water flows is described. The power generation apparatus includes: a generator; a first blade set operatively mounted to the generator for rotation in a selected direction in response to flowing water from a selected direction; a second blade set operatively mounted to the generator for rotation and operatively connected to the first blade set, the second blade set being disposed coaxially with, and downstream of or in a wake zone of, the first blade set; wherein the generator is adapted to be driven by at least one of the blade sets, the generator being disposed generally coaxially between the first and second blade sets.

Abstract: A horizontal-axis wind turbine of a rotor-support design is provided in which the structural load of the wind turbine rotor is carried by the wind turbine tower itself. The turbine uses a composite shaft to transfer torque from the wind turbine rotor to the generator, the shaft having high torsional strength but being flexible in bending. This prevents the transmission of bending moments from the rotor hub to the generator system. Accordingly, the components of the turbine can be rigidly mounted to the turbine main frame, removing the need for vibration damping elements. The result is a wind turbine of reduced weight, which can be modeled and designed for improved efficiency and performance. Furthermore, as the turbine components do not have to be load-balanced, the turbine can be of a modular construction for relatively easy servicing and/or upgrading.

Abstract: A drive shaft for a wind turbine is shaped so as to allow for increased bending of the shaft, while being suitable for transferring torque in a wind turbine system. An example of such a shaping is a drive shaft having a helical rib defined on the surface of the shaft. A wind turbine incorporating such a shaft, and a method of manufacture of such a shaft are also described.

Abstract: The disclosed embodiments provide a system that generates electricity. During operation, the system uses a set of rotating blades to convert rotational energy from a wind turbine into heat in a low-heat-capacity fluid. Next, the system selectively transfers the heat from the low-heat-capacity fluid to a working fluid. Finally, the system uses the transferred heat in the working fluid to generate electricity.