Abstract: An angle measuring system includes a first component group and a second component group, the first component group being mounted in a manner allowing rotation about an axis relative to the second component group. The first component group includes a ring having a running surface and an angle scaling. The second component group has a further ring having a further running surface, as well as a sensor for scanning the angle scaling. Rolling elements are arranged between the running surfaces, the angle scaling being applied such that a geometric pattern of the angle scaling in a first region differs from a geometric pattern of the angle scaling in a second region as a function of radial runouts of the running surfaces and/or of the rolling elements.

Abstract: A magnetic angle sensor comprises a semiconductor chip, at least two magnetic field concentrators of planar shape which are arranged on a surface of the semiconductor chip, and four Hall sensors. Each Hall sensor is assigned to one of the magnetic field concentrators and comprises a Hall element or a cluster of Hall elements. The Hall elements are integrated in the semiconductor chip and are arranged in the region of the edge of the assigned magnetic field concentrator where they are permeated by field lines of the magnetic field which extend approximately perpendicularly to the mentioned surface of the semiconductor chip in the region of the edge of the magnetic field concentrator. Two Hall sensors form a first pair of sensors for measuring a first component of the magnetic field and the two other Hall sensors form a second pair of sensors for measuring a second component of the magnetic field.

Abstract: In one embodiment, a sensor package includes a lead frame with a first portion extending and a second portion extending in a direction inclined with respect to the first potion. The sensor package also includes an application specific integrated circuit and a magneto resistive sensor and a ferrite provided with a molding body.

Abstract: An actuator and sensor assembly comprising respective sensor and actuator housings defining an interior chamber. Clips on the sensor housing engage the actuator housing for coupling the sensor and actuator housings together. The sensor housing includes a wall defining a pocket. A connector with a sensor couples to the sensor housing in a relationship wherein the sensor extends into the sensor housing pocket. A movable piston is located in the interior chamber and a tube thereon defines a receptacle for a magnet located adjacent the pocket. The piston is seated on a flexible diaphragm. An actuator shaft includes one end coupled to the piston and an opposite end coupled to a movable object. A plurality of pins in the actuator housing mount the assembly to a support bracket. The sensor senses changes in the magnetic field in response to changes in the position of the magnet relative to the sensor.

Abstract: A system for measuring a variation in a distance of an axis of rotation of an object relative to a point in a plane perpendicular to this axis comprises at least two sensors for measuring a value representing an angular position of said object about said axis, at least a first of said sensors, whose position is fixed relative to said point, comprising a magnetometer suitable for measuring the magnetic field generated by said object whose magnetization varies around its circumference; and means for determining said variation of distance on the basis of a variation in an angular deviation between said sensors relative to the axis, from one revolution of said object to the next.

Abstract: A resolver includes: a resolver rotor attached to a rotational shaft; an annular resolver stator that is provided on a radially outer side of the resolver rotor and that has a plurality of teeth each opposed, across a clearance, to an outer peripheral face of the resolver rotor and circumferentially arranged at given intervals; and a case member having a cylindrical fit portion to which an outer peripheral face of the resolver stator is fitted. At least three protrusions, each protruding radially outward, are formed at given circumferential intervals on the outer peripheral face of the resolver stator, so that the outer peripheral face of the resolver stator is press-fitted to an inner peripheral face of the fit portion at positions at which the protrusions are formed.

Abstract: A method for measuring longitudinal bias magnetic field in a tunnel magnetoresistive sensor of a magnetic head, the method includes the steps of: applying an external longitudinal time-changing magnetic field onto the tunnel magnetoresistive sensor; determining a shield saturation value of the tunnel magnetoresistive sensor under the application of the external longitudinal time-changing magnetic field; applying an external transverse time-changing magnetic field and an external longitudinal DC magnetic field onto the tunnel magnetoresistive sensor; determining a plurality of different output amplitudes under the application of the external transverse time-changing magnetic field and the application of different field strength values of the external longitudinal DC magnetic field; plotting a graph according to the different output amplitudes and the different field strength values; and determining the strength of the longitudinal bias magnetic field according to the graph and the shield saturation value.

Abstract: A tuning fork gyroscope that is insensitive to magnetic field gradients is provided. The tuning fork gyroscope includes a first electrically conducting proof mass and a second electrically conducting proof mass connected through electrically conducting suspensions to anchors attached to one or more insulating substrates, and an electrical-resistance mid-point electrically connected to opposing ends of the first electrically conducting proof mass and to opposing ends of the second electrically conducting proof mass. The tuning fork gyroscope provides an input to a sense charge amplifier. The sense charge amplifier generates an output signal indicative of a rotation of the tuning fork gyroscope. The output signal is independent of a magnetic field gradient.

Abstract: A diffusion imaging method is provided. The diffusion imaging method includes performing a plurality of data collection sequences. Each data collection sequence includes applying an excitation radio frequency signal and a selection gradient. The excitation radio frequency signal includes a first set of frequency bands selected to simultaneously excite a first nuclei type in a plurality of cross sections of a subject. Each data collection sequence further includes applying a diffusion gradient during formation of a magnetic resonance signal, applying a spatial encoding gradient during formation of the magnetic resonance signal, and while acquiring the magnetic resonance signal, applying a separation gradient to change a frequency separation between portions of the magnetic resonance signal. The diffusion imaging method further includes computationally determining a diffusion image of each of the plurality of cross sections.

Abstract: When the settings of the region of interest are received from the operator, the measurement data acquisition control unit performs control so that an image for generating profile data is taken, and the data processing unit generates profile data in the encoding directions of the set region of interest. Then, the field-of-view setting unit sets the field of view in each of the encoding directions, based on the relationship between the dimensions of the subject P in the encoding directions that are calculated from the profile data of the encoding directions and the dimensions of the region of interest in the corresponding encoding directions, by use of coefficients stored in the coefficient storage unit.

Abstract: A method of magnetic resonance imaging of an object comprises the steps of arranging the object in a stationary magnetic field, subjecting the object to an excitation and encoding sequence of magnetic field gradients resulting in k-space sampling in two segments along the phase encoding direction, wherein the encoding sequence of the magnetic field gradients is selected such that the two segments in k-space are sampled along trajectories beginning with a central k-space line through the k-space center and continuing to opposite k-space borders of the two segments, collecting magnetic resonance signals created in the object, and reconstructing an image of the object based on the magnetic resonance signals, wherein one central k-space line is sampled in both of the two k-space segments, and intersegment phase and/or intensity deviations are corrected in both k-space segments using the magnetic resonance signals collected along the central k-space line.

Abstract: The present invention provides an apparatus and a corresponding method useful for electron paramagnetic resonance imaging, in situ and in vivo, using high-isolation transmit/receive (TX/RX) coils, which, in some embodiments, provide microenvironmental images that are representative of particular internal structures in the human body and spatially resolved images of tissue/cell protein signals responding to conditions (such as hypoxia) that show the temporal sequence of certain biological processes, and, in some embodiments, that distinguish malignant tissue from healthy tissue. In some embodiments, the TX/RX coils are in a surface, volume or surface-volume configuration.

Abstract: An antenna arrangement for magnetic resonance applications includes antenna elements substantially parallel to a common central axis, distributed around the central axis at a distance from the central axis, and enclosing an essentially cylindrical volume. The antenna arrangement includes intermediate connections that connect to immediately adjacent antenna elements at connection points that lie between the ends of the antenna elements. A preamplifier connects to each of the intermediate connections and has an output that, in a receive mode, corresponds to a respective feed-out point. In send mode, the antenna arrangement injects radio-frequency signals into the antenna elements using the injection points. The antenna arrangement is also configured to adjust the intermediate connections to a higher resistance when the antenna arrangement is in the send mode and at least some of the intermediate connections to a lower resistance when the antenna arrangement is in the receive mode.

Abstract: The present embodiments relate to a method and gradient cable connection for a magnetic resonance tomography system. The gradient cable connection connects cable shoes of two gradient cables to one another. A first fastening device is provided with two nuts. Using the first fastening device, the cable shoes are pressed against one another by the two nuts, the two nuts being disposed on a bolt on opposing sides of the cable shoes. A second fastening device is also provided. Using the second fastening device, the bolt is pressed against a support plate by the bolt and one of the two nuts.

Abstract: An antenna (3) of an electromagnetic probe used in investigation of geological formations GF surrounding a borehole WBH comprises a conductive base (31) and an antenna element (32). The conductive base (31) comprises an opened non-resonant cavity (33). The antenna element (32) is embedded in the cavity (33) and goes right through the cavity. The antenna element (32) is isolated from the conductive base (31). The antenna element (32) is coupled to at least one electronic module via a first 34A and a second 34B port, respectively. The electronic module operates the antenna so as to define a simultaneously superposed pure magnetic dipole and pure electric dipole.

Abstract: There is provided a method for measuring abnormality detection parameters of a disconnect switch, comprising: releasably connecting a first sensor to the disconnect switch, the first sensor adapted to measure a first parameter related to a position of an arm of the disconnect switch, the disconnect switch comprising a rotating actuation element operatively connected to the arm for moving the arm between a closed position and an open position; releasably connecting a second sensor to the rotating actuation element, the second sensor adapted to measure a second parameter related to a torque of the rotating actuation element; moving the arm using the actuation element; measuring and storing in memory the first and second parameters while the arm is moving; and disconnecting the first and second sensors.

Abstract: When a battery current is not larger than a limit current set depending on the battery temperature and is flowing continuously for a predetermined time set depending on the battery temperature or longer, a decision is made that a secondary battery is in stable state. When the secondary battery is in stabilized state, the battery voltage is considered to be equal to the open circuit voltage and SOC estimation is performed based on the open circuit voltage-SOC characteristics. When the product of the internal resistance of the secondary battery and the limit current is made substantially constant (constant voltage) by setting the limit current in association with temperature dependence of the internal resistance, estimation error can be kept within a predetermined range in the stabilized state even if SOC estimation is performed while the battery voltage is assumed as the open circuit voltage.

Abstract: An arc flash validation unit may generate stimulus to be received by an arc flash detection unit (AFDU) and observe the response of the AFDU thereto. The response of the AFDU to the stimulus may allow for validation of the AFDU (e.g., validation that the AFDU is operating as expected). In addition, the arc flash validation unit may determine the response time of the AFDU. Different types of stimulus may be provided to the AFDU, including electro-optical (EO) stimulus (e.g., visible light), current stimulus, and the like. Results of the validation may be displayed on a human-machine interface, which may display an estimate of the total energy that would be released in an actual arc flash event. The estimate may be used to define appropriate safety parameters for the equipment monitored by the AFDU.

Abstract: The N1(s) turns of a first output winding is divided by a split ratio ? into N1a(s) turns of a lower-layer first output winding and N1b(s) of an upper-layer first output winding. The lower-layer first output winding is continuously wound around all slots as the undermost layer. A second output winding is continuously wound around all slots over the lower-layer first output winding. An upper-layer first output winding is continuously wound around all slots over the second output winding. The split ratio ? is adjusted only in the slots where the detection accuracy decreases. This equalize the contribution of the first output windings and the second output winding to the flux linkage, thereby achieving high angle detection accuracy.

Abstract: A test device for measuring permeability of a barrier material. An exemplary device comprises a test card having a thin-film conductor-pattern formed thereon and an edge seal which seals the test card to the barrier material. Another exemplary embodiment is an electrical calcium test device comprising: a test card an impermeable spacer, an edge seal which seals the test card to the spacer and an edge seal which seals the spacer to the barrier material.

Abstract: A system for inspecting bonding resistance of a display device includes a display panel, at least one circuit board, at least one driving chip and a testing board. The display panel includes at least one testing conductive line and connecting conductive lines. The circuit board is connected with the testing conductive line and the connecting conductive lines. The driving chip includes at least one testing pad and connecting pads, respectively electrically connected to the testing conductive line and the connecting conductive lines; at least one comparator connected to the testing pad; and at least one logic circuit connected to the comparator. The testing board is connected to the circuit board and provides a test signal to the testing pad through the circuit board and the testing conductive line. The test signal is compared with a reference signal in the comparator, and the logic circuit determines a comparing result.

Abstract: Device (2) for measuring electric parameters of a fluid (F), comprising: two measurement circuits (8, 10) for measuring, respectively, the dielectric permittivity and the electrical conductivity of the fluid (F); two electrodes (5, 5?) facing each other from opposite sides of the fluid (F); a selector system (11) for alternatively connecting the two measurement circuits (8, 10) to the electrodes (5, 5?). Each electrode (5, 5?) comprises two sectors (5a, 5b) suited to establish mutually separate electrical contact with the fluid (F) and the electrical conductivity measurement circuit (10) comprises two measurement sections (V, A) of different impedance, each one of which being connectable to a corresponding sector (5a, 5b) of each electrode (5, 5?).

Abstract: A method of evaluation a degree of degradation of a lubricating oil, comprising: using a device for evaluating a degree of degradation of a lubricating oil, the device comprising a pH-ISFET which is free from a reference electrode; and measuring a current flowing between a drain and a source of the pH-ISFET with a first circuit wherein a constant voltage is applied between the drain and the source, or measuring a voltage between a drain and a source with a second circuit wherein a constant current is caused to flow between the drain and the source.

Abstract: There is established an easier inspection method with which it is not required to set up probes on wires. Also, there is provided an inspection apparatus using this inspection method. With the inspection apparatus or inspection method, primary coils of an inspection substrate and secondary coils of a device substrate are superimposed on each other so that a certain space is maintained therebetween. An AC signal is inputted into the primary coils, thereby generating an electromotive force in each secondary coil by electromagnetic induction. Then, each circuit provided on the device substrate is driven using the electromotive force and information possessed by an electromagnetic wave or electric field generated in this circuit is monitored, thereby detecting each defective spot.

Abstract: An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

Abstract: Various embodiments are directed at an apparatus for implementing electrical connectivity for testing of a semiconductor device. The apparatus comprises a probe head which comprises an upper guide plate and a lower guide plate, wherein the upper guide plate defines a plurality of first apertures, and the lower guide plate defines a plurality of second apertures in some embodiments. The apparatus further comprises a plurality of probes, wherein each of the plurality of probes passes through one of the plurality of first apertures on the upper guide plate and one of the plurality of second apertures on the lower guide plate, and at least one of the plurality of probes defines a buckled form after the at least one of the plurality of probes is finally assembled in the apparatus. The apparatus further comprises a template member to guide the plurality of probes.

Abstract: A method for accelerated life testing of organic devices is provided. The lifetime of each of one or more individual organic emissive devices is measured at a non-heating current density. Based upon the measured lifetimes of the one or more devices, the device lifetime is determined for a selected luminance. An organic emissive panel is also obtained having a second organic stack that consists essentially of the one or more organic layers of the first organic stack. The junction temperature of the organic emissive panel is then determined at a heating current density. Based upon the junction temperature and the device lifetime of the one or more individual organic emissive devices, the expected lifetime of the organic emissive panel is then determined at the heating current density.

Abstract: A method of testing a semiconductor device including applying a reference test pattern to the semiconductor device in which a preset number of power pins of the semiconductor device are supplied with current, incrementally disconnecting the power pins from the current to set a number of removal power pins, and determining a final number of power pins which represents a minimum number of power pins with which the semiconductor device operates normally. The method additionally includes applying a delay test pattern to the semiconductor device to set a cycle of the delay test pattern corresponding to the number of removal power pins to reduce or prevent an overkill phenomenon.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract: Systems and methods for flexibly configuring one or more intellectual property (IP) blocks of a programmable logic device are described. The methods include configuring and operating a first portion of the programmable logic device before configuring a remaining portion of the programmable logic device. By operating the first portion before configuring the remaining portions, various timing constraints including power-up timing constraints can be met by the programmable logic device.

Abstract: The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.

Abstract: A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.

Abstract: A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.

Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.

Abstract: A frequency synthesizer for generating a low noise and low jitter timebase of a reference signal generates first and second output signals a difference frequency that is low enough for use in sub-scanning is implemented with a first incrementer, having a preset increment and a preset end value E1 controlling a first fractional divider and a second incrementer having a preset increment and a present end value E2 controlling a second fractional divider, wherein each of the incrementers is clocked from the output signal of each fractional divider so that, when the end value E1, E2 is reached, an end signal is output and the incrementers are reset to a carryover value as a new starting value and the end signal is switched between the division factors of the fractional dividers so that the switching sequence of the end signal is periodic with the output signals of the fractional dividers.

Abstract: It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.

Abstract: A buck-boost power converter includes a power stage to convert an input voltage to an output voltage, an error amplifier to generate an error signal according to a reference voltage and a feedback signal proportional to the output voltage, a ramp generator to provide two ramp signals, and two comparators to generate two control signals according to the error signal and the two ramp signals to drive the power stage. By using feed-forward technique, one of the two ramp signals has a peak varying with the input voltage and the other ramp signal has a valley varying with the input voltage, so that the power converter has fast line response.

Abstract: A clock data recovery circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

Abstract: A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract: Systems, methods and circuitry useful for adjusting a periodic signal such as with a voltage controlled oscillator or a delay line. In one series of embodiments, circuits and methods are provided for controlling current flow through first and second parallel paths where an impedance device in one path emulates the impedance characteristics of a different device in the other path. A phase or frequency characteristic of the periodic signal may be adjusted by alternate switching of current through the two paths.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A phase locked loop including a flying-adder divider circuit configured to receive phases of a periodic signal from a frequency generator and output a feedback signal to a phase detector, and a method of generating a periodic signal using such a flying-adder circuit, are disclosed. The flying-adder divider circuit generally includes a flying-adder and one or two divide-by-N dividers. The flying-adder receives K phases of the periodic signal, where K is an integer of at least 2, and generates a divided periodic signal from the K phases. The phase locked loop may include flying-adder divider circuits inside and/or outside the loop.

Abstract: The ratio of the output frequency of the PLL to the reference frequency is governed by the ratio of the feedback divider to the output divider. For the case of a fixed-point delta-sigma modulator based PLL, the feedback divide factor can only be a non-recurring/terminating rational number in base-2 (binary) system and the output divide ratio is constrained to be an integer. Hence, the range or resolution of the output frequencies that are possible is inherently limited. To solve this problem, an additional gain factor is introduced in the feedback loop. The gain factor is determined by finding an initial gain factor for which the value of the feedback divide ratio can be represented precisely in the binary format. The closest power of two larger than the initial gain factor is used as the denominator to divide the initial gain factor.

Abstract: In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.

Abstract: Apparatus and methods for phase-locked loops (PLLs) are provided. In certain implementations, a PLL includes a voltage controlled oscillator (VCO) including first and second frequency control circuits, which are coupled to first and second frequency control inputs, respectively. Additionally, the PLL can further include a loop filter, a high frequency pole circuit, and a low frequency pole circuit. The high frequency pole circuit can be electrically connected between the loop filter's output and the VCO's first frequency control input, and the low frequency pole circuit can be electrically connected between the loop filter's output and the VCO's second frequency control input.

Abstract: A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal.

Abstract: A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated.