Abstract: Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.

Abstract: Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell.

Abstract: A clock generator utilized for providing a clock signal includes: a first oscillator and a switching circuit. The switching circuit is coupled to the first oscillator and a second oscillator, and utilized for receiving a first oscillating signal generated from the first oscillator and a second oscillating signal generated from the second oscillator, and selecting one of the first oscillating signal and the second oscillating signal as the clock signal according to a status signal.

Abstract: Systems and methods for providing a rapid switchable high voltage power transistor driver with a constant gate-source control voltage have been disclosed. A low voltage control stage keeps the gate-source voltage constant in spite of temperature and process variations. A high voltage supply voltage can vary between about 5.5 Volts and about 40 Volts. The circuit allows a high switching frequency of e.g. 1 MHz and minimizes static power dissipation.

Abstract: An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter includes a first switch for receiving the reflected voltage, a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first switch, a capacitor coupled to the second terminal of the resistor for holding the reflected voltage, and a second switch coupled to the resistor in parallel, wherein the resistor and the capacitor develop a filter for sampling the reflected voltage which is sampled without filtering by the filter in a first period during a disable period of a switching signal and also sampled with filtering by the filter in a second period during the disable period of the switching signal.

Abstract: A mixer arrangement for generating an analog output signal by mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The mixer arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.

Abstract: A method of frequency down-converting an input signal to an output signal, a first local oscillator signal is generated as a square wave having a duty cycle of 1/3 or 2/3, and the input signal is mixed with first oscillator signal to achieve a first down-converted signal, a second local oscillator signal is generated as a modified square wave having the same period time as the first oscillator signal and a duty cycle of 2/3, of which one part has a positive amplitude and another part has a negative amplitude. The input signal is mixed with the second oscillator signal to achieve a second down-converted signal. The first oscillator signal has a delay of 1/4 of the period time to achieve a phase shift of ?/2 between the oscillator signals, and at least one down-converted signal is multiplied by a pre-calculated factor. The resulting down-converted signals are added to achieve the output signal.

Abstract: A low voltage isolation switch is coupled between an input terminal suitable for receiving a high voltage signal and an output terminal suitable for transmitting this high voltage signal to a load. The isolation switch includes a first driving transistor coupled between a first reference terminal and an intermediate node, a second driving transistor coupled between the intermediate node and the second reference terminal, a control transistor connected across a diode block coupled between the input and output terminals. The control transistor has a control terminal connected to the intermediate node through a low voltage decoupling block that includes first and second substrate terminals, first and second parasitic capacitive element connected to these first and second substrate terminals, and first and second decoupling transistors coupled in parallel to each other and having control terminals connected to the first and second parasitic capacitive elements, respectively.

Abstract: In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch.

Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

Abstract: A device for controlling (10) a power transistor (5), comprises: an amplifying device (15) for monitoring the transistor gate (5) via an output control signal, the device including: a first input connected to the transistor drain, the whole assembly forming a first circuit portion; a second input connected to the transistor source, the whole assembly forming a second circuit portion. The control device comprises means for producing a polarizing current (I1, I2), the current being injected into the first and second inputs (NEG, POS) so as to offset the drain-source voltage measurement and maintain a linear operating mode of the output control signal, prior to opening the transistor, and the same number of N semiconductor junctions in the first and second circuit portions. The device is applicable in particular on battery charging devices.

Abstract: The transition frequency of an inverter can vary with the transconductance of its internal transistors as a function of temperature and bias level. To maintain consistent transition frequency across temperatures, and therefore reduce the phase noise variation introduced by the inverter, systems, methods, and circuits are disclosed for biasing the inverter with a temperature varying current such that the transconductance of transistors remains constant across temperatures, while maintaining the lowest possible power consumption to do so. Various embodiments can include using current sources that have proportional-to-absolute-temperature (PTAT) devices.

Abstract: The trimming circuit includes a plurality of trimmable resistances that may be coupled among them, each resistance being connected in parallel to a respective fuse. The trimming circuit allows burning any number of fuses according to a fixed trimming sequence using only one or two dedicated pins because it includes an input diode-connected transistor and a plurality of trimming transistors of different sectional area, each connected to force current throughout a respective one of the shunt fuses and coupled to the input diode-connected transistor such to mirror the current flowing therethrough. The fuses of the trimming circuit may be burnt by applying a trimming voltage to the diode-connected input transistor with a voltage generator connected between a dedicated pin of the circuit and a terminal at a reference potential, such to force a current therethrough as long as the mirrored currents flowing throughout the fuses burn them.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: An integrated circuit and method are provided for controlling variation in the voltage output from on-chip voltage generation circuitry. The integrated circuit comprises voltage generation circuitry configured to operate from a supplied input voltage and to generate at an output node an on-chip voltage supply different to the supplied input voltage. A circuit block is then arranged to receive the on-chip voltage supply generated by the voltage generation circuitry, during operation of the circuit block the circuit block presenting a varying load on the output node. Oscillation circuitry is also coupled to the output node to provide an additional load on the output node, and is configured to produce an oscillation signal whose frequency varies as the value of the on-chip voltage supply varies. Control circuitry is configured to be responsive to a trigger condition to adjust the additional load provided on the output node by the oscillation circuitry.

Abstract: A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.

Abstract: A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal.

Abstract: A low noise analog filter with adjustable filter frequency includes an oscillatory circuit, whose resonance frequency equals the filter frequency of the filter. The oscillatory circuit has a first circuit branch. One of the frequency determining elements is a capacitance and the other an inductance. The low noise analog filter further includes an amplifier with adjustable amplification installed in one of the two circuit branches. The output of the amplifier is connected with its inverting input via the frequency determining element arranged in such circuit branch. In filter operation, the amplifier amplifies, according to the adjusted amplification, a voltage applied across the frequency determining element arranged in such circuit branch and thereby effects a corresponding change of an electrical current flowing through such frequency determining element.

Abstract: A monolithic integrated circuit (IC) chip containing a plurality of transistors, including: a substrate; a first transistor on the substrate; and a second transistor integrally formed on the substrate with the first transistor, the second transistor having a different structure than the first transistor, wherein the first transistor includes a first material system and the second transistor includes a second material system different from the first material system. The monolithic IC chip may further include a third transistor integrally formed on the substrate with the first and second transistors. The first transistor may include gallium nitride (GaN) and the second and third transistors may include silicon carbide (SiC).

Abstract: An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.

Abstract: A power amplifier circuit, comprising: an input for receiving an input signal to be amplified; a power supply; an amplifier, coupled to the input and the power supply; and a cascode device coupled between the power supply and the amplifier. The circuit is characterized by: a first current source coupled between the input and the amplifier, configured to provide a biasing current which is proportional to absolute temperature; and a second current source for controlling the cascode device, configured to provide a current which is complementary to absolute temperature (CTAT).

Abstract: A power amplifier includes generation, tracking and usage of an envelope of an input RF signal. To improve upon the efficiency of the power amplifier, various configurations include using the tracked envelope, for example, an OFDM signal, to improve the average efficiency. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to generate and track an envelope of an input RF signal and modulate one or more of the input supply voltage, cascode gate bias or parallel PA branches using the tracked envelope.

Abstract: An amplifier circuit of envelope tracking scheme has a timing adjusting unit having a finite number of adjustment values for adjusting time by which the output is delayed from the input, and capable of adjusting a time difference between an input signal and a power supply voltage which reach an amplifier, by making a selection from the adjustment values; a test signal output unit capable of repeatedly sending out a test signal serving as the input signal at predetermined cycles; and an adjustment value determining unit sequentially measuring output power for m (?k) periods from the amplifier while changing an adjustment value of the timing adjusting unit to a different value every k periods of the test signal, searching for an adjustment value at which a total sum of the output power form periods is maximum, and setting the adjustment value on the timing adjusting unit.

Abstract: An integrated circuit for providing a differential interface for an envelope tracking signal is described. The integrated circuit includes a subtraction module having a first input for receiving a digital envelope tracking signal and a second input for receiving a second signal, wherein the subtraction module is arranged to subtract the second signal from the digital envelope tracking signal and produce an envelope tracking signal with a reduced average direct current (DC) component; a digital-to-analog converter (DAC) arranged to receive the envelope tracking signal with the reduced average DC component and produce a differential analog version thereof; and a modulator operably coupled to a differential output of the DAC, wherein the modulator comprises a DC input point arranged to insert a DC component into the differential analog version of the envelope tracking signal.

Abstract: A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal.

Abstract: A differential amplifier circuit including: a differential input stage including a pair of differential MOS transistors, a pair of load elements, and a first constant-current source; an output stage including an output MOS transistor and a second constant-current source; a constant-current MOS transistor provided in parallel to one of the first and second constant-current sources; and a boost current controlling MOS transistor in which a potential of a connection node of the output MOS transistor and the second constant-current source is applied to a gate terminal thereof; wherein the boost current controlling MOS transistor is turned on when a voltage inputted to a gate terminal of one of the pair of differential MOS transistors changes, and a current of the constant-current MOS transistor is added to one of the first and second constant-current sources and is allowed to flow.

Abstract: Apparatus and methods for amplifier power supply control are provided. In certain implementations, an amplifier includes an input amplification stage and a power supply control block for generating a power high supply and a power low supply for the input amplification stage. The power supply control block receives a reference signal indicative of a common-mode input voltage of the amplifier, and the power supply control block adjusts a voltage level of the power high and power low supplies while maintaining a substantially constant voltage difference between the power high and power low supplies. The power supply control block changes the voltage level of the power high and power low supplies based on the reference signal such that the voltage levels of the power high and power low supplies move in relation to the common-mode input voltage.

Abstract: The present disclosure describes a distributed amplifier (DA) that includes active device cells within sections that are configured to provide an input gate termination that is conducive for relatively low noise and high linearity operation. A section adjacent to an output of the DA is configured to effectively terminate the impedance of an input transmission line of the DA. Each active device cell includes transistors coupled in a cascode configuration that thermally distributes a junction temperature among the transistors. In this manner, noise generated by a common source transistor of the cascode configuration is minimized. The transistors coupled in the cascode configuration may be fabricated using gallium nitride (GaN) technology to reduce physical size of the DA and to further reduce noise.

Abstract: Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.

Abstract: An amplifier including: an output stage having two first power supply terminals capable of receiving a first voltage defined by first positive and negative variable potentials with respect to a reference potential; and a circuit for controlling the current in transistors of the output stage with a reference value, wherein the output stage includes a first and a second MOS transistors in series between the first two terminals, the junction point of this series association defining an output terminal of the amplifier; the control circuit includes two measurement MOS transistors having their respective sources and gates coupled to the respective sources and gates of the first and second transistors of the output stage; at least one control branch, comprising transistors in series between two terminals of application of a second voltage, defines nodes connected to the gates of the output transistors, said second voltage being greater than the first one.

Abstract: An amplification system is provided that comprises a push-pull amplifier system having a first power transistor series coupled with a second power transistor that alternately switch between a push-pull amplifier mode of operation and a single-ended amplifier mode of operation. In the push-pull amplifier mode, both the first power transistor and the second power transistor alternately conduct to provide an amplified output signal to an output load in response to an input signal having an amplitude that is greater than or equal to a threshold level. In the single-ended amplifier mode of operation, the first power transistor conducts and the second power transistor is disabled for amplification purposes in response to the input signal having an amplitude that is less than the threshold level.

Abstract: A gain control system may include an input terminal that receives an input signal. The gain control system may include a first transistor having a source connected with the input terminal and a drain connected with an output terminal. The gain control system may include a second transistor having a gate connected with the input terminal and the source of the first transistor. The second transistor may have a drain connected with the output terminal. The second transistor may generate a reduction signal. The output terminal may output an output signal based on the input signal and the reduction signal.

Abstract: An amplifier for wireless receivers and an associated method is provided. The amplifier provides an output signal to an output terminal in response to an input signal received from an input terminal, and further includes a first block and a second block. The first block is coupled between the input terminal and the output terminal, and includes a gain control terminal and a first transistor. The gain control terminal is coupled to a gain control signal, while the gain control signal is provided such that the first transistor is kept operating in a triode region, and a gain of the output signal over the input signal can be seamlessly tuned in response to the gain control signal.

Abstract: An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

Abstract: A reference circuit for an oscillator module is provided. The reference circuit includes a reference voltage generation unit and a reference current generation unit. The reference voltage generation unit includes an electric element having a voltage proportional to absolute temperature (PTAT voltage) and provides a reference voltage based on the PTAT voltage. The reference current generation unit is coupled to the reference voltage generation unit and provides a reference current to the oscillator circuit to serve as an input current based on the PTAT voltage. The oscillator circuit generates a clock signal based on the reference voltage and the input current. The reference voltage and the input current are proportional to absolute temperature and have the same change trend relative to absolute temperature, such that the clock signal is a temperature insensitive signal. An oscillator module including an oscillator circuit and the foregoing reference circuit is also provided.

Abstract: A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.

Abstract: An oscillating circuit for determining a resonant frequency of an electro-mechanical oscillating device and for driving the electro-mechanical oscillating device at the determined resonant frequency includes a driving circuit and a start-up, impetus injection circuit. The driving circuit is configured to receive one or more reference signals and further configured to provide a driving signal related to the reference signals to the electro-mechanical oscillating device. The start-up, impetus injection circuit is operably coupled to the electro-mechanical oscillating device and configured to selectively provide a start-up excitation signal to the electro-mechanical oscillation device. The start-up, impetus injection circuit is activated upon start-up of the oscillating circuit to drive the electro-mechanical oscillation device and the driving circuit determines a resonant frequency by measuring a parameter related to the resonant frequency of the electro-mechanical oscillating device.

Abstract: A flexural mode resonator element includes: a vibration arm extending from a base end toward a tip; a base joined to the vibration arm at the base end; and supporting arms arranged on both sides of the base in a width direction perpendicular to an extending direction of the vibration arm and joined to the base, wherein the base has a reduced cross-section portion disposed along the extending direction of the vibration arm between a joint portion with the vibration arm and a joint portion with the supporting arms, and the reduced cross-section portion is disposed so as to satisfy a relationship 2×W1?L?6×W1 where L is the length of the reduced cross-section portion in the extending direction of the vibration arm, and W1 is the arm width of the vibration arm.

Abstract: A tunable oscillator circuit is disclosed. The tunable oscillator circuit includes an inductor/capacitor (LC) tank circuit comprising a primary inductor coupled in parallel with a first capacitor bank. The LC tank resonates to produce an oscillating voltage at a frequency. The tunable oscillator circuit also includes a 90 degree phase shift buffer coupled to the LC tank and a transconductor. The transconductor is coupled to the 90 degree phase shift buffer and a secondary inductor. The tunable oscillator circuit also includes a secondary inductor that is inductively coupled to the primary inductor and receives a gain-scaled oscillating current from the transconductor. By changing the transconductance, the gain-scaled oscillating current in the secondary inductor will change, thus the effective primary inductance and the oscillation frequency can be tuned.

Abstract: Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.

Abstract: Systems and methods for generating pulsed output signals that employ a gated RF oscillator circuit having an output that is switchably grounded through the emitter of a transistor and including feedback from the output of the circuit to the base of the transistor to create oscillations and to allow a digital input pulse of a desired length to control the start and stop of oscillations created by the transistor.

Abstract: A compact tracking coupler includes a plurality of ridged waveguides arranged circumferentially around a circular waveguide wherein long sides of the ridged waveguides extend circumferentially and short sides of the ridged waveguides extend radially relative to the circular waveguide. The compact tracking coupler can be especially useful in a multi-band antenna feed.

Abstract: The invention relates to a cross polarization multiplexer which doubles the capacity of radio links using a vertical polarization diplexer, a horizontal polarization diplexer and an octagonal transducer module for separating the vertically polarized waves from the horizontally polarized waves. The invention is characterized in that the vertical diplexer and the horizontal diplexer are integrated in a module forming a monoblock body having a specific, simple and inexpensive configuration. This configuration allows the use a single transceiver unit which also provides a cost saving.

Abstract: A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance.

Abstract: A microwave cavity filter is configured for operation in the dual TE22N mode to realize a very high Q factor at very high frequency ranges. The microwave filter is formed from using one or more cylindrical cavities in which two orthogonal field polarizations of the TE22N mode are excited and coupled together by means of a coupling element. Different combinations of inter-cavity irises provide for both direct and cross-coupling of aligned field polarizations in adjacent cavities, as required, to realize complex filter functions. The irises may be formed in either a side or end wall of the cavities for both collinear and planar mount configuration. Negative mode coupling also allows for transmission zeros to be realized on either side of the filter passband.

Abstract: A field programmable filter array with high spectral isolation and reconfigurability. A bank of resonators can be programmed at will and on the fly to give any type of filtering response. The order, type and bandwidth of the filter are electronically reconfigured. Each subset of resonators can switch between bandstop and bandpass configurations and form custom filter shapes consisting of combinations of bandstop and bandpass filters. The filter can include a unit cell of a resonator with a series of switches to enable coupling to any of its nearest neighbors. The path in which the flow of energy takes through the array of resonators is dynamic, and the filtering function which is created is dialable on demand.

Abstract: A micro-relay that overcomes some of the limitations and drawbacks of the prior art is disclosed. The micro-relay comprising: (1) a first substrate comprising one or more monolithically integrated planar coils for generating a magnetic field; and (2) a second substrate comprising a magnetically actuated switch having a moving contact that selectively moves in a plane parallel to its substrate. The first and second substrate are aligned and bonded to collectively provide a closed magnetic circuit that efficiently channels the generated magnetic field through the switch.

Abstract: A wireless switch comprises a mechanical oscillator, a mechanical impulse deliverer, a first array of magnets positioned on a planar surface, a first conductor, and a power management circuit. The mechanical impulse deliverer delivers a mechanical impulse to the mechanical oscillator when the wireless switch is switched. The first array comprises a one dimensional or two dimensional array of magnets. The first conductor comprises a first serpentine conductor. The power management circuit provides DC power as a result of relative motion due to the mechanical oscillator between the first array of magnets and the first conductor.

Abstract: For so-called pole wheels, as they are used for angle detection through magnetic field sensors, centering is facilitated and the service life of the pole wheel is increased by fixating the magnet ring rotationally and disengageable through sliding it on a prefabricated hub through a mounting device, which is disposed there between, like e.g. a friction locking band.