Abstract: An operation method of a semiconductor memory device includes forming a first data distribution by performing a first programming operation during a first write operation, outputting a predetermined data by detecting the first data distribution on the basis of a first reference voltage corresponding to the first programming operation during a first read operation, forming a second data distribution by performing a second programming operation during a second write operation, and outputting data that is the same as the predetermined data corresponding to the first data distribution during the first read operation by detecting the second data distribution on the basis of a second reference voltage corresponding to the second programming operation during a second read operation.

Abstract: A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line, and a second data line. The second type is different from the first type. The first data line is coupled with a first terminal of the sense amplifier. The second data line is coupled with a second terminal of the sense amplifier. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage.

Abstract: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Abstract: A method including providing a plurality of random access memories having at least a first region, a second region and a third region; storing protected data on the first region on at least two of the random access memories, where the protected data is stored distributed among the at least two random access memories of the first region; storing parity information for the protected data on the second region on at least a third one of the random access memories; and storing unprotected data on the third region.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes memory cells having first to fourth middle states corresponding to different threshold voltage distributions. The semiconductor memory device also includes a peripheral circuit configured to perform a first program operation to program memory cells having the third and the fourth middle states to have four upper states and perform a second program operation to program memory cells having the first and the second middle states to have another four upper states.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed.

Abstract: An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first write line and the second SRAM column is selected with a second write line.

Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.

Abstract: Disclosed is a semiconductor memory device. A semiconductor memory device in accordance with an embodiment of the present invention includes a write driver configured to provide voltage necessary for a write operation when the write operation is performed, a switch block connected to the write driver and configured to control the path of the write voltage, and a cell block connected to the switch block, wherein a constant voltage is supplied to a node leading to a cell selection path within the cell block using the write driver as a voltage source.

Abstract: Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled.

Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.

Abstract: A semiconductor device may include an internal circuit configured to perform write operations in response to each of a plurality of write commands, wherein the plurality of write commands are sequentially input to the internal circuit, a first pulse generation unit configured to generate a first pulse activated during a first delay amount in response to a write command, a second pulse generation unit configured to generate a second pulse activated during the first delay amount in response to a delayed write command out of the plurality of write commands after a second delay amount from the activation time of the first pulse, and a transfer control unit configured to prevent commands other than the plurality of write commands from being transferred to the internal circuit during a sum of the activation period of the first pulse and the activation period of the second pulse.

Abstract: A semiconductor device includes a plurality of memory cell arrays each including a plurality of memory cells and a first bit line coupled to the memory cells, a second bit line, a first voltage line, a plurality of first sense amplifiers each including a first transistor of which a gate is coupled to the first bit line of a corresponding one of the memory cell arrays and a second transistor, the first and second transistors in each of the first sense amplifiers being coupled in series between the second bit line and the first voltage line, a temperature detection circuit configured to detect a temperature of the semiconductor device, and a control circuit configured to receive an output of the temperature detection circuit and to supply a control signal to the gate of each of the second transistors.

Abstract: A system for repairing a plurality of semiconductor chips each comprising a data storage region including electric fuses connected to the data storage regions of the plurality of semiconductor chips, a defect determination unit configured to read the data of a chip that is actually accessed and the data of an idle chip in the data storage regions, compare the actually accessed and read data with the data of the idle chip, and detect a defect based on a result of the comparison, a storage unit configured to store the defective position of the defect according to a result of the defect determination unit, and a repair unit configured to repair the defect through an E fuse connected to the position of the defect using a reset signal.

Abstract: A memory includes first to Nth word lines, first to Mth redundancy word lines configured to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate at least one adjacent word line adjacent to a Kth redundancy word line (1?K?M) in response to an active signal, in the case where a word line corresponding to an inputted address among the first to Nth word lines is replaced with the Kth redundancy word line among the first to Mth redundancy word lines in a first mode.

Abstract: A memory may comprise a first bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, a second bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate, in the case where a word line corresponding to an inputted address among the first to Nth word lines in a bank selected between the first bank and the second bank is replaced with a Kth (1?K?M) redundancy word line among the first to Mth redundancy word lines during an operation in a first mode, at least one adjacent word line adjacent to the Kth redundancy word line of the selected bank.

Abstract: Disclosed is a semiconductor memory device that includes a late write register for temporarily storing a late write address and late write data. When a write command is input, the semiconductor memory device performs a dummy read, creates a data set having a predetermined bit width from data read by the dummy read and write data, and generates a correction bit from the data set. In parallel with the generation of the data set and the generation of the correction bit, the semiconductor memory device not only performs a late write to write the late write data at the late write address in the memory core, but also stores a write address in the late write register as a new late write address and stores the data set and the correction bit in the late write register as new late write data.

Abstract: A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.

Abstract: A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.

Abstract: A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell.

Abstract: A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.

Abstract: A semiconductor memory device includes a first memory block group including memory blocks coupled to first sub bit lines, a second memory block group including memory blocks coupled to second sub bit lines, an operation circuit coupled to main bit lines, and configured to perform an operation for data input/output to/from a memory block selected from the first memory block group or the second memory block group, and a bit line control circuit configured to differently control sub bit lines of the selected memory block group and sub bit lines of the unselected memory block groups in response to group select signals for selecting a memory block group including the selected memory block of the first memory block group and the second memory block group and voltages of the main bit lines controlled by the operation circuit.

Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a memory block and one or more peripheral circuits. The memory block includes a bit line, a common source line, a vertical channel layer coupled between the bit line and the common source line, word lines surrounding the bit line at different heights from a semiconductor substrate, and memory cells formed in portions where the word lines surround the vertical channel layer. The one or more peripheral circuits are configured to set the word lines to a floating state to supply holes to the vertical channel layer when a precharge voltage is applied to the common source line, and set word lines of memory cells to be erased to a ground state when an erase voltage is applied to the common source line.

Abstract: A semiconductor memory device includes a fuse unit including a fuse configured to be programmed with a repair target address, an enable unit configured to enable the fuse unit, an output unit configured to output a signal corresponding to whether the fuse unit is programmed or not, and a control unit configured to control a voltage difference between both ends of the fuse unit in response to a control signal.

Abstract: An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.

Abstract: A semiconductor memory device includes a bit line pre-sense amplifier configured to sense a potential difference between bit line pair and amplify the voltages of the bit line pair based on the sensed potential difference, a bit line main sense amplifier configured to sense a potential difference between the bit line pair and amplify the voltages of the bit line pair to first and second driving voltages based on the sensed potential difference, and a power supplying controller configured to supply the second driving voltage to the bit line pre-sense amplifier and the bit line main sense amplifier.

Abstract: A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.

Abstract: A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.

Abstract: A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

Abstract: A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.

Abstract: A semiconductor memory device includes a block decoder configured to output block selection signals for selecting memory blocks in response to a row address signal, a first memory block including a first drain select line, a first source select line, and a first word line group including a plurality of first word lines disposed between the first drain select line and the first source select line, the first memory block disposed between the block decoder and a first switching group, the first switching group configured to transmit first operating voltages to the first memory block in response to a first block selection signal among the block selection signals, and a first block word line configured to transmit the first block selection signal to the first switching group and disposed over the first memory block to avoid overlapping with the first word line group.

Abstract: An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

Abstract: A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.

Abstract: A method for dosing a powder into a kneader is provided, wherein the powder is fed via a feeder-mechanism into a feeding hole of the kneader. The powder falls from an additional feeding device of the feeder-mechanism into one of at least four segments of a rotary valve of the feeder-mechanism.

Abstract: The invention relates to mixing devices, methods of operating mixing devices, and methods of blending a granular substrate with a coating material. These mixing devices and methods substantially prevent the agglomeration of solids and/or viscous liquids on rotational and/or static elements of the mixing device.

Abstract: A process for mixing a liquid stored in a vessel, in which gas is sucked in from the gas phase present above the liquid interface with a suction apparatus present in the liquid, and released into it again for the gas-induced mixing of the liquid.

Abstract: A safety protection device for a speed changing device of a mixer is provided with a control unit on an operating rod assembly, and a tact switch is used in combination with the control unit. When using the operating rod assembly to perform gear shift, the user can feel whether the gear has been shifted to the correct position based on position change of the control unit with respect to the tact switch. During gear shift, the tact switch will turn off the power to the motor controller to stop the motor, so that gear shift operation can be performed more smoothly without interference with the motion transmission parts of the mixer, and consequently, the life of the mixer can be extended.

Abstract: A sample processing apparatus comprising a controller; an agitating section configured to agitate a sample in a sample tube; and a processing section configured to process the agitated sample, wherein the controller is configured to control the agitating section to agitate a sample in a first type of sample tube under a first agitation condition, and to control the agitating section to agitate a sample in a second type of sample tube, which contains a sample of lower volume than the first type of sample tube, under a second agitation condition different from the first agitation condition.

Abstract: A tumbling container is mounted for rotation with a curved screen fixedly mounted within the tumbling container. A multiple vane paddle is mounted to a shaft that is rotatably mounted to the tumbling container. The paddle vanes are formed with angular edges. As the tumbler rotates and the paddle rotates, powder is repeatedly dropped onto the screen to be sifted with the aid of the paddle. Rotating the tumbler further drops unsifted portions of the powder from the screen to mix with additional powder in the tumbler body. Thus, sifting and blending of powders is accomplished in one single operation. The invention utilizes an apparatus having a multiple section screen and a multiple section paddle to enable assembly through the openings in the tumbling container. The screen of a second embodiment has a cowl adjacent to each screen opening to optimize powder lump disintegration.

Abstract: An object information acquisition apparatus according to the present invention includes a plurality of conversion elements configured to receive waves reflected at each position inside an object, and convert the reflected waves into a plurality of received signals, a fixed signal processing unit configured to apply addition with a predetermined weight to the plurality of received signals to acquire first distribution information, an adaptive signal processing unit configured to apply adaptive signal processing to the plurality of received signals to acquire second distribution information, and a display control unit configured to input the first distribution information and the second distribution information, and output image information to a display unit, wherein the display control unit outputs image information for displaying in parallel in the same screen an image of the first distribution information, an image of the second distribution information or a combined image of the first and second distributio

Abstract: An object information obtaining apparatus according to the present invention includes a fixed signal processing unit configured to perform addition processing with a predetermined weight by using a plurality of receiving signals to obtain first distribution information, and an adaptive signal processing unit configured to perform adaptive signal processing with a weight adaptively changing according to the receiving signals by using the plurality of receiving signals to obtain second distribution information, wherein the display control unit, upon reception of information about a specified area in the image of the first distribution information input by the user in a state where the image of the first distribution information is displayed, is configured to output image information for displaying on the display unit an image of the second distribution information or the combined image for the first and second distribution information, corresponding to the specified area.

Abstract: An object information acquisition apparatus according to the present invention includes a fixed signal processing unit configured to perform addition processing with a predetermined weight on a plurality of receiving signals to acquire first distribution information, and an adaptive signal processing unit configured to perform on the plurality of receiving signals adaptive signal processing with a weight adaptively changing according to the receiving signals to acquire second distribution information, wherein the display control unit receives enlargement instruction information for the image of the first distribution information input by the user in a state where the image of the first distribution information is displayed, and outputs image information for displaying on the display unit an enlarged image of the image of the second distribution information or an enlarged image of the combined image of the first and second distribution information.

Abstract: A downscan imaging sonar utilizes a linear transducer element to provide improved images of the sea floor and other objects in the water column beneath a vessel. A transducer array may include a plurality of transducer elements and each one of the plurality of transducer elements may include a substantially rectangular shape configured to produce a sonar beam having a beamwidth in a direction parallel to longitudinal length of the transducer elements that is significantly less than a beamwidth of the sonar beam in a direction perpendicular to the longitudinal length of the transducer elements. The plurality of transducer elements may be positioned such that longitudinal lengths of at least two of the plurality of transducer elements are parallel to each other. The plurality of transducer elements may also include at least a first linear transducer element, a second linear transducer element and a third linear transducer element.

Abstract: A target object detection device is provided. The device includes a signal processor, a display unit, and a controller. The signal processor receives a reception signal generated based on an echo of an ultrasonic wave from a target object and generates echo data corresponding to a distance from a transmission source of the ultrasonic wave to the target object every time the ultrasonic wave is transmitted. The display unit has a display screen with a first side and a second side that is turnable in an axial direction perpendicular to the display screen, and displays an image on the display screen based on the echo data. The controller sets a range with respect to time at which the ultrasonic wave is transmitted, and outputs the echo data corresponding to the ultrasonic wave within the time range according to turning of the display screen.

Abstract: A wave glider system includes a float having geodetic navigation equipment for determining a geodetic position and heading thereof. The glider includes an umbilical cable connecting the float to a sub. The sub has wings operable to provide forward movement to the float when lifted and lowered by wave action on the surface of a body of water. At least one geophysical sensor streamer is coupled to the sub. The at least one geophysical sensor streamer has a directional sensor proximate a connection between the sub and one end of the at least one geophysical sensor streamer to measure an orientation of the streamer with respect to a heading of the float.

Abstract: A method for de-ghosting marine seismic trace data is described. A reference seismic trace and a candidate seismic trace are selected from acquired seismic data. The acquired seismic data is gathered using a configuration wherein either a first streamer and a second streamer are disposed at different depths relative to one another and are laterally offset relative to one another, or using a configuration wherein a first source and a second source are disposed at different depths relative to one another and are laterally offset from one another. The reference seismic trace and the candidate seismic trace are processed, e.g., to perform normal moveout correction and/or vertical datum shifting, and the processed reference seismic trace is de-ghosted using the processed, candidate seismic trace.

Abstract: A fiber optic distributed vibration system for detecting seismic signals in an earth formation is provided. The system includes a fiber optic cable deployed in a borehole that extends into the earth formation and which is configured to react along its length to a seismic wave incident on the fiber optic cable from outside the borehole. An optical source launches an optical signal into the fiber optic cable while the seismic wave is incident thereon. A receiver detects coherent Rayleigh noise (CRN) produced in response to the optical signal. A processing circuit processes the detected CRN signal to determine characteristics of the earth formation.

Abstract: A subsea electronic information system for managing data related to a characteristic of subsea equipment locatable subsea. The system includes sensors locatable subsea and in communication with and capable of measuring a characteristic of the subsea equipment. A sensor interface box (SIB) separate from the sensors and locatable subsea includes a processor and a memory device capable of receiving and storing sensor measurement data. Additionally, the SIB is in data and power communication with the sensors. The system further includes a subsea retrievable data capsule capable of recording all system data over a long period. The capsule may be recovered from subsea (independently of the other elements of the information system) for forensic analysis of the recorded data.