Abstract: Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors.

Abstract: Systems and devices in which multi-bit phase change memory is used, including memory systems and memories, as well as methods for operating such systems and devices. According to the present invention, a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from multiple phase change memory reference cells designated to store said adjacent logical states. By writing reference cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track output changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. Ordering of states within said reference cells can be used to encode information such as checksums of corresponding words.

Abstract: A semiconductor stack for performing at least a logic operation includes adjacent layers arranged in a stacked configuration with each layer comprising at least a phase-change memory cell in which a phase-change material is provided between a heater electrical terminal and at least two further heater electrical terminals, the phase-change material between the heater electrical terminal and each of the two further heater electrical terminals being operable in one of at least two reversibly transformable phases, an amorphous phase and a crystalline phase; wherein the semiconductor stack, when in use, is configurable to store information by way of an electrical resistance of the phase of the phase-change material between each heater electrical terminal and each of the two further heater electrical terminals in each layer, and the logic operation is performed on the basis of the information stored in the adjacent layers.

Abstract: A first write driver applies a first voltage above a fixed potential to a first terminal. A second write driver applies a second voltage that is higher above the fixed potential than the first voltage to a second terminal. There is at least one magnetic tunnel junction (MTJ) structure coupled at the first terminal at a first side to the first write driver and coupled at the second terminal at a second side to the second write driver. The first side of the MTJ structure receives the first voltage and the second side of the MTJ structure receives a ground voltage to change from a first state to a second state. The second side of the MTJ structure receives the second voltage and the first side of the MTJ structure receives the ground voltage to change from the second state to the first state.

Abstract: A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.

Abstract: A semiconductor memory device, a memory system having the same, and a method of fabricating the same are provided. The semiconductor memory device includes a vertical channel layer protruding from a surface of a substrate, a tunnel insulating layer and a charge storage layer, which are surrounding the vertical channel layer, a blocking layer surrounding the charge storage layer, interlayer insulating layers stacked along the blocking layer, and conductive layers interposed between the interlayer insulating layers. The blocking layer includes a metal oxide layer.

Abstract: A semiconductor memory device, a memory system including the same, a method of manufacturing the same and a method of operating the same are provided. The semiconductor memory device includes a pipe channel layer, vertical channel layers coupled to a top surface of the pipe channel layer, a first pipe gate substantially surrounding a bottom surface and side surfaces of the pipe channel layer, a boosting gate formed over the pipe channel layer, and first insulating layers and conductive layers alternately stacked over the boosting gate and the pipe channel layer.

Abstract: Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

Abstract: A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: According to one embodiment, a semiconductor memory device includes memory cells and memory strings. When lower-page data is first written into a memory string, all memory cells corresponding to the lower-page data are made write-target, a program-verifying level of first ones of the write-targeted memory cells is a first threshold level, and a program-verifying level of second ones of the write-targeted memory cells is a second threshold level. The first threshold level corresponds to data associated with the lowest threshold level and is higher than a third threshold level. The second threshold level is higher than the first threshold level.

Abstract: Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays.

Abstract: According to one embodiment, a memory system includes a semiconductor memory including a memory core having first and second circuits and an input/output circuit, a control device, a voltage control circuit which generates first to third drive voltages, and the first to third power supply lines separated from each other. The voltage control circuit supplies the first drive voltage to the first circuit through the first power supply line, the second drive voltage lower than the first drive voltage to the input/output circuit and the control device through the second power supply line, and the third drive voltage to the second circuit through the third power supply line.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level.

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Abstract: A nonvolatile memory device includes: a plurality of memory cells arranged in a region where word lines and bit lines intersect, a data read/write circuit including a plurality of latches configured to temporarily store data inputted from an external device, and configured to perform a program operation on the memory cells based on data stored in the latches, and a skip data control unit configured to determine whether data to be programmed into the memory cells are available, and to store program-inhibit data in a latch corresponding to a memory cell which is determined to not contain any data.

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Abstract: A semiconductor device including a memory block, which includes memory cells coupled to bit lines. The semiconductor device further includes a first sensing circuit coupled to an even bit line and configured to sense current flow through the even bit line in response to an even bit line control signal and an even discharge signal. The semiconductor device further includes a second sensing circuit coupled to an odd bit line and configured to sense current flow through the odd bit lines in response to an odd bit line control signal and an odd discharge signal. The first sensing circuit and second sensing circuit are configured to supply a ground voltage to the odd bit line when sensing the current flow through the even bit line, and to supply the ground voltage to the even bit line when sensing the current flow through the odd bit line.

Abstract: An operating method of a semiconductor memory device is provided. The method includes supplying a first voltage to a selected bit line where a selected memory cell among memory cells is connected and a second voltage, which is higher than the first voltage, to an unselected bit line, supplying a third voltage to a selected drain select line where the selected memory cell is connected, and a fourth voltage lower than the third voltage to an unselected drain select line; and supplying a fifth voltage to a selected word line where the selected memory cell is connected, and a sixth voltage, which is lower than the fifth voltage, to an unselected word lines for a program operation.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewritable memory cells and a select transistor connected in series; and a row decoder configured to select anyone of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations. The row decoder comprises: a plurality of first transfer transistors each disposed in a first region and connected to any one of the memory cells; and a plurality of second transfer transistors each disposed in a second region and connected to the select transistor, the second region being a residual region of the first region.

Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.

Abstract: A nonvolatile memory device includes: a page buffer block including a plurality of cache latches configured to temporarily store data inputted to program memory cells, and configured to program the inputted data into the memory cells; and a column decoder configured to provide column select signals for selecting the cache latches to the cache latches according to a column address, wherein the column decoder activates column select signals for selecting a part of the cache latches at substantially the same time, while data are set up in the cache latches.

Abstract: A NOR flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.

Abstract: N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

Abstract: Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract: Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.

Abstract: A semiconductor memory device includes a memory cell array in which memory cells are arranged, and a first wiring connected to the memory cells. A discharging circuit discharges the voltage of the first wiring according to a first current. In addition, a charging circuit charges the voltage of the first wiring according to a second current. A control circuit detects the voltage of the first wiring and controls a magnitude of the second current based on the detected voltage. A current detection unit generates a third current proportional to the second current and generates a detection result based on a magnitude of the third current. The discharging circuit is configured to control a magnitude of the first current in accordance with the detection result.

Abstract: According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed.

Abstract: According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells, based on potentials of the respective bit lines. Transistors constituting the sense amplifier are arranged one by one within an arrangement width of the sense amplifier in the direction of the bit lines. A gate length direction of the transistors is identical to the direction of the bit lines. A longer side direction of a contact electrode connected to an active area of the transistor is identical to the direction of the bit lines.

Abstract: A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Abstract: Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line. The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line.

Abstract: An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.

Abstract: A semiconductor memory device includes a memory block configured to include memory cells coupled to word lines and a peripheral circuit configured to perform a first program operation, a program verifying operation and a second program verifying operation for memory cells coupled to a word line selected from the word lines, and supply program allowable voltages having different levels to selected bit lines of program allowable cells located between program inhibition cells in the first program operation and the second program operation.

Abstract: A semiconductor memory device includes a current sourcing unit configured to supply a given current to a source line when a read operation is performed, a memory cell string configured to store data and receive the given current from the source line, and a data sensing unit configured to sense the given current transferred from the memory cell string to a bit line and latch the sensed given current in a data form.

Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE? is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.

Abstract: A method of operating a semiconductor device includes storing a supplying condition of a read voltage inputted from an external source into an internal register to perform a read operation of memory cells, performing the read operation repetitively with changing levels of the read voltage according to the supplying condition of the read voltage in the event that the number of error bits in a data read from the memory cells exceeds an allowable range, and storing an iteration number of the read operation in the internal register in case the number of the error bits falls within the allowable range.

Abstract: According to one embodiment, a storage device includes multiple cell transistors connected in series, a first selecting transistor connected between a first end of the connected cell transistors and a first line, and a second selecting transistor connected between a second end of the connected cell transistors and a second line. Writing to the multiple cell transistors is includes the following operations: a first voltage is applied to a gate of the first selecting transistor, and a second voltage lower than the first voltage is applied to the gate of the second selecting transistor; a verify voltage is applied to a selected word line, and a pass voltage is applied to non-selected word lines. A third voltage lower than the first voltage is then applied to the gate of the first selecting transistor, and a program voltage is applied to the selected word line.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: A non-volatile memory device, a method for controlling the same, and a data processing system using the device and method are disclosed, which relates to a technology for controlling operations of a flash memory device. The non-volatile memory device comprises a cell array configured to comprise a plurality of cells coupled between a word line and a bit line; a drive controller configured to calculate a constant value corresponding to variation in word-line resistance values measured at individual word-line positions, combine the constant value with a word-line address, and set a rising time of the word line; and a voltage provider configured to provide a bias voltage in response to the rising time set in the drive controller.

Abstract: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

Abstract: This technology relates to nonvolatile memory devices and methods of manufacturing the same. A nonvolatile memory device can include a memory cell array configured to include a plurality of strings, a page buffer unit connected to the plurality of strings, respectively, and configured to sense data, and a switching unit disposed between the memory cell array and the page buffer unit and configured to comprise a variable resistor.

Abstract: A semiconductor device includes a memory cell array configured to include a plurality of memory cells connected between a plurality of bit lines and a plurality of word lines, a bit line sense amplifier connected to a bit line of the bit lines and configured to amplify data stored in a selected memory cell and transfer the amplified data to a segment I/O line, a control signal generator configured to determine a level of an I/O switch control signal in response to a level of a power source voltage, and a local sense amplifier connected between the segment I/O line and an local I/O line and configured to couple or separate the segment I/O line and the local I/O line in response to the I/O switch control signal, amplify the data transferred to the segment I/O line, and supply the amplified data to the local I/O line.