Abstract: A rectifier circuit includes a first alternating current (AC) voltage input terminal, a second AC voltage input terminal, a signal generating circuit, a first energy generating circuit, a second energy generating circuit, a third energy generating circuit, a first output terminal, and a second output terminal The first and second AC voltage input terminals receive an AC voltage. The signal generating circuit generates control signals. The first energy storing circuit is charged by the AC voltage. In a positive period of the AC voltage, the first energy storing circuit discharges to the second energy storing circuit.

Abstract: An inverter according to an embodiment of the present disclosure may include a converter having a switch, configured to convert a DC voltage into a half-wave rectified sine waveform voltage; a switching device unit having a switch, configured to convert the half-wave rectified sine waveform voltage into a sine waveform voltage; and a controller configured to control the on/off of the switch of the converter and the switch of the switching device unit.

Abstract: A circuit arrangement includes a first transistor device and a second transistor device. Each transistor device includes a first load terminal, a second load terminal, a gate terminal, and a control terminal. The first load terminals are electrically connected, and the control terminals are electrically connected. A capacitive storage element is connected between the first load terminals and the control terminals.

Abstract: A system for optimizing switching dead-time includes a power converter that includes a half-bridge circuit comprising a first switch coupled in series with a second switch, first and second state detection circuits respectively coupled to the first and second switches and configured to respectively detect an activation state of the first and second switches. First and second switch control circuits coupled respectively to the first and second switches are configured to respectively toggle the first and second switches between an activate state and a deactivated state. The first switch control circuit includes a first input configured to receive an activation signal from the second state detection circuit indicative of the activation state of the second switch, and the second switch control circuit includes a first input configured to receive an activation signal from the first state detection circuit indicative of the activation state of the first switch.

Abstract: In an inverter device, a first three-level circuit includes first to fourth preceding-stage switch elements connected in series between a first input end and a ground and a first charging and discharging capacitor. A second three-level circuit includes fifth to eighth preceding-stage switch elements connected in series between a second input end and the ground and a second charging and discharging capacitor. The first and second two three-level circuits define a five-level circuit that is subjected to switching with the carrier frequency of PWM modulation. The output polarity of a subsequent-stage bridge clamping circuit is inverted between the anterior half cycle and the posterior half cycle of a power supply frequency.

Abstract: In a power-system-interconnected inverter device, PI control circuits obtain voltage correction values in directions reducing the current errors on the basis of current errors serving as differences between target current values and detection values. Multiplexers provide modulation circuits with voltage target values corrected by the voltage correction values being added to voltage detection values. The modulation circuits provide gate signals for switch elements in multilevel circuits. In addition, a sign circuit provides gate signals for switch elements in a bridge clamping circuit.

Abstract: A content addressable memory (CAM) suppresses an indication of a match in response to determining that the entry that stores data matching received compare data is the subject of a write operation. To suppress the indication, an address decoder decodes a write address associated with the write operation to determine the entry of the CAM that is the subject of the write operation, and provides control signaling indicative of the determined entry. The CAM uses the control signaling to suppress any match indications for the entry being written, thereby preventing erroneous match indications.

Abstract: A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers.

Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including first lines, second lines, and memory cells provided at each of intersections of the first lines and the second lines; and a control unit including a row control circuit, a first column control circuit provided on a side of one ends of the second lines, and a second column control circuit provided on a side of the other ends of the second lines, the control unit, during an access operation, controlling a potential of the first lines and the second lines such that a bias, which is lower than that applied to a certain unselected memory cell, is applied to those of unselected memory cells that are located more toward a center of the memory cell array in the column direction than the certain unselected memory cell.

Abstract: Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

Abstract: According to one or more embodiments of the present invention, the semiconductor memory device of this disclosure includes the first bit line and the second bit line. Each of the multiple memory cells includes a memory element and a transistor, which are connected in series between the first and the second bit lines. Multiple memory cells are connected in parallel between the first and the second bit lines. In the first memory cell, its memory element is connected to the first bit line, and its transistor is connected to the second bit line. In the second memory cell, its memory element is connected to the second bit line, and its transistor is connected to the first bit line.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.

Abstract: A shift register type magnetic memory according to an embodiment includes: a magnetic nanowire; a magnetic material chain provided in close vicinity to the magnetic nanowire, the magnetic material chain including a plurality of disk-shaped ferromagnetic films arranged along a direction in which the magnetic nanowire extends; a magnetization rotation drive unit configured to rotate and drive magnetization of the plurality of ferromagnetic films; a writing unit configured to write magnetic information into the magnetic nanowire; and a reading unit configured to read magnetic information from the magnetic nanowire.

Abstract: A program method for an e-fuse array circuit includes receiving an address and a multi-bit program data, programming the multi-bit program data in e-fuses designated by the address, reading a multi-bit read data from the e-fuses, and comparing bits of the multi-bit program data with bits of the multi-bit read data, wherein if the bits of the multi-bit program data are identical to the bits of the multi-bit read data, a program operation is terminated; and if the bits of the multi-bit read data are not identical to the bits of the multi-bit program data, then the programming of the multi-bit program data, the reading of the multi-bit read data, and the comparing of the bits are performed again.

Abstract: A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure.

Abstract: A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.

Abstract: Some embodiments include apparatuses and methods having a first memory element and a first select component coupled to the first memory element, a second memory element and a second select component coupled to the second memory element, and an access line shared by the first and second select components. At least one of the embodiments can include a circuit to generate a signal indicating a state of the second memory element based on a first signal developed from a first signal path through the first memory element and a second signal developed from a second signal path through the second memory element.

Abstract: Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and reverse-biased programming pulses.

Abstract: Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an over-reset state representing a logic value.

Abstract: Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device.

Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Abstract: A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

Abstract: A resistive random access memory (RRAM), a controlling method for the RRAM, and a manufacturing method therefor are provided. The RRAM includes a first electrode layer; a resistance switching layer disposed on the first electrode layer; a diffusion metal layer disposed on the resistance switching layer; and a second electrode layer disposed on the diffusion metal layer, wherein at least one extension electrode is disposed in the resistance switching layer.

Abstract: An operating method of a variable resistance memory device including a pre-read step which may include the steps of: reading a first reference cell using a first reference voltage; reading a second reference cell using a second reference voltage; and setting a third reference voltage based on the first and second reference voltages; and a main read step of reading a selected memory cell using the third reference voltage.

Abstract: A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.

Abstract: This semiconductor memory device comprises: a memory cell array configured as an arrangement of memory cells disposed at intersections of a plurality of first lines disposed substantially in parallel and a plurality of second lines disposed to intersect the first lines, each of the memory cells including a variable resistance element; and a control circuit configured to control the memory cell array. The control circuit is configured to change a voltage value of a resetting verify voltage applied for confirming completion of the resetting operation according to a degree of change of resistance of the memory cell when performing the resetting operation to change the memory cell from a low-resistance state to a high-resistance state.

Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array including memory cells, each of the memory cells disposed at each of intersections of first lines and second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell is applied with a first potential difference required in an operation of the selected memory cell. The control circuit is configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation, the number of selected memory cells simultaneously applied with the first potential difference can be changed.

Abstract: In a nonvolatile memory element, when a voltage value of an electric pulse has a relationship of V2>V1>0 V>V3>V4 and a resistance value of a variable resistance layer has a relationship of R3>R2>R4>R1, the resistance value of the variable resistance layer becomes: R2, when the electric pulse having a voltage value of V2 or greater is applied between electrodes; R4, when the electric pulse having a voltage value of V4 or smaller is applied between the electrodes; R3, when the resistance value of the variable resistance layer is R2 and the electric pulse having a voltage value of V3 is applied between the electrodes; and R1, when the resistance value of the variable resistance layer is R4 and the electric pulse having a voltage value of V1 is applied between the electrodes.

Abstract: A semiconductor device includes a data verification device. The data verification device includes a data storage unit for storing data to be input to a memory region in response to a first or second control signal, an input data verifier for deactivating an output of a sense amplifier in response to the first control signal and transmitting the input data stored in the data storage unit to an external pad, and a sense-amplifier verifier for transmitting the input data stored in the data storage unit to the sense amplifier upon in response to the second control signal.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory layers; and a control unit configured to control a voltage applied to the memory cell array. Each of the memory layers comprises a first line and a second line, and further includes a memory cell disposed between the first line and the second line and including a variable resistance element. The control unit is configured to, when executing a forming operation on the memory cell array, execute the forming operation sequentially on the plurality of memory layers. The forming operation is executed sequentially on the memory layers in ascending order of a magnitude of a non-selected current flowing in a non-selected memory cell during the forming operation.

Abstract: According to an embodiment, a non-volatile memory device includes a first conductive layer, a second conductive layer, and a resistance change layer provided between the first conductive layer and the second conductive layer. The resistance change layer is capable of making a transition between a low-resistance state and a high-resistance state, and includes an oxide containing at least one of hafnium (Hf) and zirconium (Zr), at least one selected from the group consisting of barium (Ba), lanthanum (La), gadolinium (Gd) and lutetium (Lu), and nitrogen (N).

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

Abstract: An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current.

Abstract: A storage device stores data in groups of memory cells using vectors corresponding to voltage code codewords, each codeword having k entries. Entries have values selected from a set of at least three entry values and 2n distinct inputs can be encoded into k-entry codewords for some n>k. A vector storage element comprising k cells can store an k electrical quantities (voltage, current, etc.) corresponding to a codeword. The voltage code is such that, for at least one position of a vector, there are at least three vectors having distinct entry values at that position and, for at least a subset of the possible codewords, the sum of the entry values over the positions of the each vector is constant from vector to vector in that subset. The storage device might be an integrated circuit device, a discrete memory device, or a device having embedded memory.

Abstract: An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first column select line and the second SRAM column is selected with a second column select line.

Abstract: A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described. Methods associated with the use of the sense amplifier enable signal delay circuit and for the sense amplifier enable signal generation delay are also described.

Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needed boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.

Abstract: A method for providing a SRAM cell having a dedicated read port separated from a write port includes providing a first and a second bit-line placed in parallel forming a complementary bit-line pair for the dedicated read port, and providing a third and a fourth bit-line placed in parallel forming a complementary bit-line pair for the write port. The method further includes providing a positive voltage supply line disposed between a first and a second ground line placed in parallel, providing a first and a second metal line adjacently flanking and in parallel to the first bit-line, and providing a third and a fourth metal line adjacently flanking and in parallel to the second bit-line to provide a new SRAM cell structure having a balanced read and write operation speed and an improved noise margin.

Abstract: A static random access memory (SRAM) is provided for establishing an initialization state. The SRAM connects to a plurality of signal lines including a bit line and an inverse bit line. The SRAM includes first and second inverters, a voltage potential and a ground. The first inverter includes a first n-type metal oxide semiconductor (MOS) transistor having a first n-type threshold voltage and a first p-type MOS transistor having a first p-type threshold voltage. The second inverter includes a second n-type MOS transistor having a second n-type threshold voltage and a second p-type MOS transistor having a second p-type threshold voltage. The first transistors connect respectively first n-type and first p-type drains together at a first junction that connects to the bit line. The second transistors connect respectively a second n-type and second p-type drains together at a second junction that connects to the inverse bit line.

Abstract: A method and system for providing a magnetic junction residing on a substrate and usable in a magnetic device are described. The magnetic junction includes a first pinned layer, a first nonmagnetic spacer layer having a first thickness, a free layer, a second nonmagnetic spacer layer having a second thickness greater than the first thickness, and a second pinned layer. The first nonmagnetic spacer layer resides between the pinned layer and the free layer. The first pinned layer resides between the free layer and the substrate. The second nonmagnetic spacer layer is between the free layer and the second pinned layer. Further, the magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro.

Abstract: The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, and a memory cell which is arranged on the semiconductor substrate and comprises a variable resistance element. The variable resistance element comprises a laminated structure including a phase-change element which has at least two different crystalline resistance states by varying a crystalline state, and a magnetoresistive element which has at least two different magnetization resistance states by varying a magnetization state, and applies or does not apply a magnetic field to the phase-change element in accordance with the magnetization state.

Abstract: Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.

Abstract: A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.

Abstract: Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum.

Abstract: Phase-change memory arrays, subarrays and chips, and systems and devices in which phase change memory is used, in which two reference columns are added on to hold complementary states for each wordline of data. The outputs from the cells in the two reference columns are combined (e.g. as a plain or weighted average) to provide a reference value for read discrimination of cell states in the other columns. This provides reference values which closely track resistance changes in corresponding ones of said words resulting from, e.g., drift and other time- and phase change material-dependent factors. One of the columns of reference cells can hold a checksum.

Abstract: Phase change memory arrays, subarrays, modules, and chips, as well as systems and devices in which phase change memory is used, wherein a reference corresponding to a pair of adjacent logical states (e.g., 0 and 1) can be generated by averaging outputs from a designated data-storing cell and a designated reference cell storing the logical complement to the logical state stored by the data-storing cell. By writing designated cells contemporaneously with words of cells that are configured to be written together, resulting references can closely track resistance changes in said words resulting from, e.g., drift and other time- and phase change material-dependent factors.