Patents Issued in March 11, 2014
  • Patent number: 8669540
    Abstract: An electrostatic clamp includes a heating block for heating a substrate, the heating block having a first surface disposed toward the substrate and a second surface opposite the first surface. A base is arranged to adjoin at least a portion of the second surface of the heating block. The adjoined base and heating block may mutually define an inner gap between a first portion of the heating block and the base. An outer gap is arranged concentric with the inner gap between a second portion of the heating block and the base, the inner and outer gaps being isolated from one another by a first sealing surface formed between the second surface of the heating block and the base.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: March 11, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Timothy J. Miller, Richard S. Muka, Julian G. Blake
  • Patent number: 8669541
    Abstract: Treatment planning methods are provided that determine the variability of relative biological effectiveness (RBE) along a beam line and calculate, among other things, what intensity of hadron beam such as a proton or a carbon ion beam should be applied to achieve a desired biological dose at treatment site of a patient afflicted with a medical condition. Typically, three or four RBE values at three or four corresponding spacially-dispersed intervals along the beam line are calculated. In one embodiment, two RBE values for the spread-out Bragg peak (SOBP) region of the treatment site; one for the proximal section and one for the declining distal section is calculated. A third and different RBE value may be determined for the distal edge region of the SOBP. A fourth value may also be calculated for a pre-SOBP region.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 11, 2014
    Assignee: Hampton University
    Inventors: Cythnia E. Keppel, Richard A. Britten, Vahagn R. Nazaryan
  • Patent number: 8669542
    Abstract: An extreme ultraviolet light source apparatus for supplying extreme ultraviolet light to a processing unit for performing processing by using the extreme ultraviolet light. The extreme ultraviolet light source apparatus includes: a chamber in which the extreme ultraviolet light to be supplied to the processing unit is generated; a collector mirror for collecting the extreme ultraviolet light generated in the chamber to output the extreme ultraviolet light to the processing unit; and an optical path connection module for defining a route of the extreme ultraviolet light between the chamber and the processing unit and isolating the route of the extreme ultraviolet light from outside.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: March 11, 2014
    Assignee: Gigaphoton Inc.
    Inventors: Yukio Watanabe, Osamu Wakabayashi, Miwa Igarashi
  • Patent number: 8669543
    Abstract: An extreme ultraviolet light generation system used with a laser apparatus may be provided, and the extreme ultraviolet light generation system may include: a chamber including at least one window for at least one laser beam and a target supply unit for supplying a target material into the chamber; and at least one polarization control unit, provided on a laser beam path, for controlling a polarization state of the at least one laser beam.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 11, 2014
    Assignee: Gigaphoton, Inc.
    Inventors: Tatsuya Yanagida, Osamu Wakabayashi
  • Patent number: 8669544
    Abstract: Amongst the candidates for very high efficiency solid state light sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group IIIA-nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. According to other embodiments of the invention self-organizing dot-within-a-dot nanowire and dot-within-a-dot-within-a-well nanowire structures are presented.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 11, 2014
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Zetian Mi, Kai Cui, Hieu Pham Trung Nguyen
  • Patent number: 8669545
    Abstract: A light emitting device includes an active layer including a quantum barrier and a quantum well, a first conductive type semiconductor layer disposed at one side of the active layer, and a second conductive type semiconductor layer disposed at the other side of the active layer, wherein the first conductive type semiconductor layer or the second conductive type semiconductor layer includes a main barrier layer, and the main barrier layer includes a plurality of sub barrier layers and a basal layer disposed between the plurality of sub barrier layers. The plurality of sub barrier layers includes a first section in which energy band gaps of the plurality of sub barrier layers are increased and a second section in which energy band gaps of the plurality of sub barrier layers are decreased.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yong Seon Song, Yong Tae Moon
  • Patent number: 8669546
    Abstract: A nitride group semiconductor light emitting device includes a substrate, n-type and p-type semiconductor layers, and an active region. The n-type and p-type semiconductor layers are formed on or above the substrate. The active region is interposed between the n-type and p-type semiconductor layers. The active region includes barrier layers that are included in a multiquantum well structure, and an end barrier layer that has a thickness greater than the barrier layer, and is arranged closest to the p-type semiconductor layer. The average thickness of the last two barrier layers that are arranged adjacent to the end barrier layer is smaller than the average thickness of the other barrier layers among the thicknesses of the barrier layers that are included in the multiquantum well structure.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 11, 2014
    Assignee: Nichia Corporation
    Inventor: Yasuhisa Kotani
  • Patent number: 8669547
    Abstract: There is provided an organic light-emitting diode luminaire. The luminaire includes a patterned first electrode, a second electrode, and an electroluminescent layer therebetween. The electroluminescent layer includes: a host material capable of electroluminescence having an emission color that is blue; a first electroluminescent dopant having an emission color that is green; and a second electroluminescent dopant having an emission color that is in the red/orange region. The additive mixing of all the emitted colors results in an overall emission of white light.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: March 11, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Daniel David Lecloux, Norman Herron, Vsevolod Rostovtsev
  • Patent number: 8669548
    Abstract: An organic light-emitting display apparatus includes a first insulating layer, a second insulating layer on the first insulating layer and including an unevenness portion, a third insulating layer on the second insulating layer, a pixel electrode on the third insulating layer, an opposite electrode facing the pixel electrode, and an organic emission layer between the pixel electrode and the opposite electrode; a thin film transistor including an active layer, a gate electrode, and source/drain electrodes connected to the active layer, the first insulating layer being between the active layer and the gate electrode and the second insulating layer being between the gate electrode, and the source/drain electrodes; and a capacitor including a lower electrode on a same layer as the gate electrode, a dielectric layer of a same material as the third insulating layer, and an upper electrode on a same layer as the pixel electrode.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: March 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Hwan Oh, Young-Jin Chang, Seong-Hyun Jin, Se-Hun Park, June-Woo Lee, Kwang-Hae Kim, Jong-Hyun Choi, Kwan-Wook Jung, Won-Kyu Lee, Jae-Beom Choi
  • Patent number: 8669549
    Abstract: A laminated body includes a lower electrode formed on a substrate and a basic insulating film which is formed above the lower electrode and covers the lower electrode on the substrate, in which the lower electrode has a film thickness reduction section in which the film thickness of the lower electrode in a portion which is not covered by the basic insulating film is smaller than the film thickness of the lower electrode in a portion which is covered by the basic insulating film in the lower electrode.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 11, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventor: Ryohei Matsubara
  • Patent number: 8669550
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8669551
    Abstract: A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: March 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-il Kim, Young-soo Park, I-hun Song, Chang-jung Kim, Jae-chul Park, Sang-wook Kim
  • Patent number: 8669552
    Abstract: The present invention generally relates to an offset electrode TFT and a method of its manufacture. The offset electrode TFT is a TFT in which one electrode, either the source or the drain, surrounds the other electrode. The gate electrode continues to be below both the source and the drain electrodes. By redesigning the TFT, less voltage is necessary to transfer the voltage from the source to the drain electrode as compared to traditional bottom gate TFTs or top gate TFTs. The offset electrode TFT structure is applicable not only to silicon based TFTs, but also to transparent TFTs that include metal oxides such as zinc oxide or IGZO and metal oxynitrides such as ZnON.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8669553
    Abstract: A thin-film transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, a channel layer, and a passivation layer. The channel layer has a first surface and an opposed second surface, where the first surface is disposed over at least a portion of the gate dielectric. The channel layer also has a first oxide composition including at least one predetermined cation. The passivation layer is disposed adjacent to at least a portion of the opposed second surface of the channel layer. The passivation layer has a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: March 11, 2014
    Assignees: Hewlett-Packard Development Company, L.P., Oregon State University
    Inventors: Chris Knutson, Rick Presley, John F. Wager, Douglas Keszler, Randy Hoffman
  • Patent number: 8669554
    Abstract: A fast recovery rectifier structure with the combination of Schottky structure to relieve the minority carriers during the forward bias condition for the further reduction of the reverse recovery time during switching in addition to the lifetime killer such as Pt, Au, and/or irradiation. This fast recovery rectifier uses unpolished substrates and thick impurity diffusion for low cost production. A reduced p-n junction structure with a heavily p-type doped thin film is provided to terminate and shorten the p-n junction space charge region. This reduced p-n junction with less total charge in the p-n junction to further improve the reverse recovery time. This reduced p-n junction can be used alone, with the traditional lifetime killer method, with the Schottky structure and/or with the epitaxial substrate.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: March 11, 2014
    Inventor: Ho-Yuan Yu
  • Patent number: 8669555
    Abstract: Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Masao Takahashi, Koji Takemura, Toshihiko Sakashita, Tadaaki Mimura
  • Patent number: 8669556
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. Further, a semiconductor device which has stable electric characteristics and high reliability is provided by using the oxide semiconductor film. An oxide semiconductor film includes a crystalline region, and the crystalline region includes a crystal in which an a-b plane is substantially parallel with a surface of the film and a c-axis is substantially perpendicular to the surface of the film; the oxide semiconductor film has stable electric conductivity and is more electrically stable with respect to irradiation with visible light, ultraviolet light, and the like. By using such an oxide semiconductor film for a transistor, a highly reliable semiconductor device having stable electric characteristics can be provided.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Patent number: 8669557
    Abstract: The present invention relates to a thin film transistor substrate and a method for fabricating the same which can reduce a number of steps.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 11, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Young Kwack, Mun Gi Park
  • Patent number: 8669558
    Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 11, 2014
    Assignee: AU Optronics Corp.
    Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang
  • Patent number: 8669559
    Abstract: Provided is an image display apparatus in which color breakup of a reflection image formed from reflected ambient light may be reduced to suppress the influence of an ambient environment. The image display apparatus includes multiple pixels. Each of the pixels includes a light-emitting layer and a structure layer having a refractive index distribution in an in-plane direction parallel to a screen of the image display apparatus, for extracting light generated from the light-emitting layer. The structure layer includes multiple structures formed of a first medium and a layer formed of a second medium having a refractive index different from a refractive index of the first medium. The multiple structures are non-periodically arranged in the layer. Reflected ambient light is reflected by the multiple structures formed of the first medium to have an overlap range to reduce color breakup of a reflection image formed from the reflected ambient light.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: March 11, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuya Nobayashi
  • Patent number: 8669560
    Abstract: Disclosed is a light-emitting device including: a support member; and a light-emitting structure on the support member, the light-emitting structure including a first semiconductor layer, at least one intermediate layer, an active layer and a second semiconductor layer, wherein the intermediate layer is on at least one of upper and lower regions of the active layer and comprises at least four layers, wherein the layers have different band gaps, and wherein, among the layers, a layer having the largest band gap contacts a layer having the smallest band gap. Based on this configuration, it is possible to reduce crystal defects and improve brightness of the light-emitting device through effective diffusion of current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Sanghyun Lee
  • Patent number: 8669561
    Abstract: A semiconductor device includes: a semiconductor substrate; a first conductivity type semiconductor layer that is formed on the substrate and is made of silicon carbide; an active area formed on a surface of the semiconductor layer; a first semiconductor area of a second conductivity type formed on the surface of the semiconductor layer to surround the active area; a second semiconductor area, provided to adjoin an outer side of the first semiconductor area on the surface of the semiconductor layer and surround the first semiconductor area, in which a second conductivity type impurity area having the same impurity concentration and the same depth as those of the first semiconductor area is formed in a mesh shape; a first electrode provided on the active area; and a second electrode provided on the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuo Hatakeyama
  • Patent number: 8669562
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Tsuchiya, Takashi Shinohe
  • Patent number: 8669563
    Abstract: Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire bond pad has an area less than the area of the first contact. A reflective structure is disposed between the first contact and the wire bond pad such that the reflective structure has substantially the same area as the wire bond pad. A second contact is provided opposite the active region from the first contact. The reflective structure may be disposed only between the first contact and the wire bond pad. Methods of fabricating such devices are also provided.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: March 11, 2014
    Assignee: Cree, Inc.
    Inventors: Kevin Haberern, Michael John Bergmann, Van Mieczkowski, David Todd Emerson
  • Patent number: 8669564
    Abstract: A light emitting device (10) comprises an elongate first body (12) of a semiconductor material. A transverse junction (18) is formed in the first body between a first n+-type region (12.1) of the first body and a second p-type region (12.2). A third p+-type region (12.3) is spaced from the first region by the second region. A second body (22) of an isolation material is provided immediately adjacent at least part of the second region to at least partially encapsulate the first body. A terminal arrangement (28) is connected to the first body and is arranged to reverse bias the junction (18) into a breakdown mode. The device is configured such that a depletion region associated with the junction (18) extends through the second region (12.2) and reaches the third region (12.3) before the junction (18) enters the breakdown mode.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: March 11, 2014
    Assignee: Insiava (Pty) Limited
    Inventor: Monuko Du Plessis
  • Patent number: 8669565
    Abstract: LED devices includes a lead frame having a reflector cup with a round bottom surface and a wall surface having a variable inclination with respect to the bottom surface and defining an opening at an upper end thereof. An LED is mounted on the bottom surface of the reflector cup, and an LED module includes first and second LED device that emit different colors. The first and second LED devices have substantially matched far field patterns in a first and second direction, where a first viewing angle in the first direction is less than about 99°.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: March 11, 2014
    Assignee: Cree Huizhou Solid State Lighting Company Limited
    Inventors: Chi Keung Chan, Zhi Kuan Zhang, Xiang Fei, Hao Liu, Ju Zuo Sheng, David Todd Emerson
  • Patent number: 8669567
    Abstract: A light-emitting device is disclosed. More particularly, the light-emitting device comprises a first substrate; a light-emitting element over the first substrate; a second substrate over the light-emitting element, wherein the second substrate contains a concave portion; a sealant between the first substrate and the second substrate; and a material having a water absorbing property is formed in the concave portion, wherein the material having the water absorbing property is provided so as not to overlap the light-emitting element, and so as to be spaced from the sealant.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Kawakami, Kaoru Tsuchiya, Takeshi Nishi, Yoshiharu Hirakata, Keiko Kida, Ayumi Sato, Shunpei Yamazaki
  • Patent number: 8669568
    Abstract: A light emitting device includes a light emitting unit and a submount. The light emitting unit has a plurality of light emitting diodes (LEDs), and the submount has a plurality of conductive contacts on a side thereof. The LEDs are coupled to the conductive contacts in various electrical connection manners, such that the LEDs are connected in series or/and in parallel.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 11, 2014
    Assignee: InterLight Optotech Corporation
    Inventor: Hwa Su
  • Patent number: 8669569
    Abstract: A method for fabricating light emitting diode packages includes: providing a light emitting diode wafer which has a plurality of light emitting diode chips, each of the light emitting diode chips including a semiconductor unit that has p-type and n-type electrode regions, and two electrodes; forming a light-transmissive insulating layer on the light emitting diode chips; forming a reflective metal layer on a portion of the light-transmissive insulating layer; forming a layer of insulating material on the light-transmissive insulating layer and the reflective metal layer, and performing exposing and developing treatments to form the layer of insulating material into a plurality of protective insulating structures; forming a conductor-receiving insulating layer on the light-transmissive insulating layer and the protective insulating structures; and performing a cutting process to obtain a plurality of light emitting diode packages each having at least one of the light emitting diode chips.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: March 11, 2014
    Inventors: Yu-Nung Shen, Tsung-Chi Wang
  • Patent number: 8669570
    Abstract: A light emitting assembly (10) includes a plurality of light emitting diodes (28) (L.E.D.s) serially aligned along a mounting surface (14) and a light shield (40) is disposed adjacent each L.E.D. An exterior surface of one light shield (40) is exposed to light emitting from an adjacent light shield (40). A non-reflective film (52) comprising a black color is painted over the exterior surface and a reflective material (54) is disposed over an interior surface of each light shield (40). The light shields (40) comprise sections (44) defined by a triangular shape joining at a ridge (48) and extending upwardly from the mounting surface (14) at an angle to define an opening for emitting light. The light shields (40) are spaced from the L.E.D.s at desired locations and angles to achieve full cutoff light emissions.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: March 11, 2014
    Assignee: Relume Technologies, Inc.
    Inventor: Peter A. Hochstein
  • Patent number: 8669571
    Abstract: A light distribution controller of a light-emitting device includes a first optical member formed of ZnO disposed over an LED interposing a transparent adhesive, and a second optical member which covers the first optical member. The first optical member includes a first concave portion having an opening in a regular hexagon shape whose area gradually increases. In the first concave portion, inner wall surfaces having inclined surfaces, each of whose bases is formed by one side of the hexagon of the opening shape, are formed. Outside of the first optical member, outer wall surfaces each having a trapezoidal shape are formed. The second optical member includes a second concave portion arranged so that light at an annular peak in the light distribution characteristic of the light traveled through the first optical member is totally reflected.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Akihiko Murai, Masahiro Kume, Akiko Nakamura, Tooru Aoyagi, Kiyoshi Fujihara
  • Patent number: 8669572
    Abstract: Adhesive-free assembly of the substrate and reflector components of a semiconductor die package is achieved by injection molding the reflector onto a surface of the substrate or by molding the reflector separate from the substrate and securing it in place on the substrate through deformation of a portion of the reflector. The reflector may be made reflective either by molding the reflector using a light scattering material or through the addition of a reflective element, such as a piece of foil material that is secured to the reflector. A variety of interchangeable reflective elements having different surface shapes, and thus different light reflecting properties, may be made.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: March 11, 2014
    Assignee: Cree, Inc.
    Inventors: Michael Leung, James Ibbetson
  • Patent number: 8669573
    Abstract: Methods of packaging a semiconductor light emitting device include providing a substrate having the semiconductor light emitting device on a front face thereof. A first optical element is formed from a first material on the front face proximate the semiconductor light emitting device but not covering the semiconductor light emitting device and a second optical element is formed from a second material, different from the first material, over the semiconductor light emitting device and the first optical element. Packaged semiconductor light emitting devices are also provided.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: March 11, 2014
    Assignee: Cree, Inc.
    Inventor: Nicholas W. Medendorp, Jr.
  • Patent number: 8669574
    Abstract: The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light-reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: March 11, 2014
    Assignee: GLO AB
    Inventors: Steven Konsek, Jonas Ohlsson, Yourii Martynov, Peter Hanberg
  • Patent number: 8669575
    Abstract: In a light emitting module 40, light wavelength conversion ceramic 58 converts the wavelength of the light emitted by a semiconductor light emitting element 52. The light wavelength conversion ceramic 58 is made so transparent that the light wavelength conversion ceramic 58 has 40 percent or more of the total light transmittance of the light with a wavelength within the conversion wavelength range. A reflective film 60 is provided on the surface of the light wavelength conversion ceramic 58 and narrows down the emission area of the light that has transmitted the light wavelength conversion ceramic 58 to an area smaller than the light emitting area of the semiconductor light emitting element 52. In the case, the reflective film 60 guides the light such that the light is emitted in the direction approximately parallel to the light emitting surface of the light emitting element 52.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: March 11, 2014
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Hisayoshi Daicho, Yasuaki Tsutsumi, Takaaki Komatsu, Shogo Sugimori, Yuji Higashi
  • Patent number: 8669576
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer formed in contact with the first semiconductor layer, and a third semiconductor layer of a second conductivity type formed in contact with the second semiconductor layer, the first semiconductor layer provided with a first semiconductor region at a given distance from an interface between the first semiconductor layer and the second semiconductor layer, and an impurity concentration of the first semiconductor region higher than an impurity concentration of the first semiconductor layer except where the first semiconductor region is formed.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Takahashi
  • Patent number: 8669577
    Abstract: A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first and second semiconductor layers, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a first reflection layer disposed on the second semiconductor layer. The first reflection layer includes at least a first layer having a first index of refraction and a second layer having a second index of refraction different from the first index of refraction. The first reflection layer is further disposed on a side surface of the second electrode and a portion of an upper surface of the second electrode.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: SungKyoon Kim, SungHo Choo, HyunSeoung Ju
  • Patent number: 8669578
    Abstract: A wavelength conversion particle 7 used for a wavelength conversion member 70 is provided with a moth-eye structure section 74 having a fine concavo-convex structure in the side of a surface of a fluorescent particle 71, and the fine concavo-convex structure is formed in fluorescent particle 71 itself. Wavelength conversion member 70 is formed by dispersing wave-length conversion particle(s) 7 into a translucent medium 73 having a smaller refraction index than fluorescent particle 71 of wavelength conver-sion particle 7. Wavelength conversion member 70 is further provided with an antireflection section 76 in the side of the surface of fluorescent particle 71. Antireflection section 76 comprises moth-eye structure section 74 and translucent medium 73 entered between taper-shaped fine projections 75 of moth-eye structure section 74.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Shinji Shibamoto, Keiichi Yamazaki, Shunpei Fujii, Tomokazu Kusunoki
  • Patent number: 8669579
    Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Hiroki Ohara, Makoto Hosoba, Junichiro Sakata, Shunichi Ito
  • Patent number: 8669580
    Abstract: The present invention provides a Scalable Heat Dissipating Microelectronic Integration Platform (SHDMIP) LED Package having excellent heat dissipation and protection to LED, thus extending the lifespan of the LED. The SHDMIP LED package comprises a dual lead frame assembly comprising bottom and top lead frame, protection and driver circuits conductively attached to the bottom lead frame and a LED conductively attached to the top lead frame. The bottom lead frame comprises heat sink pad for heat dissipation purpose. Plurality of SHDMIP LED packages of the present invention can be configured in a matrix or row, forming a SHDMIP LED array for various lighting solutions. A method to manufacture the SHDMIP LED array of the present invention is provided herein.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: March 11, 2014
    Assignee: PSI Technologies, Inc.
    Inventors: Thomas Joachim Werner Morsheim, Fernando Villon Capinig, Dandy Navarro Jaducana, Anthony Augusto Malon Galay
  • Patent number: 8669581
    Abstract: Provided is a light emitting device package, which includes a ceramic body, an ultraviolet light emitting diode, a support member, and a glass film. The ceramic body defines a cavity. The ultraviolet light emitting diode is disposed within the cavity. The support member is disposed on the body, and surrounds the cavity. The glass film is coupled to the support member, and covers the cavity. Since the light emitting device package includes the ceramic body to efficiently dissipate heat, and the glass film is directly attached to the ceramic body to decrease the number of components, thereby simplifying the manufacturing process thereof, and reducing the manufacturing costs thereof.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jung Su Jung, Byung Mok Kim, Yu Dong Kim, Gun Kyo Lee
  • Patent number: 8669582
    Abstract: Disclosed is a light emitting device a light transmissive substrate, a light emitting structure disposed on the light transmissive substrate, comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, a conductive layer disposed on the second conductive type semiconductor layer, a first electrode part disposed on the conductive layer, with at least predetermined region in contact with the first conductive type semiconductor layer, passing through the conductive layer, the second conductive type semiconductor layer and the active, and a first insulation layer disposed between the conductive layer and the first electrode part, between the second conductive type semiconductor layer and the first electrode part and between the active layer and the first electrode part.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Min Gyu Na, Sung Kyoon Kim, Myeong Soo Kim
  • Patent number: 8669583
    Abstract: A heat-curable silicone resin composition for sealing optical semiconductors including: component (A): 100 parts by mass of a silicon compound expressed by Formula (1) below; and component (B): from 0.001 to 10 parts by mass of a condensation catalyst. (R1SiO3/2)a((R2)2SiO2/2)b((R3)3SiO1/2)c(SiO4/2)d(XO1/2)e??(1) In this formula, R1, R2, and R3 are identical or differing monovalent organic groups, “X” is a hydrogen atom or a monovalent organic group, “a” is a positive number, “b” is 0 or a positive number, “c” is 0 or a positive number, “d” is 0 or a positive number, and “e” is 0 or a positive number; however “a” to “e” satisfy the following conditions: b/a is a number from 0 to 10, c/a is a number from 0 to 0.5, d/(a+b+c+d) is a number from 0 to 0.3, and e/(a+b+c+d) is a number from 0.01 to 1.5.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: March 11, 2014
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventors: Takeaki Saiki, Yoshihito Takei
  • Patent number: 8669584
    Abstract: A light emitting device, comprises a LED chip, and a case having an accommodating recession accommodating the LED chip, wherein the light emitting device emits light from an opening portion of the accommodating recession, the case is monolithically formed by injection molding of a resin composition preparing by mixing fine grains of specular reflection material and glass fibers as diffusion reflecting material as fillers therein, an inner surface of a side wall portion of the case works as a reflector that reflects the light emitted from the LED chip so that the light is output from the opening portion, and a thickness of the side wall portion is selected to be smaller than an average length of the glass fibers.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 11, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Makoto Sato, Satoshi Ota, Masakata Koseki
  • Patent number: 8669585
    Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×102° atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.
    Type: Grant
    Filed: September 1, 2012
    Date of Patent: March 11, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventors: Zhen Chen, Yi Fu
  • Patent number: 8669586
    Abstract: A light emitting device includes a first electrode, a first semiconductor layer, an active layer; a second semiconductor layer, and a second electrode. A current blocking layer is formed on a side surface of and has a width provided within the first semiconductor layer. The thickness and width of the current blocking layer is smaller than the thickness and width of the first semiconductor layer.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Sung Min Hwang, Hyun Kyong Cho
  • Patent number: 8669587
    Abstract: A vertical topology light emitting device comprises a support structure, a first adhesion layer, a second adhesion layer, a first metal layer, a second metal layer comprising a portion which directly contacts a GaN-based semiconductor structure, an interface layer, and a contact pad.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Myung Cheol Yoo
  • Patent number: 8669588
    Abstract: A unit cell for use in an imaging system may include an absorber layer of semiconductor material formed on a semiconductor substrate, at least one contact including semiconductor material formed on the semiconductor substrate and electrically coupled to the absorber layer, and a cap layer of semiconductor material formed on the semiconductor substrate and electrically coupled to and formed between the absorber layer and the at least one contact. The absorber layer may be configured to absorb incident photons such that the absorbed photons excite electrons in the absorber layer to generate a photocurrent. The at least one contact may be configured to conduct the photocurrent to one or more electrical components external to the unit cell. The cap layer may be configured to conduct the photocurrent between the absorber layer and the at least one contact.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: March 11, 2014
    Assignee: Raytheon Company
    Inventors: Edward Peter Gordon Smith, Gregory Mark Venzor, Eric J. Beuville
  • Patent number: 8669589
    Abstract: A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: March 11, 2014
    Assignee: Cree, Inc.
    Inventors: Yifeng Wu, Marcia Moore, Tim Wisleder, Primit Parikh
  • Patent number: 8669590
    Abstract: Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Errol Antonio C. Sanchez, Yi-Chiau Huang