Abstract: A semiconductor device having a substrate is disclosed. The substrate includes a first set of inner edges and a second set of inner edges cooperating with the first set of inner edges. The second set of inner edges is positioned outside the first set of inner edges with respect to a cavity formed by the first inner edges and the second inner edges by a pre-defined distance. The substrate further includes a layer within the cavity, including a dried liquid material formed from a liquid deposited within the cavity. The layer within the cavity is formed between the respective first inner edges and the second inner edges. The semiconductor device may be implemented in a display of an electronic device.

Abstract: A Plastic Leaded Chip Carrier (PLCC) package is disclosed. The PLCC package is configured to support a plurality of light sources. The light sources may be mounted on a mounting section of the PLCC package's lead frame and the mounting section of the lead frame may extend diagonally with respect to the housing of the lead frame.

Abstract: An approach is provided for a device and a method for an LED with a convex cover, which comprises multiple LED diodes compartmentalized to at least one group. Each group of LED diodes forms an electrical loop on a PCB, and has at least one first LED diode on a center region and at least two second LED diodes on a periphery region. Each second LED diode is connected to the first LED diode in series, and connected to the other second LED diode in parallel. The power of the first LED diode is higher than the second LED diode.

Abstract: A lighting device using an electroluminescent material, in which color mixing and dimming can be performed by a simple method, is provided. A lighting device including a first light-emitting element and a second light-emitting element which emits light having a wavelength longer than that of light emitted from the first light-emitting element and starts to emit light at a lower voltage than the first light-emitting element, is provided. The first light-emitting element and the second light-emitting element are connected in parallel, whereby a mixed color of emission colors of the first light-emitting element and the second light-emitting element is controlled by a voltage applied to the first light-emitting element and the second light-emitting element.

Abstract: The present invention provides a color filter substrate manufacturing method which can prevent the occurrence of color mixing between adjacent pixels despite of the use of an inkjet method, and which are unlikely to cause flicker when used for displays such as televisions.

Abstract: An illumination component package includes a substrate, at least one illumination component, a dam and an encapsulating glue. The illumination component is mounted on the substrate. The dam surrounds the illumination component to form a accommodating space. The inner wall of the dam includes a plurality of glue adhering microstructures. The encapsulating glue is filled in the accommodating space.

Abstract: A luminescence device used in a backlight unit for lighting or displaying may include a substrate having a first electrode and a second electrode, and an LED chip disposed on the first electrode. A dam is disposed on the substrate. The dam is disposed spaced from the LED chip, and the substrate comprises a direct copper bonding (DCB) substrate including a first copper layer and a second copper layer. The first electrode and the second electrode include respectively a metal film which fills a void of the surfaces thereof.

Abstract: A phosphor adhesive sheet includes a phosphor layer containing a phosphor and an adhesive layer laminated on one surface in a thickness direction of the phosphor layer. The adhesive layer is formed from a silicone pressure-sensitive adhesive composition. A percentage of the peel strength of the phosphor adhesive sheet is 30% or more.

Abstract: A phosphor layer attaching kit includes a phosphor layer and a silicone pressure-sensitive adhesion composition for attaching the phosphor layer to an optical semiconductor element or an optical semiconductor element package. A percentage of the peel strength of the silicone pressure-sensitive adhesion composition is 30% or more.

Abstract: An encapsulating sheet-covered semiconductor element includes a semiconductor element having one surface in contact with a board and the other surface disposed at the other side of the one surface and an encapsulating sheet covering at least the other surface of the semiconductor element. The encapsulating sheet includes an exposed surface that is, when projected from one side toward the other side, not included in the one surface of the semiconductor element and exposed from the one surface and the exposed surface has the other side portion that is positioned toward the other side with respect to the one surface of the semiconductor element.

Abstract: A method for increasing the luminous efficacy of a white light emitting diode (WLED), comprising introducing optically functional interfaces between an LED die and a phosphor, and between the phosphor and an outer medium, wherein at least one of the interfaces between the phosphor and the LED die provides a reflectance for light emitted by the phosphor away from the outer medium and a transmittance for light emitted by the LED die. Thus, a WLED may comprise a first material which surrounds an LED die, a phosphor layer, and at least one additional layer or material which is transparent for direct LED emission and reflective for the phosphor emission, placed between the phosphor layer and the first material which surrounds the LED die.

Abstract: A semiconductor light emitting device, includes: a stacked structural unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided therebetween; and an electrode including a first and second metal layers, the first metal layer including silver or silver alloy and being provided on a side of the second semiconductor layer opposite to the light emitting layer, the second metal layer including at least one element selected from gold, platinum, palladium, rhodium, iridium, ruthenium, and osmium and being provided on a side of the first metal layer opposite to the second semiconductor layer. A concentration of the element in a region including an interface between the first and second semiconductor layers is higher than that of the element in a region of the first metal layer distal to the interface.

Abstract: A Light emitting diode (LED) chip includes a substrate, an N-type semiconductor layer, a luminous layer, a P-type semiconductor layer, an N-type electrode layer and a P-type electrode layer. The N-type semiconductor layer is mounted on the substrate. The luminous layer is mounted on the N-type semiconductor layer. The P-type semiconductor layer is mounted on the luminous layer. The N-type electrode layer is mounted on the N-type semiconductor layer. The P-type electrode layer is mounted on the P-type semiconductor layer, and includes a plurality of enclosed circuit patterns. These enclosed circuit patterns respectively encompass different parts of the N-type electrode layer.

Abstract: A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode. The second electrode includes a treated patterned carbon nanotube film. The treated patterned carbon nanotube film includes at least two carbon nanotube linear units spaced from each other; and carbon nanotube groups spaced from each other. The carbon nanotube groups are located between the at least two carbon nanotube linear units, and combined with the at least two carbon nanotube linear units.

Abstract: A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface.

Abstract: A light emitting diode includes a substrate consisting two separated parts with a gap therebetween. A first electrical connecting portion is fixed to one of the two separated parts of the substrate and adjacent to the gap. A second electrical connecting portion is fixed to the other one of the two separated parts of the substrate and adjacent to the gap. An LED chip is mounted on the substrate and electrically connected to the first and second electrical connecting portions. An encapsulation covers the LED chip and fills in at least a part of the gap to connect the two separated parts of the substrate together.

Abstract: A method of forming a current diffusion layer is provided that comprises providing an epitaxial wafer. The method further comprises depositing ITO source material on the epitaxial wafer to form a base ITO layer by a direct current electron gun and depositing ZnO source material, during simultaneous deposition of the ITO source material, on the base ITO layer to form a ZnO doped ITO layer by a pulse current electron gun. The ZnO source material is deposited at a deposition rate higher than the rate at which the ITO source material is deposited. Generation and termination of current may be controlled by adjusting a duty cycle of pulse current provided by the pulse current electron gun and result in discontinuous deposition of the ZnO source material. The method further comprises depositing the ITO source material on the ZnO doped ITO layer to cover the ZnO doped ITO layer and form a finished ITO layer.

Abstract: A light emitting device includes a package constituted by a molded article having a light emitting face, a bottom face, and a rear face, and a pair of leads partially embedded in the molded article, protrude from the bottom face, and have ends that bend toward either the light emitting face or the rear face. The molded article has a front protruding part that protrudes from the bottom face and includes a surface continuous with the light emitting face, the front protruding part being spaced apart from the rear face, and a rear protruding part that protrudes from the bottom face and includes a surface continuous with the rear face, the rear protruding part being spaced apart from the light emitting face, between the leads on the bottom face, the front protruding part being spaced apart from the rear protruding part.

Abstract: An encapsulated structure of a light-emitting device, an encapsulating process thereof, and a display device comprising said encapsulated structure. The encapsulated structure of the light-emitting device comprises: a light-emitting device; and a protective layer of a sulfonate salt formed on a top electrode of the light-emitting device, the sulfonate salt having the following structure: wherein the cation X+ is Li+, Na+ or K+; and R is a substituent selected from the group consisting of unsubstituted alkyl groups having more than 5 carbon atoms, substituted alkyl groups having more than 5 carbon atoms, and alkoxyl groups having more than 5 carbon atoms.

Abstract: Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide-base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.

Abstract: A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p+-type diffusion region, a p?-type region, and an anode electrode. The p?-type region is formed as a region of relatively high electrical resistance sandwiched between the p+-type diffusion regions.

Abstract: Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more.

Abstract: According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer.

Abstract: An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.

Abstract: A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons.

Abstract: Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.

Abstract: An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output.

Abstract: A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region.

Abstract: A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract: A semiconductor device including: a substrate having a channel region and first and second recesses disposed on opposite sides of the channel region; a gate insulating layer disposed on the channel region; a gate structure disposed on the gate insulating layer; and a source region disposed in the first recess and a drain region disposed in the second recess, wherein the source region includes a first layer disposed on a surface of the first recess and a second layer disposed on the first layer and the drain region includes a third layer disposed on a surface of the second recess and a fourth layer disposed on the third layer; and a distance between the gate structure and the second layer of the source region is greater or less than a distance between the gate structure and the fourth layer of the drain region.

Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Abstract: A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high-voltage surface region during operation of the device into multiple much smaller spikes.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region.

Abstract: The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET1, FET2), which has a first electrode, a second electrode, a control electrode, and a channel between the first electrode and the second electrode, and comprising an antenna structure. An electrode is connected to the antenna structure such that an electromagnetic signal which lies in the THz-frequency range and which is received by the antenna structure (1) can be fed into the channel between electrodes and the control electrode is connected to an electrode via a capacitor and/or the control electrode and the first electrode or the control electrode and the second electrode have an intrinsic capacitor such that no AC voltage drop occurs between the control electrode and the first electrode or the second electrode.

Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Abstract: A solid-state imaging device includes a photoelectric converting portion including a first semiconductor region capable of accumulating a signal charge, a second semiconductor region of the same conductivity type as the first semiconductor region, a gate electrode provided between the first and second semiconductor regions, and an insulating layer provided on the first semiconductor region, the second semiconductor region, and the gate electrode. The solid-state imaging device further includes a first light-shielding portion including a metal portion provided in an opening or a trench of the insulating layer between the first and second semiconductor regions, and a second light-shielding portion including a metal portion provided on the insulating layer on the second semiconductor region.

Abstract: A fluorocarbon coating comprises an amorphous structure with CF2 bonds present in an atomic percentage of at least about 15%, and having a refractive index of less than about 1.4. The fluorocarbon coating can be deposited on a substrate by placing the substrate in a process zone comprising a pair of process electrodes, introducing a deposition gas comprising a fluorocarbon gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes.

Abstract: In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer.

Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.

Abstract: A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate.

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract: A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (VS) and a load current to the substrate, and a second supply terminal operably provided with a second supply potential. A first vertical transistor is integrated in the semiconductor chip and electrically coupled between the supply terminal and an output terminal. The first vertical transistor is configured to provide a current path for the load current to the output terminal in accordance with a control signal, which is provided to a gate electrode of the first vertical transistor.

Abstract: A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall.

Abstract: A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.

Abstract: In a transistor including a trench gate, a gate contact hole for connecting a gate electrode and a gate wiring to each other is provided on a trench. In a transistor in which the trench gate is formed in a grid pattern and a plurality of source regions are surrounded by the trench gate, the gate contact hole is formed at an intersection portion of the trench gate.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.