Patents Issued in April 3, 2014
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Publication number: 20140091439Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: APPLE INC.Inventors: Shawn X. ARNOLD, Matthew E. LAST
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Publication number: 20140091440Abstract: Electronic assemblies and their manufacture are described. One assembly includes a coreless substrate comprising a plurality of dielectric layers and electrically conductive pathways, the coreless substrate including a first side and a second side opposite the first side. The assembly includes a first die embedded in the coreless substrate, the first die comprising an RF die, the first die positioned in a dielectric layer that extends to the first side of the coreless substrate. The assembly includes a second die positioned on first side, the second die positioned on the first die. In another aspect, a molding material may be positioned on the die side, wherein the first die and the second die are covered by the molding material. In another aspect, an electrical shielding layer may be positioned over the first side. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2012Publication date: April 3, 2014Inventors: Vijay K. NAIR, John S. GUZEK, Johanna M. SWAN
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Publication number: 20140091441Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.Type: ApplicationFiled: November 27, 2013Publication date: April 3, 2014Applicant: XINTEC INC.Inventors: Yao-Hsiang CHEN, Tsang-Yu LIU, Yen-Shih HO, Shu-Ming CHANG
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Publication number: 20140091442Abstract: An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Bok Eng Cheah, Shanggar Periaman, Kooi Chi Ooi
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Publication number: 20140091443Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.Type: ApplicationFiled: September 19, 2013Publication date: April 3, 2014Applicants: STMicroelectronics Pte Ltd, STMicroelectronics (Malta) LtdInventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
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Publication number: 20140091444Abstract: A semiconductor unit includes a base, an insulating substrate bonded to the base, a conductive plate made of a metal of poor solderability, a semiconductor device mounted to the insulating substrate through the conductive plate, and a metal plate interposed between the conductive plate and the semiconductor device and made of a metal of good solderability as compared to the metal used for the conductive plate. The base, the insulating substrate, the conductive plate and the metal plate are brazed together, and the semiconductor device is soldered to the metal plate.Type: ApplicationFiled: September 20, 2013Publication date: April 3, 2014Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Shogo MORI, Yuri OTOBE, Naoki KATO, Shinsuke NISHI
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Publication number: 20140091445Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Weng Hong Teh, Deepak Kulkarni, Chia-Pin Chiu, Tannaz Harirchian, John S. Guzek
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Publication number: 20140091446Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Yan Xun Xue, Yueh-Se Ho, Yongping Ding
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Publication number: 20140091447Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.Type: ApplicationFiled: September 11, 2013Publication date: April 3, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yutaka ONOZUKA, Hiroshi Yamada, Kazuhiko Itaya
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Publication number: 20140091448Abstract: There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle.Type: ApplicationFiled: September 27, 2013Publication date: April 3, 2014Applicant: Conexant Systems, Inc.Inventors: Robert W. Warren, Hyun Jane Lee, Nic Rossi
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Publication number: 20140091449Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a U-phase output node situated on a first leadframe island of a leadframe, a V-phase output node situated on a second leadframe island of said leadframe, and a W-phase output node situated on a W-phase die pad of said leadframe. The first leadframe island can be on a first leadframe strip of the leadframe, where the first leadframe strip is connected to a U-phase die pad of the leadframe. The second leadframe island can be on a second leadframe strip of the leadframe, where the second leadframe strip is connected to a V-phase die pad of the leadframe. A first W-phase power switch is situated on the W-phase die pad. Furthermore, at least one wirebond is connected to the W-phase die pad and to a source of a second W-phase power switch. The W-phase die pad can be a W-phase output terminal of the PQFN package.Type: ApplicationFiled: December 10, 2013Publication date: April 3, 2014Applicant: International Rectifier CorporationInventors: Dean Fernando, Roel Barbosa
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Publication number: 20140091450Abstract: A semiconductor housing includes a front side with a semiconductor chip and a first metallization on a substrate, and a rear side with a second metallization. The rear side is situated opposite the front side of the semiconductor housing. The semiconductor housing further includes a first compensation layer applied on the front side of the semiconductor housing.Type: ApplicationFiled: September 24, 2013Publication date: April 3, 2014Inventors: Frank Pueschner, Juergen Hoegerl, Peter Scherl, Thomas Spoettl
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Publication number: 20140091451Abstract: A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.Type: ApplicationFiled: September 20, 2013Publication date: April 3, 2014Applicant: STMicroelectronics (Crolles 2) SASInventors: Philippe Delpech, Eric Sabouret, Sebastien Gallois-Garreignot
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Publication number: 20140091452Abstract: A semiconductor module is provided which includes a semiconductor unit which is made by a resin mold. The resin mold has formed therein a coolant path through which a coolant flows to cool a semiconductor chip embedded in the resin mold. The resin mold also includes heat spreaders, and electric terminals embedded therein. Each of the heat spreaders has a fin heat sink exposed to the flow of the coolant. The fin heat sink is welded to a surface of each of the heat spreaders through an insulator, thus minimizing an electrical leakage from the heat spreader to the coolant.Type: ApplicationFiled: November 4, 2013Publication date: April 3, 2014Applicant: DENSO CORPORATIONInventors: Chikage Katou, Hiroaki Arai, Yoshiyuki Yamauchi, Yasuou Yamazaki, Naoki Sugimoto, Yasuyuki Sakai
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Publication number: 20140091453Abstract: A cooling device includes a base and a plurality of radiator fins. The base includes an exterior, an interior, an inlet, and an outlet. A heat generation element is connected to the exterior of the base. The radiator fins are located near the heat generation element in the interior of the base. The radiator fins are arranged from the inlet to the outlet. Each radiator fin has a sidewise cross-section with a dimension in a flow direction of the cooling medium and a dimension in a lateral direction orthogonal to the flow direction of the cooling medium. The dimension in the flow direction is longer than the dimension in the lateral direction. The radiator fins are separated from one another by a predetermined distance in the lateral direction.Type: ApplicationFiled: September 27, 2013Publication date: April 3, 2014Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Shogo MORI, Yuri OTOBE, Naoki KATO, Shinsuke NISHI, Tomoya HIRANO, Seiji MATSUSHIMA
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Publication number: 20140091454Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Kang Chen, Yu Gu
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Publication number: 20140091455Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Thomas J. Strothmann, Damien M. Pricolo, Il Kwon Shim, Yaojioan Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Publication number: 20140091456Abstract: Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Ameya LIMAYE, Richard J. HARRIES, Sandeep B. SANE
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Publication number: 20140091457Abstract: An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the substrate surface includes the solder extending a first distance outward therefrom. A second of the bonding pads in a second location on the substrate surface includes the solder extending a second distance outward therefrom. The first distance is different than the second distance. Other embodiments are described and claimed.Type: ApplicationFiled: September 29, 2012Publication date: April 3, 2014Inventors: Hongjin JIANG, Arun Kumar C. NALLANI, Wei TAN
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Publication number: 20140091458Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.Type: ApplicationFiled: September 9, 2013Publication date: April 3, 2014Applicant: NXP B.V.Inventors: Leonardus Antonius Elisabeth VAN GEMERT, Tonny KAMPHUIS, Hartmut BUENNING, Christian ZENZ
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Publication number: 20140091459Abstract: A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.Type: ApplicationFiled: October 14, 2013Publication date: April 3, 2014Applicant: Invensas CorporationInventor: Masamichi Ishihara
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Publication number: 20140091460Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.Type: ApplicationFiled: December 3, 2013Publication date: April 3, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-Sun LEE, Jung-Hwan KIM, Tae-Hong KIM, Hyun-Jung SONG, Sun-Pil YOUN
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Publication number: 20140091461Abstract: A die cap for use with flip chip packages, flip chip packages using a die cap, and a method for manufacturing flip chip packages with a die cap are provided in the invention. A die cap encases the die of flip chip packages about its top and sides for constraining the thermal deformation of the die during temperature change. The CTE (coefficient of thermal expansion) mismatch between the die and substrate of flip chip packages is the root cause for warpage and reliability issues. The current inventive concept is to reduce the CTE mismatch by using a die cap to constrain the thermal deformation of the die. When a die cap with high CTE and high modulus is used, the die with the die cap has a relatively high overall CTE, reducing the CTE mismatch. As a result, the warpage and reliability of flip chip packages are improved.Type: ApplicationFiled: September 30, 2012Publication date: April 3, 2014Inventor: Yuci Shen
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Publication number: 20140091462Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.Type: ApplicationFiled: December 28, 2012Publication date: April 3, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventor: SILICONWARE PRECISION INDUSTRIES CO., LTD.
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Publication number: 20140091463Abstract: According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.Type: ApplicationFiled: July 16, 2013Publication date: April 3, 2014Inventors: Hae-jung YU, Hak-kyoon BYUN, Kyung-tae NA, Seung-hun HAN, Tae-sung PARK, Choong-bin YIM
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Publication number: 20140091464Abstract: The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which includes first wiring and second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other, and the first wiring and the second wiring being fixed at a mutually different potential, an uppermost interlayer film disposed on the lower layer wiring pattern, a titanium nitride layer disposed on the uppermost interlayer film so as to cover the first wiring and the second wiring, and the titanium nitride having the thickness of 800 ? or more, and a pad metal disposed on the titanium nitride layer.Type: ApplicationFiled: September 25, 2013Publication date: April 3, 2014Applicant: ROHM CO., LTD.Inventor: Motoharu HAGA
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Publication number: 20140091465Abstract: A method of assembling semiconductor devices includes dispensing a metal paste including metal particles in a solvent onto a bonding area of a plurality of metal terminals of a leadframe. The dispensing provides a varying thickness over the bonding area. The solvent is evaporated to form a sloped metal coating including a first sloped top face and a second sloped top face. The first sloped top face is closer to the die pad compared to the second sloped top face, the second sloped top face increases in coating thickness with decreasing distance to the die pad, and the first sloped top face decreases in coating thickness with decreasing distance to the die pad. A bottom side of semiconductor die including a plurality of top side bond pads is attached to the die pad. Bond wires are connected between the bond pads and the second sloped top faces.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: KAZUNORI HAYATA, MASAHIKO GOTO, SHOHTA UJIIE
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Publication number: 20140091466Abstract: A silicon structure is fabricated determining a pattern for wire trenches and air gaps. The wire trenches are created, and certain trenches are used as air gaps. The remaining wire trenches are used for metallization of inter connecting wires.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventor: Marc Van Veenhuizen
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Publication number: 20140091467Abstract: Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Christopher J. Jezewski, Alan M. Meyers, Kanwal Jit Singh, Tejaswik K. Indukuri, James S. Clarke, Florian Gstrein
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Publication number: 20140091468Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.Type: ApplicationFiled: December 3, 2013Publication date: April 3, 2014Applicant: Renesas Electronics CorporationInventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
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Publication number: 20140091469Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Vinodhkumar Raghunathan, Ebrahim Andideh
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Publication number: 20140091470Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Sandeep B. Sane, Shandar Ganapathysubramanian, Jorge Sanchez, Leonel R. Arana, Eric J. Li, Nitin A. Deshpande, Jiraporn Seangatith, Poh Chieh Benny Poon
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Publication number: 20140091471Abstract: A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
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Publication number: 20140091472Abstract: A semiconductor element includes a plurality of electrodes on a main surface, a sealing resin covering at least a part of a side surface of the semiconductor element, and a first insulating layer formed on the main surface of the semiconductor element, a part of the side surface of the semiconductor element, and the sealing resin. The first insulating layer has first openings formed therein to allow the plural electrodes on the main surface to be exposed through the first openings, and a fillet provided on a part of the side surface. The semiconductor element further includes a wiring layer formed in the first openings in such a manner as to be electrically connected to the plural electrodes, and also formed on the first insulating layer, and a second insulating layer having second openings formed on the first insulating layer and the wiring layer.Type: ApplicationFiled: September 2, 2013Publication date: April 3, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kyoko HONMA, Kazuo SHIMOKAWA
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Publication number: 20140091473Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jing-Cheng LEN, Shang-Yun HOU
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Publication number: 20140091474Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20140091475Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventor: DOUGLAS M. REBER
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Publication number: 20140091476Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Paul A. Nyhus, Swaninathan Sivakumar
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Publication number: 20140091477Abstract: A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsu Wu, Shih-Kang Fu, Hsin-Chieh Yao, Chia-Min Lin, Hsiang-Huan Lee, Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue
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Publication number: 20140091478Abstract: To provide a semiconductor device having a high efficiency of arranging a TSV, there is provided a semiconductor device which is stacked with a semiconductor chip, and in which the semiconductor chips contiguous each other are electrically connected by plural TSVs, the semiconductor chip includes a core circuit and plural IO circuits arranged at a surrounding thereof, the TSV is arranged in the core circuit, and a pitch of arranging the TSVs is an integer-told of a ceil pitch of a library configuring the core circuit.Type: ApplicationFiled: October 1, 2013Publication date: April 3, 2014Inventors: Futoshi Furuta, Kenichi Osada
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Publication number: 20140091479Abstract: A semiconductor chip 109 is mounted on a substrate 100, first wire group 120 and a second wire group 118 having a wire length shorter than the first wire group are provided so as to connect the substrate 100 and the semiconductor chip 109 to each other, and a sealing resin 307 is injected from the first wire group 120 toward the second wire group 118 so as to form a sealer 401 covering the semiconductor chip 109, the first wire group 120, and the second wire group 118.Type: ApplicationFiled: December 3, 2013Publication date: April 3, 2014Applicant: Elpida Memory, Inc.Inventor: Naohiro HANDA
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Publication number: 20140091480Abstract: The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.Type: ApplicationFiled: December 3, 2013Publication date: April 3, 2014Inventors: Naohide TAKAMOTO, Takeshi MATSUMURA
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Publication number: 20140091481Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.Type: ApplicationFiled: December 11, 2013Publication date: April 3, 2014Applicant: MediaTek Inc.Inventors: Tzu-Hung LIN, Ching-Liou HUANG, Thomas Matthew GREGORICH
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Publication number: 20140091482Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.Type: ApplicationFiled: March 15, 2013Publication date: April 3, 2014Applicant: STATS CHIPPAC, LTD.Inventors: Yaojian Lin, Heinz-Peter Wirtz, Seung Wook Yoon, Pandi C. Marimuthu
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Publication number: 20140091483Abstract: A method of manufacturing a semiconductor apparatus includes: a charging step of charging the thermosetting resin in excess of an amount necessary for forming the sealing layer to fill the inside of the first cavity with the thermosetting resin and discharging an excess of the thermosetting resin from the first cavity; an integrating step of integrating the substrate on which the semiconductor device is mounted, the substrate on which no semiconductor device is mounted and the sealing layer by molding the thermosetting resin while pressurizing the upper mold and the lower mold; and a dicing step of extracting the integrated substrates from the molding mold and dicing the integrated substrates to obtain an individual semiconductor apparatus.Type: ApplicationFiled: August 12, 2013Publication date: April 3, 2014Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Hideki AKIBA, Toshio SHIOBARA, Susumu SEKIGUCHI
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Publication number: 20140091484Abstract: A bubble generator includes a housing engaged in a receptacle, and a casing engaged into the housing and having an outer peripheral fence and a bottom plate, and having a bulge extended upwardly from the bottom plate for forming an inner peripheral channel between the bulge and the peripheral fence, and having a passage formed in the peripheral fence and communicating with the inner peripheral channel of the casing for allowing a fluid to flow into the inner peripheral channel of the casing and to flow out through the passage of the casing and to flow into the compartment of the housing, and the casing includes a number of projections extended from the bulge for agitating the fluid and for generating air bubbles in the fluid.Type: ApplicationFiled: October 3, 2012Publication date: April 3, 2014Inventor: Shih Tang LIU
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Publication number: 20140091485Abstract: An improved spray nozzle assembly for use in a steam desuperheating device that is adapted to spray cooling water into a flow of superheated steam. The nozzle assembly is of simple construction with relatively few components, and thus requires a minimal amount of maintenance. In addition, the nozzle assembly is specifically configured to, among other things, prevent thermal shock to prescribed internal structural components thereof, to prevent “sticking” of a valve element thereof, and to create a substantially uniformly distributed spray of cooling water for spraying into a flow of superheated steam in order to reduce the temperature of the steam.Type: ApplicationFiled: October 3, 2012Publication date: April 3, 2014Inventors: Daniel Allen Lee Watson, Raymond Richard Newton, Stephen Gerald Freitas, Kevin Naziri
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Publication number: 20140091486Abstract: An improved spray nozzle assembly for use in a steam desuperheating device that is adapted to spray cooling water into a flow of superheated steam. The nozzle assembly is of simple construction with relatively few components, and thus requires a minimal amount of maintenance. In addition, the nozzle assembly is specifically configured to, among other things, prevent thermal shock to prescribed internal structural components thereof, to prevent “sticking” of a valve element thereof, and to create a substantially uniformly distributed spray of cooling water for spraying into a flow of superheated steam in order to reduce the temperature of the steam.Type: ApplicationFiled: September 30, 2013Publication date: April 3, 2014Applicant: Control Components, Inc.Inventors: Daniel Allen Lee Watson, Raymond Richard Newton, Stephen Gerald Freitas, Kevin Naziri
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Publication number: 20140091487Abstract: A dispensing system for dispensing a material is disclosed that includes a housing for receipt of a dispenser holding a material. A fan is disposed within the housing. Upon activation, the fan draws air into the housing and diffuses the material charged air from the housing with a substantially 360 degree dispersal pattern.Type: ApplicationFiled: October 2, 2012Publication date: April 3, 2014Inventor: David C. Belongia
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Publication number: 20140091488Abstract: This microstructure forming mold forms a concavoconvex reflection preventing part on a concave lens surface of a lens main body including the concave lens surface with curvature. The reflection preventing part is formed using a surface processing device including: a molding surface part that transfers the reflection preventing part; a base body part that supports the molding surface part in a bendable manner; and a cavity portion, an annular cavity portion, and a liquid supply unit that deform the base body part to bend the molding surface part.Type: ApplicationFiled: December 6, 2013Publication date: April 3, 2014Applicant: Olympus CorporationInventor: MOTOAKI OZAKI