Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.

Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: A semiconductor device comprises a thin film transistor provided over a substrate having an insulating surface, and an electrode penetrating the substrate. The thin film transistor is provided between a first structural body and a second structural body, which has a higher rigidity than the first structural body, which serve as protectors because the structural bodies have resistance to a pressing force such as a tip of a pen or bending stress applied from outside so malfunction due to the pressing force and the bending stress can be prevented.

Abstract: A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.

Abstract: The present invention provides a circuit board having a reduced wiring area in a circuit portion and therefore suitably used for reduction in a display region of a display device, and further provides a display device including such a circuit board.

Abstract: A thin-film transistor including an oxide semiconductor layer is disclosed. The oxide semiconductor layer includes a first area, a second area and a third area forming a well-type potential in the film-thickness direction. The first area forms a well of the well-type potential and has a first electron affinity. The second area is disposed nearer to the gate electrode than the first area and has a second electron affinity smaller than the first electron affinity. The third area is disposed farther from the gate electrode than the first area and has a third electron affinity smaller than the first electron affinity. At least an oxygen concentration at the third area is lower than an oxygen concentration at the first area.

Abstract: According to one embodiment, a flat panel display includes a first mounting portion including a first input pad and a first output pad, a second mounting portion including a second input pad and a second output pad, a first common terminal and a second common terminal, which have a common potential, and a guard ring wiring which is formed in a manner to extend from the first common terminal, to pass between the first input pad and the first output pad of the first mounting portion, to pass between the second input pad and the second output pad of the second mounting portion, and to reach the second common terminal, the guard ring wiring including a first resistor element of a first resistance value and a second resistor element of a second resistance value which is higher than the first resistance value.

Abstract: An organic light-emitting display device in which a pixel electrode is formed by extending from source and drain electrodes, a capacitor including a thin upper capacitor electrode formed below the pixel electrode and constituting a metal-insulator-metal (MIM) CAP structure, thereby simplifying manufacturing processes, increasing an aperture ratio, and improving a voltage design margin.

Abstract: A semiconductor element includes: an organic semiconductor layer; an electrode disposed on the organic semiconductor layer so as to be in contact with the organic semiconductor layer; and a wiring layer formed separately from the electrode and electrically connected to the electrode.

Abstract: A display unit includes, on a substrate: a plurality of light emitting devices in which a first electrode, an organic layer including a light emitting layer, and a second electrode are respectively and sequentially layered; and a black insulating layer separating the organic layer for the every light emitting device.

Abstract: Present embodiments provide a display apparatus including a substrate; a sealing substrate facing the substrate; a display unit between the substrate and the sealing substrate; a first sealing member between the substrate and the sealing substrate to be spaced apart from the display unit, so as to bond the substrate and the sealing substrate to each other; a second sealing member between the substrate and the sealing substrate to be spaced apart from the display unit and the first sealing member, so as to bond the substrate and the sealing substrate to each other; and a light pattern layer on a surface of the sealing substrate opposite to a surface facing the display unit, so as to adjust light intensity transmitted through the sealing substrate. The light pattern layer includes a first pattern corresponding to the first sealing member and a second pattern corresponding to the second sealing member.

Abstract: The disclosed technology is in connection with an array substrate of a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing the same, and the array substrate comprises: a base substrate; a gate line and a data line forming on the base substrate and defining a pixel region, a pixel electrode, a thin film transistor and a common electrode are formed in the pixel region; a black matrix made of conductive thin film material, the black matrix is electrically connected with the common electrode.

Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.

Abstract: A composite substrate for laser devices is disclosed having improved wave guiding properties, improved lattice matching, improved thermal expansion matching, and improved thermal conductivity. The composite substrate has an intermediate layer formed on a support substrate, and a seed layer formed on the intermediate layer. An active device layer is grown or attached to the seed layer, or to a light confinement layer on the seed layer. The intermediate layer may be formed directly on the support layer, or may be formed by thinning an attached wafer of the intermediate material, which is then thinned to a desired thickness.

Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: Disclosed is an LED package. The LED package includes a package body, a first frame and a second frame on the package body and a light emitting device chip on the first frame. The first frame is separated from the second frame, and the first frame includes a bottom frame on the package body and at least two sidewall frames extending from the bottom frame and inclined with respect to the bottom frame.

Abstract: A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer.

Abstract: Provided is a light-emitting element including a semiconductor substrate, an island structure formed on the semiconductor substrate and including at least a current confining layer and p-type and n-type semiconductor layers, a light-emitting thyristor formed in the island structure and having a pnpn structure, and a shift thyristor formed in the island structure and having a pnpn structure, wherein the island structure includes a first side surface having a first depth such that the first side surface does not reach the current confining layer in a formation region of the shift thyristor and a second side surface having a second depth such that the second side surface reaches at least the current confining layer in a formation region of the light-emitting thyristor, and an oxidized region selectively oxidized from the second side surface is formed in the current confining layer in the formation region of the light-emitting thyristor.

Abstract: A lighting device is provided. The lighting device comprises a first substrate and a plurality of second substrates. The plurality of second substrates are separately and electrically connected to the first substrate and comprise a light emitting device.

Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: A high efficiency Group III nitride light emitting diode is disclosed. The diode includes a substrate selected from the group consisting of semiconducting and conducting materials, a Group III nitride-based light emitting region on or above the substrate, and, a lenticular surface containing silicon carbide on or above the light emitting region, and extending to said light emitting region.

Abstract: A light-emitting device for generating incoherent light comprises a substrate, a semiconductor structure, and a first metallic conductor formed on the substrate. The semiconductor structure comprises a top face, a bottom face, outer side faces, a first light-emitting part, a second light-emitting part, and light-extraction surfaces arranged for harvesting light from the semiconductor structure and being distant from the outer side faces. Each of the first and second light-emitting parts comprises a lower semiconductor layer on the substrate, an upper semiconductor layer on the lower semiconductor layer, and an active region between the lower and upper semiconductors for generating light. The first metallic conductor electrically connects the upper semiconductor layer of the first light-emitting part with the lower semiconductor layer of the second light-emitting part. The substrate comprises a non-semiconductor material.

Abstract: Disclosed are a light emitting device. A light emitting diode comprises a light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.

Abstract: A light-emitting apparatus includes a submount, a chip carrier formed on the submount, and a light-emitting chip formed on the chip carrier. The light-emitting apparatus also includes a reflecting cup formed on the submount and enclosing the light-emitting chip and the chip carrier, and a transparent encapsulating material for encapsulating the light-emitting chip.

Abstract: The present invention provides a resin composition comprising a liquid crystal polyester and a titanium oxide filler, wherein when a value obtained by converting the content of aluminum in the titanium oxide filler to the content of aluminum oxide is A (% by weight) and the volume average particle diameter of the titanium oxide filler is B (?m), A and B satisfy the formula (I): A?0.1 and the formula (II): A/B2?25, a reflective board obtained by molding the resin composition, and a light-emitting apparatus comprising the reflective board and a light-emitting element. According to the resin composition of the present invention, a reflective board having high reflectance and high heat resistance can be obtained. Furthermore, a light-emitting apparatus which is excellent in properties such as luminance can be obtained by using the reflective board.

Abstract: The present application is to provide a light-emitting device comprising a metal reflective layer; a first transparent conductive oxide layer having a first refractive index; a second transparent conductive oxide layer having a second refractive index different from the first refractive index, and being between the metal reflective layer and the first transparent conductive oxide layer; and a light-emitting stack layer electrically connected to the second transparent conductive oxide layer substantially through the first transparent conductive layer; wherein there is no light absorbing material between the metal reflective layer and the first transparent conductive oxide layer.

Abstract: A light-emitting diode (LED) package structure including a carrier substrate, at least one LED chip, an optical element and a thermal-conductive transparent liquid is provided. The LED chip is disposed on the carrier substrate and has an active layer. The optical element is disposed on the substrate and forms a sealed space with the carrier substrate, and the LED chip is disposed in the sealed space. The thermal-conductive transparent liquid fills up the sealed space.

Abstract: An optoelectronic component includes a housing. At least one semiconductor chip is arranged in the housing. The semiconductor chip includes an active layer suitable for producing or detecting electromagnetic radiation. A casting compound at least partially surrounds the semiconductor chip. Reflective particles are embedded in the casting compound.

Abstract: A silicon-on-insulator wafer is provided. The silicon-on-insulator wafer includes a silicon substrate having optical vias formed therein. In addition, an optically transparent oxide layer is disposed on the silicon substrate and the optically transparent oxide layer is in contact with the optical vias. Then, a complementary metal-oxide-semiconductor layer is formed over the optically transparent oxide layer.

Abstract: Light emitting diodes include a diode region comprising a gallium nitride-based n-type layer, an active region and a gallium nitride-based p-type layer. A substrate is provided on the gallium nitride-based n-type layer and optically matched to the diode region. The substrate has a first face remote from the gallium nitride-based n-type layer, a second face adjacent the gallium nitride-based n-type layer and a sidewall therebetween. At least a portion of the sidewall is beveled, so as to extend oblique to the first and second faces. A reflector may be provided on the gallium nitride-based p-type layer opposite the substrate. Moreover, the diode region may be wider than the second face of the substrate and may include a mesa remote from the first face that is narrower than the first face and the second face.

Abstract: Disclosed are a light emitting device, a light emitting device package, a lighting system and a manufacturing method of light emitting device. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer between the first and second conductive semiconductor layers; a first ohmic layer over the light emitting structure; and a second ohmic layer including a pattern over the first ohmic layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, and a second insulating layer. The semiconductor layer includes a first major surface, a second major surface opposite to the first major surface, and a light emitting layer. The first electrode is provided on a region including the light emitting layer on the second major surface. The second electrode is provided on the second major surface and interposed in the first electrode in a planar view.

Abstract: An optoelectronic semiconductor device including: a substrate; a semiconductor system having an active layer formed on the substrate; and an electrode structure formed on the semiconductor system, wherein the electrode structure includes: a first conductivity type bonding pad; a second conductivity type bonding pad; a first conductivity type extension electrode; and a second conductivity type extension electrode, wherein the first conductivity type extension electrode and the second conductivity type extension electrode form a three-dimensional crossover; wherein the first conductivity type extension electrode and the second conductivity type extension electrode are on the opposite sides of the active layer.

Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.

Abstract: Exemplary embodiments of the present invention provide a light emitting diode package including a light emitting diode chip, a lead frame having a chip area on which the light emitting diode chip is arranged, and a package body supporting the lead frame. The lead frame includes a first terminal group arranged at a first side of the chip area and a second terminal group arranged at a second side of the chip area. The first terminal group and the second terminal group each include a first terminal and a second terminal, and in at least one of the first terminal group and the second terminal group, the first terminal is connected to the chip area and the second terminal is separated from the chip area. The first terminal has a first width, the second terminal has a second width, and the first width is different than the second width.

Abstract: According to one embodiment, a light-transmitting metal electrode includes a metal layer. The metal layer is provided on a major surface of a member and includes a metal nanowire and a plurality of openings formed with the metal nanowire. The thin layer includes a plurality of first straight line parts along a first direction and a plurality of second straight line parts along a direction different from the first direction. A maximum length of the first line parts along the first direction and a maximum length of the second line parts along the direction different from the first direction are not more than a wave length of visible light. A ratio of an area of the metal layer viewed in a normal direction of the surface to an area of the metal layer viewed in the normal direction is more than 20% and not more than 80%.

Abstract: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

Abstract: A semiconductor light emitting device has a multilayer epitaxial structure for emitting light by a light emitting layer located between a first conductive layer and a second conductive layer. The multilayer epitaxial structure can be grown directly on a base substrate. A reflective layer can be provided in the multilayer epitaxial structure between the base substrate and the first conductive layer. A distributive Bragg reflector can be positioned adjacent the substrate. A surface of the multilayer epitaxial structure can be conformed to provide improved light extraction. A phosphorus film encapsulates the multilayer epitaxial structure and its respective side surfaces.

Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.

Abstract: According to one embodiment, a nitride semiconductor device includes: a stacked foundation layer, and a functional layer. The stacked foundation layer is formed on an AlN buffer layer formed on a silicon substrate. The stacked foundation layer includes AlN foundation layers and GaN foundation layers being alternately stacked. The functional layer includes a low-concentration part, and a high-concentration part provided on the low-concentration part. A substrate-side GaN foundation layer closest to the silicon substrate among the plurality of GaN foundation layers includes first and second portions, and a third portion provided between the first and second portions. The third portion has a Si concentration not less than 5×1018 cm?3 and has a thickness smaller than a sum of those of the first and second portions.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.

Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract: A semiconductor device includes: a substrate 101, a first nitride semiconductor layer 104S which includes a plurality of nitride semiconductor layers formed on the substrate 101, and has a channel region; a second semiconductor layer 105 which is formed on the first nitride semiconductor layer 104S, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer 105, and includes a metal layer 107 or a high carrier concentration semiconductor layer having a carrier concentration of 1×1018 cm?3 or higher; an insulating layer 110 formed on the conductive layer; a gate electrode 111 formed on the insulating layer 110; and a source electrode 108 and a drain electrode 109 formed to laterally sandwich the second semiconductor layer 105.

Abstract: Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.

Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.