Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

Abstract: The present invention provides a photodiode comprising a p-i-n or pn junction at least partly formed by first and second regions (2) made of semiconductor materials having opposite conductivity type, wherein the p-i-n or pn junction comprises a light absorption region (11) for generation of charge carriers from absorbed light. One section of the p-i-n or pn junction is comprises by one or more nanowires (7) that are spaced apart and arranged to collect charge carriers generated in the light absorption region (11). At least one low doped region (10) made of a low doped or intrinsic semiconductor material provided between the nanowires (7) and one of said first region (1) and said second region (2) enables custom made light absorption region and/or avalanche multiplication region of the active region (9).

Abstract: Methods and systems for forming a photodiode in a substrate, forming a source/drain region in the substrate and extending over at least a portion of the photodiode, and growing a thermal oxide layer over the photodiode by performing a rapid thermal anneal (RTA) process utilizing an oxidizing environment.

Abstract: In a manufacturing method for a solid-state imaging device, a photoelectric conversion portion including a first impurity layer whose carrier polarity is a first conductivity type is formed within a substrate, a second impurity layer, whose carrier polarity is a second conductivity type opposite to the first conductivity type, is formed on a surface of the first impurity layer so as to be in contact with the surface located on one surface side of the substrate, a third impurity layer, whose carrier polarity is the first conductivity type, is formed on the second impurity layer so as to be in contact therewith, a gate electrode is formed above the third impurity layer so as to cover the third impurity layer, and an impurity region portion, whose carrier polarity is the first conductivity type, is formed within the substrate so as to be connected to the third impurity layer.

Abstract: An image sensor includes: a substrate, at least a pixel, and at least a light shield is provided. Wherein the pixel includes a photodiode and at least a transistor, and the transistor is connected to a metal line via a contact. The light shield is positioned around at least one side of the pixel, wherein the light shield is made while forming the contact.

Abstract: Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member.

Abstract: A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

Abstract: A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film.

Abstract: In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate 1 a first gate lamination structure which comprises a first insulating film 11 including a trap layer, and a first conductive body 9, and a second gate lamination structure which comprises a second insulating film 12 free of a trap layer and including an insulating film layer 13 doped with metal for controlling the work function at least on the upper layer, and a second conductive body 10. A source drain region 2 and a source drain region 3 are formed such that the first gate lamination structure and the second gate lamination structure are interleaved therebetween. The effective work function of the second gate lamination structure is higher than that of the first gate lamination structure.

Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution.

Abstract: According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.

Abstract: A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.

Abstract: A non-volatile memory device includes a pair of columnar cell channels vertically extending from a substrate, a doped pipe channel arranged to couple lower ends of the pair of columnar cell channels, insulation layers over the substrate in which the doped pipe channel is buried, memory layers arranged to surround side surfaces of the columnar cell channels, and control gate electrodes arranged to surround the memory layers.

Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.

Abstract: One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material.

Abstract: An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract: A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract: A semiconductor device includes a trench defined by etching a semiconductor substrate including a device isolation film and an active region, an active region protruded from a side and bottom of the trench, and a gate electrode surrounding the active region simultaneously while being buried in the trench.

Abstract: A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.

Abstract: A semiconductor device has a semiconductor substrate having an upper main surface and a lower main surface. The semiconductor substrate includes a drain layer, a main base region, an underpad base region and a source region. The semiconductor device includes a first main electrode connected to the main base regions and the source region and not connected to the underpad base region, a gate electrode opposed to a channel region in the main base region interposed between the drain layer and the source region with a gate insulating film provided therebetween, a conductive gate pad opposed to an exposed surface of the underpad base region in the upper main surface with an insulating layer interposed therebetween and the conductive gate pad is connected to the gate electrode, and a second main electrode connected to the lower main surface.

Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

Abstract: There is provided a semiconductor device in which the degradation of electric characteristics can be inhibited. A semiconductor substrate has a main surface, and a trench in the main surface. A buried insulating film is buried in the trench. The trench has one wall surface and the other wall surface which oppose each other. A gate electrode layer is located over at least the buried insulating film. The trench has angular portions which are located between the main surface of at least either one of the one wall surface and the other wall and a bottom portion of the trench.

Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type.

Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.

Abstract: An electric resistance element comprising: a base body, which is formed with a semiconductor material; a first contact element, which is electrically conductively connected to the base body; and a second contact element, which is electrically conductively connected to the base body. The base body has a first main surface into which a cutout is introduced. The first contact element is electrically conductively connected to the base body at least in places in the cutout. The base body has a second main surface, which is arranged in a manner lying opposite the first main surface. The second contact element is electrically conductively connected to the base body at least in places at the second main surface.

Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.

Abstract: A semiconductor device includes a gate electrode formed over a semiconductor substrate, and a sidewall spacer formed on a sidewall of the gate electrode. The sidewall spacer formed along the sidewall parallel to a gate length direction of the gate electrode has a first thickness, and the sidewall spacer formed along the sidewall parallel to a gate width direction of the gate electrode has a second thickness that is greater than the first thickness.

Abstract: A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between ?0.1 Gpa and ?3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer.

Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

Abstract: A method of manufacturing a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, a transistor is positioned in the transistor region and a resistor is positioned in the resistor region; forming a dielectric layer exposing tops of the transistor and the resistor on the substrate; performing a first etching process to remove portions of the resistor to form two first trenches respectively at two opposite ends of the resistor; forming a patterned protecting layer in the resistor region; performing a second etching process to remove a dummy gate of the transistor to form a second trench in the transistor region; and forming a metal layer filling the first trenches and the second trench.

Abstract: An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

Abstract: A device being a micro-system and/or a nano-system which includes a first substrate, having at least one lower electrode and at least one dielectric layer, and includes an intermediate substrate extending across a main plane of the device and including a moving portion. The intermediate substrate is attached, outside the moving portion, by molecular bonding to the first substrate. The moving portion faces at least a portion of the lower electrode. The device also includes an upper substrate, attached to the intermediate substrate. The moving portion is movable between the lower electrode and the upper substrate. The first, intermediate, and upper substrates extend in a plane parallel to the main plane of the device. The lower electrode detects a component of the movement of the moving portion perpendicular to the plane of the device.

Abstract: A method for fabricating a MEMS resonator is provided. A stacked main body including a silicon substrate, a plurality of metallic layers and an isolation layer is formed and has a first etching channel extending from the metallic layers into the silicon substrate. The isolation layer is filled in the first etching channel. The stacked main body also has a predetermined suspended portion. Subsequently, a portion of the isolation layer is removed so that a second etching channel is formed and the remained portion of the isolation layer covers an inner sidewall of the first etching channel. Afterwards, employing the isolation layer that covers the inner sidewall of the first etching channel as a mask, an isotropic etching process through the second etching channel is applied to the silicon substrate, thereby forming the MEMS resonator suspending above the silicon substrate. A micro electronic device is also provided.

Abstract: In a method for manufacturing a micromechanical component, a cavity is produced in the substrate from an opening at the rear of a monocrystalline semiconductor substrate. The etching process used for this purpose and the monocrystalline semiconductor substrate used are controlled in such a way that a largely rectangular cavity is formed.

Abstract: A MEMS device is disclosed. The MEMS device comprises a first plate with a first surface and a second surface; and an anchor attached to a first substrate. The MEMS device further includes a second plate with a third surface and a fourth surface attached to the first plate. A linkage connects the anchor to the first plate, wherein the first plate and second plate are displaced in the presence of an acoustic pressure differential between the first and second surfaces of the first plate. The first plate, second plate, linkage, and anchor are all contained in an enclosure formed by the first substrate and a second substrate, wherein one of the first and second substrates contains a through opening to expose the first surface of the first plate to the environment.

Abstract: A storage element includes: a storage layer which has magnetization perpendicular to a film surface, the direction of the magnetization being changed in accordance with information; a magnetization fixed layer which has magnetization perpendicular to a film surface used as a base of information stored in the storage layer; and an insulating layer of a nonmagnetic substance provided between the storage layer and the magnetization fixed layer. In the storage element described above, the magnetization of the storage layer is reversed using a spin torque magnetization reversal generated by a current flowing in a lamination direction of a layer structure including the storage layer, the insulating layer, and the magnetization fixed layer to store information, the storage layer is directly provided with a layer at a side opposite to the insulating layer, and this layer includes a conductive oxide.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the active layers (such as AP1, SIL, FGL, and Free layers). An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi.

Abstract: An image sensor device that includes a substrate and a plurality of color filters. The substrate includes a plurality of photo detectors (wherein a first portion of the plurality of photo detectors each has a lateral size that is smaller than that of each of a second portion of the plurality of photo detectors) and a plurality of contact pads which are electrically coupled to the photo detectors. The plurality of color filters are each disposed over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. A third portion of the plurality of photo detectors are laterally disposed between the first and second portions of the photo detectors, and each having a lateral size between those of the first and second portions of the photo detectors.

Abstract: An image sensing device includes a light-shielding film having transit portions, a first film and a second film. The second film comprises a first layer having a different refractive index from the first film. The first layer lies within at least the transit portions, and forms interfaces with the first film. The distance between the interface and the corresponding photoelectric conversion portion is greater than the distance between the photoelectric conversion portion and the lower end of the corresponding transit portion.

Abstract: A metal encapsulating sheet is configured to cover a display unit on a substrate and includes an insulating base film, and metal wirings on the base film for forming a current path between the display unit and a power supply, wherein connecting units of the metal wirings coupled to the power supply are outside a light-emitting region corresponding to the display unit.