Abstract: A dual-gate transistor including: a first insulating layer provided to cover a first conductive layer; a first semiconductor layer over the first insulating layer; second semiconductor layers over the first semiconductor layer, the second semiconductor layers are spaced from each other to expose the first semiconductor layer; impurity semiconductor layers over the second semiconductor layers; second conductive layers over the impurity semiconductor layers; second insulating layers over the second conductive layers; a third insulating layer to cover the first semiconductor layer, the second semiconductor layers, the impurity semiconductor layers, the second conductive layers, and the second insulating layers; and a third conductive layer at least over the third insulating layer, and in the dual-gate transistor including the first to third insulating layers with openings, the first insulating layer is substantially equal in thickness to the second insulating layer.

Abstract: Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

Abstract: A crystalline silicon thin film is formed by irradiating a silicon thin film with a laser beam. The laser beam is a continuous wave laser beam. An intensity distribution of the laser beam in a first region about a center of the intensity distribution is symmetric on an anterior side and a posterior side of the center. The intensity distribution in a second region about the center is asymmetric on the anterior side and the posterior side. The first region is from the maximum intensity of the laser beam at the center to an intensity half of the maximum intensity. The second region is at most equal to the half of the maximum intensity of the laser beam. In the second region, an integral intensity value on the posterior side is larger than on the anterior side.

Abstract: An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is applied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed.

Abstract: A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a replacement gate approach, the fill conditions upon filling in the highly conductive electrode metal, such as aluminum, may be enhanced by removing the final work function metal, for instance a titanium nitride material in P-channel transistors, only preserving a well-defined bottom layer.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

Abstract: Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

Abstract: When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.

Abstract: Methods for forming CMOS integrated circuit structures are provided, the methods comprising performing a first implantation process for performing at least one of a halo implantation and a source and drain extension implantation into a region of a semiconductor substrate and then forming a stressor region in another region of the semiconductor substrate. Furthermore, a semiconductor device structure is provided, the structure comprising a stressor region embedded into a semiconductor substrate adjacent to a gate structure, the embedded stressor region having a surface differing along a normal direction of the surface from an interface by less than about 8 nm, wherein the interface is formed between the gate structure and the substrate.

Abstract: A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET.

Abstract: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.

Abstract: A method of forming a dielectric stack devoid of an interfacial layer includes subjecting an exposed interfacial layer provided on a semiconductor material to a low pressure thermal anneal process for a predetermined time period at a temperature of about 900° C. to about 1000° C. with an inert gas purge. A semiconductor structure is also disclosed, with a dielectric stack devoid of an interfacial layer.

Abstract: The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory.

Abstract: According to one embodiment, a method is disclosed for manufacturing nonvolatile semiconductor memory device including forming a stacked body by alternately stacking an electrode layer and a layer-to-be-etched, and forming an oxidized layer between the layer-to-be-etched provided at least in any side of an upper side and a lower side of the electrode layer and the electrode layer. The method can include forming a groove which passes through the stacked body. The method can include embedding an insulating body within the groove. The method can include forming a hole which passes through the stacked body. The method can include selectively removing the layer-to-be-etched via the hole. The method can include forming a charge storage layer in an inner side of the hole. The method can include forming a channel body layer in an inner side of the charge storage layer.

Abstract: A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate having a protruding channel region, forming a gate insulation layer surrounding the protruding channel region, forming a sacrificial layer having an etch selectivity varying in a thickness direction of the sacrificial layer, on the gate insulation layer, and performing a gate-last process to form a gate electrode on the gate insulation layer in place of the sacrificial layer.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Abstract: A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

Abstract: The concentration of a non-silicon species in a semiconductor alloy, such as a silicon/germanium alloy, may be increased after a selective epitaxial growth process by oxidizing a portion of the semiconductor alloy and removing the oxidized portion. During the oxidation, preferably the silicon species may react to form a silicon dioxide material while the germanium species may be driven into the remaining semiconductor alloy, thereby increasing the concentration thereof. Consequently, the threshold adjustment of sophisticated transistors may be accomplished with enhanced process uniformity on the basis of a given parameter setting for the epitaxial growth process while nevertheless providing a high degree of flexibility in adjusting the composition of the threshold adjusting material.

Abstract: A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.

Abstract: In a method of manufacturing a semiconductor device, a source/drain feature is formed over a substrate. A Si-containing layer is formed over the source/drain feature. A metal layer is formed over the Si-containing layer. A metal silicide layer is formed from the metal layer and Si in the Si-containing layer.

Abstract: A process, machine, manufacture, composition of matter, and improvement thereof, and method of making and method of using the same, as well as necessary intermediates, generally relating to the field of semiconductor devices, the structure of transistors, and the structure of compound semiconductor heterojunction bipolar transistors.

Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.

Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.

Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.

Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.

Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.

Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.

Abstract: A method of forming a silicon based optical waveguide can include forming a silicon-on-insulator structure including a non-crystalline silicon portion and a single crystalline silicon portion of an active silicon layer in the structure. The non-crystalline silicon portion can be replaced with an amorphous silicon portion and maintaining the single crystalline silicon portion and the amorphous portion can be crystallized using the single crystalline silicon portion as a seed to form a laterally grown single crystalline silicon portion including the amorphous and single crystalline silicon portions.

Abstract: A fin field-effect transistor (FinFET) includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region uniformly beneath a top surface and sidewall surfaces of the fin structure, the LDD region having a depth less than about 25 nm. Another FinFET includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region, and a top surface of the fin structure has a different crystal structure from a sidewall surface of the fin structure. A method of making a FinFET includes forming a fin structure on a substrate. The method further includes performing a pulsed plasma doping on the fin structure to form lightly doped drain (LDD) regions in the fin structure.

Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Abstract: A method for fabricating a metal-oxide-semiconductor field-effect transistor includes the following steps. Firstly, a substrate is provided. A gate structure, a first spacer, a second spacer and a source/drain structure are formed over the substrate. The second spacer includes an inner layer and an outer layer. Then, a thinning process is performed to reduce the thickness of the second spacer, thereby retaining the inner layer of the second spacer. After a stress film is formed on the inner layer of the second spacer and the source/drain structure, an annealing process is performed. Afterwards, the stress film is removed.

Abstract: The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.

Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.

Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.

Abstract: A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench.

Abstract: A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed.

Abstract: Electrodes formed in a partial surface area of a semiconductor substrate and distal ends of conductive nanotubes bristled on a surface of a growth substrate, are bombarded with rare gas plasma. The distal ends of the conductive nanotubes bombarded with the rare gas plasma are brought into contact with the electrodes bombarded with the rare gas plasma to fix the conductive nanotubes to the electrodes. The growth substrate is separated from the semiconductor substrate in such a manner that the conductive nanotubes fixed to the electrodes remain on the electrodes formed on the semiconductor substrate.

Abstract: After a plurality of pads (2) are formed on an insulation film (1), a passivation film (3) is formed on the entire surface thereof, and opening parts (3a) which exposes all the pads (2) are formed in the passivation film (3). Next, another passivation film is formed on the entire surface and, for each of the pads (2), an opening part is formed in this passivation film to expose the central portion of the pad (2). According to the above method, the probing test can be performed with the opening parts (3a) formed in the passivation film (3). Performing the probing test in such a state increases the probability that the probe contacts the pad (2) since the entire surface of the pad (2) is exposed, thereby providing the test with a higher accuracy. Thus, the pad can be miniaturized and/or the pitch can be narrowed without requiring a higher accuracy of the probe.

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract: The invention relates to an ultrathin semiconductor circuit having contact bumps and to a corresponding production method. The semiconductor circuit includes a bump supporting layer having a supporting layer thickness and having a supporting layer opening for uncovering a contact layer element being formed on the surface of a semiconductor circuit. An electrode layer is situated on the surface of the contact layer element within the opening of the bump supporting layer, on which electrode layer is formed a bump metallization for realizing the contact bump. On account of the bump supporting layer, a thickness of the semiconductor circuit can be thinned to well below 300 micrometers, with the wafer reliably being prevented from breaking. Furthermore, the moisture barrier properties of the semiconductor circuit are thereby improved.

Abstract: The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A conductive layer is deposited on the substrate. A patterned hard mask is formed on the conductive layer and then a patterned photoresist is formed on the patterned hard mask and the conductive layer. A local metal catalyst layer is formed on the conductive layer in the openings of the patterned photoresist. Carbon nanotubes (CNTs) are grown from the local metal catalyst layer. The conductive layer is etched by using the CNTs and the patterned hard mask as etching mask to form metal features. An inter-level dielectric (ILD) layer is deposited between metal features.