Patents Issued in July 15, 2014
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Patent number: 8779390Abstract: An apparatus for time-gated fluorescence or luminescence detection includes gating means (206) arranged to alternately permit light from an excitation source (242) to be directed to a sample (235) along a first communication path (231, 232), and then permit light emitted from the sample to be directed to a detector (246) along a second communication path (237, 238) while blocking the first communication path (231, 232): The gating means (206) may comprise a single chopper wheel or apertured disc, or a rotating or oscillating arm, and may further comprise one or more reflective facets (207). The gating means (206) may be driven via a magnetic rotor, with a ferrite bead placed to offset rotor magnets with respect to drive coils, when at rest, so as to assist with self starting.Type: GrantFiled: May 13, 2009Date of Patent: July 15, 2014Assignee: MacQuarie UniversityInventor: Russell Connally
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Patent number: 8779391Abstract: An exemplary sterilization system includes a self-propelled robotic mobile platform for locating and eradicating infectious bacterial and virus strains on floors (and objects thereon), walls, cabinets, angled structures, etc., using one or more ultraviolet light sources. A controller allows the system to adjust the quantity of ultraviolet light received by a surface by, for example, changing the intensity of energy input to a ultraviolet light source, changing a distance between a ultraviolet light source and a surface being irradiated, changing the speed/movement of the mobile platform to affect time of exposure, and/or by returning to contaminated areas for additional passes. The mobile platform may include a sensor capable of detecting fluorescence of biological contaminants irradiated with ultraviolet light to locate contaminated areas. The system is thus capable of “seek and destroy” functionality by navigating towards contaminated areas and irradiating those areas with ultraviolet light accordingly.Type: GrantFiled: February 24, 2012Date of Patent: July 15, 2014Assignee: Teckni-CorpInventors: Patrick Flaherty, Bruce L. Winkler, Robert J. Gold
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Patent number: 8779392Abstract: The invention relates to a charged particle beam lithography system comprising: a charged particle optical column arranged in a vacuum chamber for projecting a charged particle beam onto a target, wherein the column comprises deflecting means for deflecting the charged particle beam in a deflection direction, a target positioning device comprising a carrier for carrying the target, and a stage for carrying and moving the carrier along a first direction, wherein the first direction is different from the deflection direction, wherein the target positioning device comprises a first actuator for moving the stage in the first direction relative to the charged particle optical column, wherein the carrier is displaceably arranged on the stage and wherein the target positioning device comprises retaining means for retaining the carrier with respect to the stage in a first relative position.Type: GrantFiled: November 16, 2011Date of Patent: July 15, 2014Assignee: Mapper Lithography IP B.V.Inventors: Jerry Peijster, Guido de Boer
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Patent number: 8779393Abstract: A charged particle beam irradiation system includes: an accelerator which accelerates charged particles along an orbit, thereby emitting a charged particle beam; a gantry on which the accelerator is mounted and which can rotate or oscillate around a given axis; and an irradiation section which is mounted on the gantry and can irradiate the charged particle beam emitted from the accelerator, toward an irradiated body, wherein a shielding body which is provided in the gantry and shields radiation that is radiated from a side of the accelerator, which may be a face intersecting the radial direction of the orbit, is disposed.Type: GrantFiled: March 8, 2012Date of Patent: July 15, 2014Assignee: Sumitomo Heavy Industries, Ltd.Inventor: Kenzo Sasai
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Patent number: 8779394Abstract: A charged particle beam writing apparatus includes a division/distribution processing unit to divide and distribute processed data into data groups each having an approximately equal data amount respectively, transmitting units to transmit the processed data of the groups such that processed data is transmitted in descending order with respect to order of writing processing for each data group and the groups are transmitted in parallel, memories to store the processed data of the groups such that each of the memories stores processed data of each different one of the groups, a writing order data output unit to output them, regardless of data group and in order of writing processing, and a writing unit to write a pattern on a target workpiece with a charged particle beam, based on the processed data output in the order of writing processing.Type: GrantFiled: March 27, 2012Date of Patent: July 15, 2014Assignee: NuFlare Technology, Inc.Inventor: Hideo Inoue
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Patent number: 8779395Abstract: An ion implantation system for improving performance and extending lifetime of an ion source is disclosed whereby the selection, delivery, optimization and control of the flow rate of a co-gas into an ion source chamber is automatically controlled.Type: GrantFiled: December 1, 2011Date of Patent: July 15, 2014Assignee: Axcelis Technologies, Inc.Inventors: Neil K. Colvin, Tseh-Jen Hsieh
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Patent number: 8779396Abstract: The present invention provides a drawing apparatus which performs drawing on a substrate with a charged particle beam based on drawing data generated from pattern data representing a circuit pattern to be drawn on the substrate, and mark data representing a mark to be drawn on the substrate, the apparatus including an obtaining unit configured to obtain information associated with a positioning accuracy of the charged particle beam relative to the substrate, a determination unit configured to determine a drawing region for the mark based on the obtained information, and a generation unit configured to generate the drawing data by combining the pattern data and the mark data such that the mark is drawn in the determined drawing region.Type: GrantFiled: December 5, 2012Date of Patent: July 15, 2014Assignee: Canon Kabushiki KaishaInventors: Masashi Kotoku, Kuniyasu Haginiwa
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Patent number: 8779397Abstract: A substrate cover 40 includes a conductive portion 41 having a shape corresponding to a peripheral edge region of a substrate. Since at least part of the conductive portion includes transmissive portions 47 each formed of a light transmissive member, it is configured so as to allow desired light to penetrate through. The position of each edge portion of the substrate is detected in such a manner that the substrate is disposed with the substrate cover 40 placed thereon between light irradiation means and a light detecting unit, irradiation light directed from the light irradiation means located above the substrate to the edge portion of the substrate is made to penetrate through at least part of the substrate cover 40, the edge portion of the substrate is then irradiated with light from the irradiation means.Type: GrantFiled: December 16, 2010Date of Patent: July 15, 2014Assignees: NuFlare Technology, Inc., Kabushiki Kaisha ToshibaInventors: Michihiro Kawaguchi, Keisuke Yamaguchi, Shun Kanezawa, Soichiro Mitsui, Kiminobu Akeno
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Patent number: 8779398Abstract: Compact, dual energy radiation scanning systems are described comprising two particle beam accelerators, each configured to accelerate charged particles to different energies, positioned parallel to a direction of movement of an object to be inspected. The accelerator may be positioned perpendicular to a plane of the conveying system, instead. Bend magnet systems bend each charged particle beam toward a respective target. Alternatively, a single dual energy accelerator capable of accelerating charged particles to at least two different energies is positioned parallel to the direction of movement of the object, or perpendicular to a plane of the conveying system. A single bend magnet system is provided to bend each accelerated charged particle beam toward the same target. The particle beams may be bent through an orbit chamber. Two separate passages may be defined through at least part of the orbit chamber, one for charged particles having each energy.Type: GrantFiled: June 8, 2012Date of Patent: July 15, 2014Assignee: Varian Medical Systems, Inc.Inventors: David Whittum, James E. Clayton
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Patent number: 8779399Abstract: The present invention provides an electrostatic deflector which deflects a plurality of charged particle beams, the deflector comprising a first electrode member including a plurality of first electrode pairs arranged along a first axis direction in an oblique coordinate system, and a second electrode member including a plurality of second electrode pairs arranged along a second axis direction in the oblique coordinate system, wherein each of the plurality of charged particle beams is deflected by a corresponding first electrode pair of the plurality of first electrode pairs, and a corresponding second electrode pair of the plurality of second electrode pairs.Type: GrantFiled: June 19, 2013Date of Patent: July 15, 2014Assignee: Canon Kabushiki KaishaInventor: Toshiro Yamanaka
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Patent number: 8779400Abstract: An ion beam machining and observation method relevant to a technique of cross sectional observation of an electronic component, through which a sample is machined by using an ion beam and a charged particle beam processor capable of reducing the time it takes to fill up a processed hole with a high degree of flatness at the filled area. The observation device is capable of switching the kind of gas ion beam used for machining a sample with the kind of a gas ion beam used for observing the sample. To implement the switch between the kind of a gas ion beam used for sample machining and the kind of a gas ion beam used for sample observation, at least two gas introduction systems are used, each system having a gas cylinder, a gas tube, a gas volume control valve, and a stop valve.Type: GrantFiled: June 25, 2013Date of Patent: July 15, 2014Assignee: Hitachi High-Technologies CorporationInventors: Hiroyasu Shichi, Satoshi Tomimatsu, Kaoru Umemura, Noriyuki Kaneoka, Koji Ishiguro
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Patent number: 8779401Abstract: A target supply unit includes a nozzle unit having a through-hole to allow a target material to be outputted therethrough. A cover is provided to cover the nozzle unit, the cover having a through-hole to allow the target material to pass therethrough. A discharge device is included to pump out gas inside a space defined by the cover.Type: GrantFiled: June 26, 2012Date of Patent: July 15, 2014Assignee: GIGAPHOTON Inc.Inventors: Hakaru Mizoguchi, Takayuki Yabu, Toshihiro Nishisaka
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Patent number: 8779402Abstract: A target supply device includes a target supply device body including a nozzle having a through-hole through which a target material is discharged, a piezoelectric member having first and second surfaces and connected to the target supply device body at the first surface, the piezoelectric member being configured such that a distance between the first and second surfaces changes in according with an externally supplied electric signal, an elastic member having first and second ends and connected to the second surface of the piezoelectric member at the first end, the elastic member being configured such that a distance between the first and second ends extends or contract in accordance with an externally applied force, and a regulating member configured to regulate a distance between the second end of the elastic member and the target supply device body.Type: GrantFiled: November 13, 2012Date of Patent: July 15, 2014Assignee: Gigaphoton Inc.Inventors: Takayuki Yabu, Yukio Watanabe, Toshihiro Nishisaka, Hiroshi Someya, Osamu Wakabayashi
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Patent number: 8779403Abstract: An apparatus and a method for generating extreme ultra violet radiation are provided. The apparatus for generating extreme ultra violet radiation includes a light source, a first reflecting mirror on which source light emitted from the light source is incident, a second reflecting mirror on which first reflected light reflected by the first reflecting mirror is incident, a focus mirror on which second reflected light reflected by the second reflecting mirror is incident, the focus mirror reflecting third reflected light back to the second reflecting mirror, and a gas cell on which fourth reflected light reflected by the second reflecting mirror is incident.Type: GrantFiled: December 11, 2013Date of Patent: July 15, 2014Assignees: Samsung Electronics Co., Ltd., Fine Semitech Corp.Inventors: Dong-Gun Lee, Eok-Bong Kim, Jong-Ju Park, Seong-Sue Kim
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Patent number: 8779404Abstract: A system for electro-hydrodynamically extracting energy from wind includes an upstream collector that is biased at an electric potential and induces an electric field. An injector introduces a particle into the electric field. The wind drag on the particle is at least partially opposed by a force of the electric field on the particle. A sensor monitors an ambient atmospheric condition, and a controller changes a parameter of the injector in response to a change in the atmospheric condition.Type: GrantFiled: July 1, 2013Date of Patent: July 15, 2014Assignee: Accio Energy, Inc.Inventors: David Carmein, Dawn White
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Patent number: 8779405Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: GrantFiled: June 1, 2012Date of Patent: July 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
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Patent number: 8779406Abstract: A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.Type: GrantFiled: January 18, 2013Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Satoru Ito, Satoru Fujii, Shinichi Yoneda, Takumi Mikawa
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Patent number: 8779407Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.Type: GrantFiled: February 7, 2012Date of Patent: July 15, 2014Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLCInventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Yun Wang, Hong Sheng Yang
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Patent number: 8779408Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.Type: GrantFiled: March 30, 2012Date of Patent: July 15, 2014Assignee: Macronix International Co., Ltd.Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
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Patent number: 8779409Abstract: Low energy memristors with engineered switching channel materials include: a first electrode; a second electrode; and a switching layer positioned between the first electrode and the second electrode, wherein the switching layer includes a first phase comprising an insulating matrix in which is dispersed a second phase comprising an electrically conducting compound material for forming a switching channel.Type: GrantFiled: September 28, 2012Date of Patent: July 15, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jianhua Yang, Minxian Max Zhang, Gilberto Medeiros Riberio, R. Stanley Williams
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Patent number: 8779410Abstract: According to one embodiment, a resistance change memory includes resistance change elements, vias and sidewall insulating layers, the elements and the vias provided alternately in a first direction and a second direction orthogonal to the first direction, and the sidewall insulating layers provided on sidewalls of the elements. The elements are provided in a lattice pattern having a constant pitch. A thickness of each of the sidewall insulating layers in a direction orthogonal to the sidewalls is a value for contacting the sidewall insulating layers each other or more to form holes between the sidewall insulating layers. The vias are provided in the holes respectively.Type: GrantFiled: January 23, 2012Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Motoyuki Sato, Yoshiaki Asao, Takashi Obara, Takashi Nakazawa
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Patent number: 8779411Abstract: The present disclosure provides a light emitting diode and a method of manufacturing the same. The light emitting diode includes a graphene layer on a second conductive semiconductor layer and a plurality of metal nanoparticles formed on some region of the graphene layer, whereby adhesion between the second conductive semiconductor layer comprised of an inorganic material and the graphene layer is enhanced, thereby securing stability and reliability of the light emitting diode. In addition, the light emitting diode allows uniform spreading of electric current, thereby allowing stable emission of light through a surface area of the light emitting diode.Type: GrantFiled: November 16, 2012Date of Patent: July 15, 2014Assignee: Gwanju Institute of Science and TechnologyInventors: Dong Seon Lee, Jae Phil Shim, Seong Ju Park, Min Hyeok Choe, Do Hyung Kim, Tak Hee Lee
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Patent number: 8779412Abstract: There is provided a semiconductor light emitting device including: first and second conductivity type semiconductor layers; and an active layer disposed between the first and second conductivity type semiconductor layers and having a structure in which a plurality of quantum barrier layers and a plurality of quantum well layers are alternately disposed, wherein at least one of the plurality of quantum well layers includes a first region in which band gap energy is reduced through a first slope and a second region in which band gap energy is reduced through a second slope different from the first slope. The influence of polarization is minimized by adjusting the shape of the band gap of the quantum well layer, crystallinity and internal quantum efficiency can be enhanced.Type: GrantFiled: July 19, 2012Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Heon Han, Do Young Rhee, Jong Hyun Lee, Jin Young Lim, Young Sun Kim
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Patent number: 8779413Abstract: Optoelectronic devices and methods of producing the same are disclosed. Methods may include forming a film from fused all-inorganic colloidal nanostructures, where the nanostructures may include inorganic nanoparticles and functional inorganic ligands, and the fused nanostructures may form an electrical network that is photoconductive. Other methods may provide an optoelectronic device which may include an integrated circuit or large panel thin-film transistor matrix, an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions.Type: GrantFiled: January 31, 2013Date of Patent: July 15, 2014Assignee: Sunpower Technologies LLCInventor: Daniel Landry
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Patent number: 8779414Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.Type: GrantFiled: June 21, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Philip S. Waggoner
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Patent number: 8779415Abstract: Organic polymeric multi-metallic alkoxide or aryloxide composites are used as dielectric materials in various devices with improved properties such as improved mobility. These composites comprise an organic polymer comprising metal coordination sites, and multi-metallic alkoxide or aryloxide molecules that are coordinated with the organic polymer, the multi-metallic alkoxide or aryloxide molecules being represented by: (M)n(OR)x wherein at least one M is a metal selected from Group 2 of the Periodic Table and at least one other M is a metal selected from any of Groups 3 to 12 and Rows 4 and 5 of the Periodic Table, n is an integer of at least 2, R represents the same or different alkyl or aryl groups, and x is an integer of at least 2.Type: GrantFiled: November 8, 2012Date of Patent: July 15, 2014Assignee: Eastman Kodak CompanyInventors: Deepoak Shukla, Dianne M. Meyer
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Patent number: 8779416Abstract: An organic light emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes: i) gate wires positioned on a substrate in a first direction, ii) data wires positioned on the gate wires in a second direction crossing the first direction, iii) a pixel circuit including first thin film transistors respectively connected to the gate wires and the data wires and iii) an OLED connected to the pixel circuit. The first thin film transistor may also include a first active layer interconnecting the data wires and the OLED and including a channel region and source and drain regions doped with an impurity, and a first gate electrode positioned over the first active layer with first and second insulation layers sequentially interposed therebetween, wherein the second insulation layer is positioned on the channel region.Type: GrantFiled: November 28, 2012Date of Patent: July 15, 2014Assignee: Samsung Display Co., Ltd.Inventor: Ok-Byoung Kim
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Patent number: 8779417Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: GrantFiled: October 28, 2013Date of Patent: July 15, 2014Assignee: Sony CorporationInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Patent number: 8779418Abstract: An object is to provide a thin film transistor having favorable electric characteristics and a semiconductor device including the thin film transistor as a switching element. The thin film transistor includes a gate electrode formed over an insulating surface, a gate insulating film over the gate electrode, an oxide semiconductor film which overlaps with the gate electrode over the gate insulating film and which includes a layer where the concentration of one or a plurality of metals contained in the oxide semiconductor is higher than that in other regions, a pair of metal oxide films formed over the oxide semiconductor film and in contact with the layer, and a source electrode and a drain electrode in contact with the metal oxide films. The metal oxide films are formed by oxidation of a metal contained in the source electrode and the drain electrode.Type: GrantFiled: October 7, 2010Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
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Patent number: 8779419Abstract: An object of the present invention is to provide a novel semiconductor device which is excellent in stability, uniformity, reproducibility, heat resistance, durability and the like, and can exert excellent transistor properties. The semiconductor device is a thin-film transistor, and this thin-film transistor uses, as an active layer, a polycrystalline oxide semiconductor thin film containing In and two or more metals other than In and having an electron carrier concentration of less than 1×1018/cm3.Type: GrantFiled: March 9, 2012Date of Patent: July 15, 2014Assignee: Idemitsu Kosan Co., Ltd.Inventors: Koki Yano, Inoue Kazuyoshi
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Patent number: 8779420Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.Type: GrantFiled: November 23, 2012Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8779421Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.Type: GrantFiled: July 18, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida
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Patent number: 8779422Abstract: A semiconductor device includes an active body having two sidewalls facing each other in a lateral direction, a junction formed in a sidewall of the two sidewalls, a dielectric layer having an open portion to expose the junction and covering the active body, a junction extension portion having a buried region to fill the open portion, and a bit line coupled to the junction extension portion.Type: GrantFiled: September 23, 2011Date of Patent: July 15, 2014Assignee: SK Hynix Inc.Inventors: Sang-Do Lee, Kyung-Bo Ko, Hae-Jung Lee
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Patent number: 8779423Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming an epitaxial layer on a top surface of the semiconductor substrate and having a predetermined thickness, and forming a plurality of trenches in the epitaxial layer. The trenches are formed in the epitaxial layer and have a predetermined depth, top width, and bottom width. Further, the method includes performing a first trench filling process to form a semiconductor layer inside of the trenches using a mixture gas containing at least silicon source gas and halogenoid gas, stopping the first trench filling process when at least one trench is not completely filled, and performing a second trench filling process, different from the first trench filling process, to fill the plurality of trenches completely.Type: GrantFiled: October 16, 2012Date of Patent: July 15, 2014Assignee: Shanghai Hua Hong Nec Electronics Company, LimitedInventors: Jiquan Liu, Shengan Xiao, Wei Ji
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Patent number: 8779424Abstract: A sheet for use in a light-emitting device including layers including a light-emitting layer was invented. The sheet includes: a first layer including a plurality of projecting portions; and a second layer on the first layer, in which the projecting portions each include at least two steps, the second layer is formed on top at least surfaces of the steps, and when an effective refractive index of the first layer is n1, an effective refractive index of the second layer is n2, and an effective refractive index of the air above the second layer is n0, a relationship n1>n2>n0 is satisfied.Type: GrantFiled: June 17, 2013Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventor: Jumpei Matsuzaki
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Patent number: 8779425Abstract: A light emitting device, a light emitting device package, and a lighting system are provided. The light emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first and second conductive type semiconductor layers. The active layer includes a first active layer adjacent to the second conductive type semiconductor layer, a second active layer adjacent to the first conductive type semiconductor layer, and a gate quantum barrier between the first and second active layers.Type: GrantFiled: March 26, 2013Date of Patent: July 15, 2014Assignee: LG Innotek Co., Ltd.Inventors: Yong Tae Moon, Jeong Sik Lee, Dae Seob Han
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Patent number: 8779426Abstract: A thin film transistor for increasing the conductivity of a channel region and suppressing the leakage current of a back channel region, and a display device including the thin film transistor, are discussed. According to an embodiment, the thin film transistor includes a gate electrode arranged on a substrate, a source electrode and a drain electrode spaced from each other on the substrate, a gate insulating film to insulate the gate electrode from the source electrode and the drain electrode, and a semiconductor layer insulated from the gate electrode through the gate insulating film, the semiconductor layer including a channel region and a back channel region, the semiconductor layer made of (In2O3)x(Ga2O3)y(ZnO)z(0?x?5, 0?y?5, 0?z?5), wherein X or Z is greater than Y in the channel region of the semiconductor layer, and Y is greater than X and Z in the back channel region of the semiconductor layer.Type: GrantFiled: July 12, 2010Date of Patent: July 15, 2014Assignee: LG Display Co., Ltd.Inventors: Jae-Seok Heo, Ji-Yeon Seo
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Patent number: 8779428Abstract: A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.Type: GrantFiled: June 23, 2011Date of Patent: July 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu
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Patent number: 8779429Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.Type: GrantFiled: August 2, 2012Date of Patent: July 15, 2014Assignee: Samsung Display Co., Ltd.Inventors: O-Sung Seo, Hwa-Yeul Oh, Hyoung-Cheol Lee, Tae-Kyung Yim
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Patent number: 8779430Abstract: A semiconductor device (18) includes: a gate electrode (102) formed on a substrate (101); a semiconductor layer (104) formed above the gate electrode (102) and including a source region, a drain region, and a channel region; a source electrode (106) connected to the source region above the semiconductor layer (104); and a drain electrode (107) connected to the drain region above the semiconductor layer (104). The semiconductor layer (104) has, at a portion overlapping the drain electrode (107), a protrusion that protrudes outward along an extending direction of a drain line drawn out from the drain electrode (107). At an outside of the channel region sandwiched between the drain electrode (107) and the source electrode (106), the semiconductor layer (104) has an adjustment portion where an outer boundary of the semiconductor layer (104) is positioned more inward than an outer boundary of the gate electrode (102).Type: GrantFiled: April 27, 2011Date of Patent: July 15, 2014Assignee: Sharp Kabushiki KaishaInventors: Shoji Okazaki, Takeshi Yaneda, Wataru Nakamura, Hiromitsu Katsui
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Patent number: 8779431Abstract: A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.Type: GrantFiled: September 26, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Tatsuya Arao, Munehiro Azami
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Patent number: 8779432Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.Type: GrantFiled: January 20, 2012Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiromichi Godo
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Patent number: 8779433Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.Type: GrantFiled: May 25, 2011Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Yoshinori Ieda, Kiyoshi Kato, Yuto Yakubo, Yuki Hata
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Patent number: 8779434Abstract: A thin film transistor array is disclosed. The thin film transistor array includes plural gate electrodes formed on an insulation substrate, plural source electrodes formed above or under the gate electrodes via a gate insulation film so that the source electrodes cross the gate electrodes in a planar view, plural drain electrodes formed at corresponding positions surrounded by the gate electrodes and the source electrodes in a planar view in the same layer as that of the source electrodes, semiconductor layers formed via the gate insulation film to face the gate electrodes for forming corresponding channel regions between the source electrodes and the drain electrodes. The plural gate electrodes are linearly formed, and the channel regions are disposed to face the gate electrodes.Type: GrantFiled: October 6, 2008Date of Patent: July 15, 2014Assignee: Ricoh Company, Ltd.Inventors: Takao Inoue, Takumi Yamaga, Atsushi Onodera
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Patent number: 8779435Abstract: A semiconductor wafer has a plurality of optical semiconductor devices (namely, semiconductor lasers) which are formed from epitaxially grown layers and arranged across the surface of the semiconductor wafer. The InGaAs epitaxial layer of the semiconductor wafer has an opening (or groove) which continuously extends along and between the plurality of optical semiconductor devices, and which exposes the layer underlying the InGaAs epitaxial layer to at least the layer overlying the InGaAs epitaxial layer. The semiconductor wafer may be scribed along this opening to form a vertically extending crack therein.Type: GrantFiled: October 12, 2011Date of Patent: July 15, 2014Assignee: Mitsubishi Electric CorporationInventor: Masato Negishi
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Patent number: 8779436Abstract: A display device includes a plurality of pixel units. Each of the pixel units at least includes three sub-pixels for displaying different colors. The three sub-pixels are electrically connected to three different gate lines, and at least two of the three sub-pixels are electrically connected to the same data line.Type: GrantFiled: March 13, 2013Date of Patent: July 15, 2014Assignee: AU Optronics Corp.Inventors: Yi-Ching Chen, Yu-Sheng Huang, Chia-Wei Chen, Chun-Ru Huang
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Patent number: 8779437Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.Type: GrantFiled: August 22, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8779438Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.Type: GrantFiled: August 7, 2012Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
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Patent number: 8779439Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.Type: GrantFiled: February 13, 2012Date of Patent: July 15, 2014Assignee: Hyundai Motor CompanyInventors: Kyoung Kook Hong, Jong Seok Lee
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Patent number: 8779440Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.Type: GrantFiled: January 7, 2013Date of Patent: July 15, 2014Assignee: Infineon Technologies AGInventor: Martin Henning Albrecht Vielemeyer