Abstract: Disclosed is a semiconductor light emitting element (1) which is provided with: a laminated semiconductor layer which is formed on a substrate, and in which a first semiconductor layer having a first conductivity type, a light emitting layer, and a second semiconductor layer having a second conductivity type different from the first conductivity type; a first electrode (first electrode (170)) which is formed on a surface of the first semiconductor layer in the laminated semiconductor layer, and has a first opening (170a) used for electrical connection with an outside; and a second electrode (second electrode (180)) which is formed on a surface of the second semiconductor layer, and has a second opening (180a) used for electrical connection with the outside. The surface of the second semiconductor layer is exposed by cutting off a part of the laminated semiconductor layer.

Abstract: An LED module comprises an LED and a lens matching with the LED. The lens comprises a light-guiding portion and a plurality of retaining portions protruded from the light-guiding portion. The LED includes a substrate, a first electrode and a second electrode mounted on the substrate. A plurality of through holes is defined in the first electrode and a second electrode, respectively. Each retaining portion includes a rugged portion. The retaining portions are inserted into the through holes correspondingly, and the rugged portion abuts the substrate. Glue is applied between the rugged portion and the substrate.

Abstract: A sensor package is provided having a light sensitive component and a light emitting component attached to a same substrate. Light from the light emitting component is emitted from the package through a first opening and reflected back into the package to the light sensitive component through a second opening in the package. A glass attachment is placed between the light emitting component and the light sensitive component. A portion of the glass is removed and filled with an opaque substance to prevent light travelling between the light emitting component and the light sensitive component in the package.

Abstract: An L.E.D. lamp assembly (20) includes an electrically insulative coating (24) disposed on a thermally conductive substrate (22). A plurality of light emitting diodes (26) are secured to the coating (24) and a circuit (40) is adhesively secured to the coating (24) in predetermined spaced lengths (42) along the coating (24) to establish discrete and electrically conductive spaced lengths (42) with the light emitting diodes (26) disposed between the spaced lengths (42). LED electrical leads (32) are secured to the spaced lengths (42) of the circuit (40) to electrically interconnect the light emitting diodes (26). The circuit (40) includes a foil tape (46) having an electrically conductive tape portion (48) and a coupling portion (50) disposed on the tape portion (48) for securing the foil tape (46) to the insulated substrate (22).

Abstract: A light emitting diodes (LEDs) is presented. The LED includes a stress-alleviation layer on a substrate. Open regions and stress-alleviation layer regions are formed on the substrate. Epitaxial layers are disposed on the substrate, at least in the open regions therein, thereby forming an LED structure. The substrate is diced through at least a first portion of the stress-alleviation regions, thereby forming the plurality of LEDs.

Abstract: A light emitting device package according to the embodiment includes a body having a cavity; at least one light emitting device in the cavity; a resin member filled in the cavity while covering the light emitting device; and a fluorescence sheet coupled with a top surface of the body such that the fluorescence sheet is physically separable from the top surface of the body, and including a fluorescence material for converting light emitted from the light emitting device into another light.

Abstract: The present application discloses a semiconductor light-emitting device with a protection layer. The structure includes a heat dispersion substrate, a first connecting layer on the heat dispersion substrate, a protection layer on the first connecting layer, a second connecting layer on the protection layer, and a light-emitting unit on the second connecting layer. The protection layer is highly insulative and can avoid the current leakage forming between the light-emitting unit and the heat dispersion substrate.

Abstract: The invention relates to an illumination system comprising 1) a light source arranged to emit primary radiation, 2) a radiation converting element arranged to convert at least part of the primary radiation into secondary radiation, and 3) a filter arranged to block radiation generated in the illumination system having a wavelength shorter than a certain cut-off wavelength. According to the invention, the filter is designed to block a part of the secondary radiation by having arranged the cut-off wavelength of the filter in the emission spectrum of the radiation converting element. Illumination devices according to this design show emission spectra with small bandwidth.

Abstract: An LED array having N light-emitting diode units (N?3) comprises a permanent substrate, a bonding layer on the permanent substrate, a second conductive layer on the bonding layer, a second isolation layer on the second conductive layer, a crossover metal layer on the second isolation layer, a first isolation layer on the crossover metal layer, a conductive connecting layer on the first isolation layer, an epitaxial structure on the conductive connecting layer, and a first electrode layer on the epitaxial structure. The light-emitting diode units are electrically connected with each other by the crossover metal layer.

Abstract: Disclosed is a light-emitting device including a support member, a reflective layer on the support member, a light-transmitting electrode layer on the reflective layer, a light-emitting structure on the light-transmitting electrode layer, the light-emitting structure being provided with a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, and a luminescence layer interposed between the reflective layer and the light-transmitting electrode layer. Accordingly, the luminescence layer is formed in the chip formation process to minimize non-uniform application of a phosphor composed of an epoxy resin and simplify fabrication of the light-emitting device.

Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

Abstract: A light-emitting element that has an improved light-extraction efficiency and an improved color purity of an emitted light. A light-emitting element includes a reflective electrode, a transparent electrode, a light-emitting layer, a functional layer, and a color filter. An optical film thickness of the functional layer is from approximately 218 nm to approximately 238 nm for a light emitting element that emits a blue light. An optical film thickness of the functional layer is from approximately 384 nm to approximately 400 nm for a light emitting element that emits a red light.

Abstract: The present invention provides a light emitting element which emits linearly polarized light, has high efficiency, can show a higher luminance and has also adequate productivity.

Abstract: The present invention provides a semiconductor light-emitting device that emits light with a specific low correlated color temperature and with a high Ra, and a semiconductor light-emitting system provided with the semiconductor light-emitting device. This object is attained by the semiconductor light-emitting device having the below-described configuration. A semiconductor light-emitting device includes a LED chip as a semiconductor light-emitting element, and a phosphor emitting light using the LED chip as an excitation source, and emits light with a correlated color temperature equal to or higher than 1600 K and lower than 2400 K. The phosphor includes at least a green phosphor and a red phosphor. In the spectrum of light emitted from the semiconductor light-emitting device, the value of the peak intensity of the light emitted by the LED chip is less than 60% of the maximum peak intensity of the light emitted by the phosphor.

Abstract: An LED device having plasmonically enhanced emission is provided. The device includes an inverted LED structure with a coating of metal nanoparticles on the surface chosen to match the plasmonic response to the peak emission from the active quantum well (QW) emission region of the LED. The active QW emission region is separated from the metal nanoparticles on the surface by a thin n-type contact layer disposed on a top side of the active QW emission. A p-type layer is disposed immediately beneath the active QW emission region and injects holes into the active QW emission region. The n-type contact layer is sufficiently thin to permit a coupling of the surface plasmons (SPs) from the metal nanoparticles and the excitons in the active QW emission region. The SP-exciton coupling provides an alternative decay route for the excitons and thus enhances the photon emission from the LED device.

Abstract: An electrode structure includes at least two first electrodes and at least two second electrodes configured to be electrically connected in parallel to a power supply. Each of the first electrodes includes at least one first pad and at least one first extending wire with one end connected to the first pad, and the at least two first electrodes are spaced apart from each other. Each of the second electrodes includes at least one second pad and at least one second extending wire with one end connected to the second pad, and the at least two second electrodes are spaced apart from each other.

Abstract: A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, an upper electrode, and a lower electrode. The active layer is sandwiched between the first semiconductor layer and the second semiconductor layer. The lower electrode is electrical connected with the first semiconductor layer, and the upper electrode is electrical connected with the second semiconductor layer. A surface of the second semiconductor layer away from the active layer is used as the light extraction surface. A surface of the first semiconductor layer connected with the lower electrode is a patterned surface comprising a plurality of grooves.

Abstract: An LED unit includes a housing accommodating a wiring substrate mounted an LED, the housing including a light projecting portion for projecting light emitted from the LED, and wiring lines electrically connected to the wiring substrate. First and second lead-out portions, for leading out the wiring lines, are respectively provided at opposite end portions of the housing along a specified direction when seen in a plan view. First and second attachment portions for attaching the housing are respectively provided in the opposite end portions of the housing along the specified direction. The first and second lead-out portions are arranged at the opposite sides from each other with respect to a centerline of the housing extending along the specified direction. The first and second attachment portions are respectively arranged at the opposite sides from the first and second lead-out portions with respect to the centerline of the housing.

Abstract: An embodiment discloses a light source unit including a first terminal, a first semiconductor layer supporting the first terminal, a second semiconductor layer surrounding the first terminal, and a second terminal electrically connected to the second semiconductor layer and not surrounding the first terminal.

Abstract: A light emitting diode (LED) package comprises a LED, and a lead frame electrically connected to the LED. The lead frame includes a notch which has a predetermined size and a predetermined shape configured to separate a solder paste into two regions on either side of the notch when the solder paste is disposed on the lead frame.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: A sapphire substrate having one principal surface on which a nitride semiconductor is grown, said one principal surface having a plurality of projections. Each of the projections has a generally pyramidal shape with a not truncated, more sharpened tip and with an inclined surface composed of a crystal growth-suppression surface that lessens or suppresses the growth of the nitride semiconductor and also which has an inclination change line at which an inclination angle discontinuously varies.

Abstract: A structure for starting a semiconductor component including a porous silicon layer in the upper surface of a semiconductor substrate. This porous silicon layer is contacted, on its upper surface side, by a metallization and, on its lower surface side, by a heavily-doped semiconductor region.

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: An ESD protection device is manufactured such that its ESD characteristics are easily adjusted and stabilized. The ESD protection device includes an insulating substrate, a cavity provided in the insulating substrate, at least one pair of discharge electrodes each including a portion exposed in the cavity, the exposed portions being arranged to face each other, and external electrodes provided on a surface of the insulating substrate and connected to the at least one pair of discharge electrodes. A particulate supporting electrode material having conductivity is dispersed between the exposed portions of the at least one pair of discharge electrodes in the cavity.

Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes. an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.

Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.

Abstract: Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

Abstract: A semiconductor device, comprising: a substrate; a plurality of gate finger electrodes which are arranged on the substrate; a plurality of source finger electrodes which are arranged on the substrate, each source finger electrode is close to the gate finger electrode; a plurality of drain finger electrodes which are arranged on the substrate, each drain finger electrode faces the source finger electrode via the gate finger electrode; a shield plate electrode which is arranged via an insulating layer over the drain finger electrode and the first surface of the substrate between the gate finger electrode and the drain finger electrode, is short-circuited to the source finger electrode, and shields electrically the gate finger electrode and the drain finger electrode from each other; and a slot VIA hole which is formed in the substrate under the source finger electrode and is connected to the source finger electrode.

Abstract: Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0<x1?1, 0?y1?1), the second semiconductor crystal layer is made of Inx2Ga1-x2Asy2P1-y2 (0?x2?1, 0?y2?1, y2?y1), and the electron affinity Ea1 of the first semiconductor crystal layer is lower than the electron affinity Ea2 of the second semiconductor crystal layer.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: The electric device (1, 100) has a body (2, 101) with a resistor (7, 250) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 250) has an electric resistance which depends on whether the phase change material is in the first phase or the second phase. The resistor (7, 250) is able to conduct a current for enabling a transition from the first phase to the second phase. The phase change material is a fast growth material which may be a composition of formula Sb1?cMc with c satisfying 0.05?c?0.61, and M being one or more elements selected from the group of Ge, In, Ag, Ga, Te, Zn and Sn, or a composition of formula SbaTebX100?(a+b) with a, b and 100?(a+b) denoting atomic percentages satisfying 1?a/b?8 and 4?100?(a+b)?22, and X being one or more elements selected from Ge, In, Ag, Ga and Zn.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract: A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.

Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

Abstract: Provided are a photosensor, a photosensor apparatus including the photosensor, and a display apparatus including the photosensor apparatus. The photosensor includes a substrate; a first light receiving layer which is formed on the substrate and comprises an oxide; a second light receiving layer which is connected to the first light receiving layer and comprises an organic material; and first and second electrodes which are respectively connected to the first and second light receiving layers.

Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide later is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.

Abstract: Provided is a semiconductor device having good properties. Particularly, the semiconductor device is provided which can improve imaging properties. The semiconductor device (CMOS image sensor) includes a plurality of pixels, each having a photodiode PD for generating a charge by receiving light, and a transfer transistor TX for transferring the charge generated by the photodiode PD. The semiconductor device further includes an active region AcTP with the photodiode, and an active region AcG located on an upper side of the region AcTP in the planar direction and having a contact Pg to which a ground potential is applied. A gettering region GET is disposed in the active region AcG.

Abstract: Electronic devices may be provided with imaging modules that include plasmonic light collectors. Plasmonic light collectors may be configured to exploit an interaction between incoming light and plasmons in the plasmonic light collector to alter the path of the incoming light. Plasmonic light collectors may include one or more spectrally tuned plasmonic image pixels configured to preferentially trap light of a given frequency. Spectrally tuned plasmonic image pixels may include plasmonic structures formed form a patterned metal layer over doped silicon layers. Doped silicon layers may be interposed between plasmonic structures and a reflective layer. Plasmonic image pixels may be used to absorb and detect as much as, or more than, ninety percent of incident light at wavelengths ranging from the infrared to the ultraviolet. Plasmonic image pixels that capture light of different colors may be arranged in patterned arrays to form imager modules or imaging spectrometers for optofluidic microscopes.

Abstract: An image sensor includes a plurality of color filters and an anti-reflective layer. The color filters are located on a substrate. The anti-reflective layer is located between the substrate and the color filters, and parts of the anti-reflective layer corresponding to at least two of the color filters have different thicknesses. Moreover, an image sensing process including the following steps is also provided. An anti-reflective layer is formed on a substrate. A plurality of color filters is formed on the anti-reflective layer, wherein parts of the anti-reflective layer right below at least two of the color filters have different thicknesses.

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract: A ferroelectric capacitor includes a ferroelectric film, a lower electrode in contact with one surface of the ferroelectric film, and an upper electrode in contact with the other surface of the ferroelectric film. At least one of the upper electrode and the lower electrode has a stacked electrode structure in which one or more oxide conductive layers and one or more metal layers are stacked alternately, and the stacked electrode structure includes at least one of two or more oxide conductive layers and two or more metal layers.

Abstract: A Dynamic Random Access Memory (DRAM) device can include a semiconductor substrate that includes an active region including a source region therein. A gate line can cross the active region and a first contact plug can be on the active region adjacent to the gate line and can be connected to the source region. A conductive layer can be on the first contact plug to expose a portion of the first contact plug and a capacitor storage node electrode can be on the conductive layer.

Abstract: In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.

Abstract: A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Abstract: A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.