Abstract: A unit pixel of an image sensor includes a photoelectric conversion region, a floating diffusion region, and a transfer gate. The photoelectric conversion region is in an active region defined by an isolation region of a semiconductor substrate. The photoelectric conversion region generates electric charges corresponding to incident light. The transfer gate transfers the electric charges to the floating diffusion region, which is located in the active region.

Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.

Abstract: In a TDI-type linear image sensor in which pixels are constituted of CCDs (Charge Coupled Devices) of n phases (n being an integer not smaller than 3), a gate opening portion and a gate non-opening portion functioning as a TDI transfer channel (15) are formed in all of transfer gates of the CCDs of n phases constituting the pixels. Within one pixel pitch in a TDI transfer direction, n microlenses (18) are formed such that light is concentrated at the gate non-opening portion formed at the transfer gate of each phase.

Abstract: An apparatus includes a device substrate including an array of sensors. Each sensor of the array of sensors can include a electrode structure disposed at a surface of the device substrate. The apparatus further includes a wall structure overlying the surface of the device substrate and defining an array of wells at least partially corresponding with the array of sensors. The well structure including an electrode layer and an insulative layer.

Abstract: CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

Abstract: Disclosed are a method to fabricate a semiconductor device having a two-layered gate structure, and so fabricated a semiconductor. The gate threshold voltage can be tuned by using two metal layers with different workfunctions, disposed over a fin structure on a substrate and extending in parallel to the current flow direction in the fin structure, and by varying individual thicknesses of the layer so as to change the relative coverage of the fin structure by the layers. The method may comprise providing a substrate having a fin structure, depositing first and second gate metals, and forming a gate dielectric layer. The method may further comprise determining the workfunctions of the first and second gate metals and their thicknesses to achieve a desired gate threshold voltage. Forming the first and second gate metal layers and the dielectric layer may use processes such as deposition, epitaxial growth, CMP, or selective etching.

Abstract: Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract: A method of fabricating an integrated circuit includes forming an interlayer dielectric (ILD) layer over a dummy gate stack. The dummy gate stack includes a dummy gate structure, a hardmask layer, and sidewall spacers formed over a semiconductor substrate. The method further includes removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, and depositing at least one workfunction material layer within the first opening and within the first extended opening. Still further, the method includes removing portions of the workfunction material within the first opening and depositing a low-resistance material over remaining portions of the workfunction material thereby forming a replacement metal gate structure that includes the remaining portion of the workfunction material and the low-resistance material.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

Abstract: There is provided a back-illuminated type solid-state image pickup unit, in which a pad wiring line is provided on a light reception surface, capable of improving light reception characteristics in a photoelectric conversion section by thinning an insulating film in the back-illuminated type solid-state image pickup unit. A solid-state image pickup unit according to the present technology to accomplish such a purpose includes a sensor substrate having a pixel region in which photoelectric conversion sections are formed in an array, and a drive circuit is provided on a surface opposed to a light reception surface for the photoelectric conversion sections of the sensor substrate. Moreover, a through hole via reaching the drive circuit from the light reception surface of the sensor substrate is provided in a peripheral region located outside the pixel region. Further, a pad wiring line directly laminated on the through hole via is provided on the light reception surface in the peripheral region.

Abstract: A planar STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states either parallel or anti-parallel to the fixed reference layer magnetization through a set/reset current pulse along a conductive line provided by a control circuitry, accordingly, the magnetoresistive element is pre-configured into a reading mode having canceled spin-transfer torques or a recording mode having additive spin-transfer torques.

Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

Abstract: A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall.

Abstract: In a nonvolatile memory device and a method for fabricating the same, a device comprises a substrate, a trench in the substrate and a first gate pattern comprising a first bottom gate electrode having a first portion in the trench and having a second portion on the first portion and protruding in an upward direction relative to an upper surface of the substrate. A second gate pattern comprising a second gate electrode is on the substrate at a side of the first gate pattern and insulated from the first gate pattern. An impurity region is present in the substrate at a side of the first gate pattern opposite the second gate pattern, and overlapping part of the trench.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A charge-trap type flash memory device having a low-high-low energy band as a trapping layer embeds Al2O3 between Si3N4 and HfO2 as a CT layer. Most injected charged can be trapped at an interface of Si3N4/Al2O3. Al2O3 can also provide a high blocking effect for electronic dissipation. Therefore this invention can enhance the writing and retention characteristics for CT VNM.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.

Abstract: An integrated circuit may include a semiconductor portion with a power transistor including first gate trenches that cross a first region and a sense transistor including second gate trenches that cross a second region. Each gate trench extends in a longitudinal direction and comprises a gate electrode and a field electrode. The first and second regions are arranged along the longitudinal direction. A first termination trench intersects at least the second gate trenches in a third region between the first and second regions. The first termination trench includes a first conductive structure that is electrically connected to the field electrodes in the second gate trenches. The characteristics of the sense transistor formed in the second region reliably and precisely replicate the characteristics of the power transistor.

Abstract: To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches. The active area trenches and termination trenches include a trench dielectric liner and electrically conductive filler material filled field plates. A gate is over the drain drift region between active area trenches. A body region of a second conductivity abuts the active region trenches. A source of the first conductivity type is in the body region on opposing sides of the gate. A vertical drain drift region uses the drift region below the body region. A first and second curved trench feature couples the field plate of the first and second termination trench to field plates of active area trenches.

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.

Abstract: A semiconductor device includes an epitaxial layer of semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the epitaxial layer from a main surface of the epitaxial layer, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the epitaxial layer from the main surface than a peak doping concentration of the device channel region.

Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract: A silicon-on-insulator (SOI) radio-frequency (RF) device is disclosed, the SOI RF device includes: a silicon substrate; a buried oxide layer formed on the silicon substrate; a device layer formed on the buried oxide layer, the device layer including an RF device; a first dielectric layer covering the device layer; a deep trench structure extending through, from the top downward, the first dielectric layer, the silicon device layer and the buried oxide layer to an interface between the buried oxide layer and the silicon substrate; and a second dielectric layer covering both of the first dielectric layer and the deep trench structure. The SOI RF device is capable of improving signal transmission characteristics and preventing signal distortion, and can be easily manufactured with lower cost in less critical process conditions. A method of forming such an SOI RF device is also disclosed.

Abstract: FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide.

Abstract: A method of fabricating a semiconductor device is disclosed. The exemplary method includes providing a substrate including a device layer and a sacrificial layer formed over the device layer and patterning the sacrificial layer thereby defining a cut pattern. The cut pattern of the sacrificial layer having an initial width. The method further includes depositing a mask layer over the device layer and over the cut pattern of the sacrificial layer. The method further includes patterning the mask layer thereby defining a line pattern including first and second portions separated by the cut pattern of the sacrificial layer and selectively removing the cut pattern of the sacrificial layer thereby forming a gap that separates the first and second portions of the line pattern of the mask layer. The method further includes patterning the device layer using the first and second portions of the line pattern of the mask layer.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. An oxide layer is formed over the SOI layer. At least one first set and at least one second set of fins are patterned in the SOI layer and the oxide layer. A conformal gate dielectric layer is selectively formed on a portion of each of the first set of fins that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer over the portion of each of the first set of fins that serves as the channel region of the transistor device. A second metal gate stack is formed on a portion of each of the second set of fins that serves as a channel region of a diode device.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: Provided is a semiconductor device which uses a comb-like N-type MOS transistor as an ESD protection element and is capable of uniformly operating the entire comb-like N-type MOS transistor. By adjusting a length L of a gate electrode of the N-type MOS transistor used as the ESD protection element in accordance with the distance from a contact for fixing a substrate potential, which is provided on a guard ring around an outer periphery, respective portion of N-type MOS transistor represented as a comb teeth uniformly enter snap-back operation, permitting avoidance of local concentration of current and obtainment of a desired ESD tolerance.

Abstract: An ESD protection circuit having a smaller area is provided. The ESD protection circuit includes: a P-type diffusion resistor 12 whose one end is connected to an input terminal 11 formed in the N-type well; a diode 14 disposed between the diffusion resistor 12 and the N-type well connected to the power supply terminal; an NMOS transistor 15 whose drain is connected to the other end of the diffusion resistor 12; and a parasitic diode formed between the power supply terminal and the ground terminal.

Abstract: A method of forming an integrated circuit comprises forming at least one gate electrode of at least one active transistor, and at least one first dummy gate electrode. The method also comprises forming a first doped region disposed in the substrate and adjacent to a first side wall of the at least one first dummy gate electrode, wherein the first doped region has a first conductivity type dopant. The method further comprises forming a second doped region disposed in the substrate and adjacent to a second side wall of the at least one first dummy gate electrode. The second doped region has a second conductivity type dopant that is opposite to the first conductivity type dopant.

Abstract: A first cell having a cell height N times as large as a reference cell height (N is an integer equal to or more than 2) is adjoined by a second cell in the cell width direction. A diffusion interconnect made of an impurity diffusion region is formed under a metal interconnect for power supply in the second cell. The first cell includes a transistor diffusion region formed, opposed to the diffusion interconnect, so as to stride across a region extended in the cell with direction of the metal interconnect. The diffusion interconnect is placed apart from the cell boundary in the cell width direction.

Abstract: A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

Abstract: According to embodiments, there is provided a semiconductor device, including: a first area including plural transistors formed therein; and a second area including plural dummy transistors formed therein, the second area surrounding the first area, wherein a pitch of the dummy transistors is equal to or less than a central wavelength of a light used to form the transistors.

Abstract: A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Abstract: A transistor device comprising epitaxial LDD and Halo regions and a method of manufacturing the same are disclosed.

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract: An encapsulated MEMS device includes stress-relief trenches in a region of its substrate that surrounds the movable micromachined structures and that is covered by a cap, such that the trenches are fluidly exposed to a cavity between the substrate and the cap. A method of fabricating a MEMS device includes fabricating stress-relief trenches through a substrate and fabricating movable micromachined structures, and capping the device prior art encapsulating the device.

Abstract: A microphone structure is disclosed. The microphone structure comprises a substrate penetrated with at least one opening chamber and having an insulation surface. A conduction layer is arranged on the insulation surface and arranged over the opening chamber. An insulation layer is arranged on the conduction layer and having a opening to expose a part of the conduction layer as a vibration block arranged over the opening chamber. At least two first patterned electrodes are arranged on the insulation layer and arranged over the vibration block. At least two second patterned electrodes are arranged over the opening chamber, arranged on the vibration block and separated from the first patterned electrodes by at least two first gaps. When the vibration block vibrates, the vibration block moves the second patterned electrodes whereby the second patterned electrodes and the first patterned electrodes perform differential sensing.

Abstract: A housing for a semiconductor chip has an injection molded body, in which an accommodating area for accommodating the semiconductor chip is provided. The injection-molded body has at least one metallization for making electrical contact with the semiconductor chip.