Abstract: A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion.

Abstract: Disclosed herein are a method of improving sensitivity of a terrestrial magnetism sensor and an apparatus using the same. A method of forming a terrestrial magnetism sensor includes: cleaning a surface of the terrestrial magnetism sensor; and depositing a thermoelectric material as a thin film on the cleaned surface of the terrestrial magnetism sensor. Therefore, a sensing error of the terrestrial magnetism sensor that has been generated due to heat in the prior art is decreased, thereby making it possible to allow the terrestrial magnetism sensor to calculate an accurate sensing value.

Abstract: A perpendicular magnetoresistive element comprises anovel buffer layer provided on a surface of the recording layer, which is opposite to a surface of the recording layer where the tunnel barrier layer is provided, wherein at least the portion of the buffer layer interfacing to the recording layer contains a rocksalt crystal structure having the (100) plane parallel to the substrate plane and at least a portion of the buffer layer comprises a doped element having conductivity enhancement and the perpendicular resistance of the buffer layer is relatively small than that of the tunnel barrier layer.

Abstract: A STT-MRAM comprises a method to form magnetic random access memory (MRAM) element array having ultra small dimensions using double photo exposures and etch of their hard masks. The memory cells are located at the cross section of two ultra-narrow photo-resist lines suspended between two large photo-resist bases. Array of MRAM cells with small dimension is formed by a third magnetic etch.

Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract: An integrated magnetic sensor formed by a semiconductor chip having a surface and accommodating a magnetic via and a sensing coil. The magnetic via is formed by a cylindrical layer of ferromagnetic material that extends perpendicular to the surface of the first chip and has in cross-section an annular shape of a circular or elliptical or curvilinear type. The sensing coil surrounds the magnetic via at a distance and is connected to an electronic circuit.

Abstract: A magnetic miniaturized memory element with improved thermal stability of magnetization includes a first magnetic layer, an insulating layer that is formed on the first magnetic layer, a second magnetic layer that is formed on the insulating layer, and an expanded interlayer insulating film that comes into contact with side surfaces of the first and second magnetic layers, where at least one of the first magnetic layer and the second magnetic layer is strained and deformed so as to be elongated in an easy magnetization axis direction of the first magnetic layer or the second magnetic layer or compressive strain remains in any direction in the plane of at least one of the first magnetic layer and the second magnetic layer.

Abstract: Conductive layer(s) in a thin film photovoltaic (TFPV) panel are divided by first scribe curves into photovoltaic cells connected in series. At least one of the layers is scribed to isolate a shunt defect in a cell from parts of that cell away from the defect. The isolation scribes can substantially follow or parallel current-flow lines established by the design of the panel. A TFPV panel can be altered by, using a controller, automatically locating a shunt defect and scribing at least one of the conductive layers along two spaced-apart second scribe curves. Each second scribe curve can intersect the two first scribe curves that bound the cell with the defect. The two second scribe curves can be on opposite sides of the defect.

Abstract: A polarized light detection system includes a detection apparatus, a power source, and a photoresistor. The detection apparatus, power source and photoresistor are electrically connected with wires to form a galvanic circle. The photoresistor includes a photosensitive material layer with a first surface and a second surface opposite to each other, a first electrode layer located on the first surface of the photosensitive material layer, and a second electrode layer located on the second surface of the photosensitive material layer. The first electrode layer includes a carbon nanotube film structure.

Abstract: A photonic integrated circuit (I/C) includes a focusing sidewall or in-plane surface that redirects and focuses light from a waveguide to a photodetector structure. The focusing includes redirecting an optical signal to a width smaller than a width of the waveguide. The focusing of the light allows the photodetector structure to be outside a waveguide defined by parallel oxide structures. With the photodetector structure outside the waveguide, the contacts can be placed closer together, which reduces contact resistance.

Abstract: A solid-state image sensor includes a structure having a semiconductor layer in which a plurality of photoelectric converters are arranged, a light blocking member arranged above a face of the structure and including a plurality of circular openings each corresponding to at least one of the photoelectric converters, a first layer configured to cover the light blocking member, and exposed portions of the face of the structure, that are formed by the plurality of circular openings, and a second layer arranged to cover the first layer and having a refractive index higher than that of the first layer, wherein an interface between the first layer and the second layer includes lens faces protruding toward the exposed portions.

Abstract: A semiconductor device comprising a semiconductor substrate with a plurality of photo-diodes arranged in the semiconductor substrate with interconnect layers defining apertures at the photo-diodes and a first polymer which fills the gaps such as to cover the photo-diode. Further, layers of color filters are arranged on top the gap filling polymer layer opposite to the photo-diodes and a second polymer arranged on the interconnect layers covers and planarizes and passivates the color filter layers. On top of the planarizing polymer there is a plurality of micro-lenses opposite to the color filters, and a third polymer layer is deposited on the micro-lenses for passivating the micro-lenses. According to the invention the polymer materials are comprised of a siloxane polymer which gives thermally and mechanically stable, high index of refraction, dense dielectric films exhibiting high-cracking threshold, low pore volume and pore size.

Abstract: A fully depleted “diode passivation active passivation architecture” (DPAPA) produces a photodiode structure which includes a substrate, a highly-doped buffer layer of a first carrier doping type above the substrate, a low-doped or undoped semiconductor active layer of the first carrier doping type above the buffer layer, a low-doped or undoped passivation layer above the active layer, the passivation layer having a wider band gap than the active layer; and a junction layer of a carrier doping type opposite the first carrier doping type above the passivation layer such that a pn junction is formed between the junction layer and the passivation and active layers, the junction creating a depletion region which expands completely through the passivation and active layers in response to a reverse bias voltage. The fully depleted structure substantially eliminates Auger recombination, reduces dark currents and enables cryogenic level performance at high temperatures.

Abstract: A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Abstract: A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other.

Abstract: The invention relates to an InGaAs photodiode army (101) and to the method for manufacturing same, wherein said array includes: a cathode including at least one indium-phosphide substrate layer (4) and an active gallium-indium arsenide layer (5); and a plurality of anodes (3) at least partially formed in the active gallium-indium arsenide layer by diffusing a P-type dopant, the interaction between an anode (3) and the cathode forming a photodiode. According to said method, an indium-phosphide passivation layer (6) is arranged on the active layer before the diffusion of the P-type dopant forming the anodes (3), and a first selective etching is performed so as to remove, over the entire thickness thereof, an area (10) of the passivation layer (6) surrounding each anode (3).

Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.

Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.

Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

Abstract: Semiconductor die packaged with air core inductors (ACIs) and magnetic core inductors (MCIs), or with multiple MCIs, are described. In a first example, a semiconductor package includes a semiconductor die, one or more air core inductors (ACIs) coupled to the semiconductor die, and one or more magnetic core inductors (MCIs) coupled to the semiconductor die. In a second example, a semiconductor package includes a semiconductor die, a first magnetic core inductor (MCI) coupled to the semiconductor die and having a first saturation current, and a second MCI coupled to the semiconductor die and having a second, different, saturation current.

Abstract: A semiconductor device includes a substrate, a metal film on a portion of the substrate, a first dielectric film having a first portion on the metal film and a second portion on the substrate, the second portion being integral with the first portion, a lower electrode on the first portion, a second dielectric film having a first portion on the lower electrode and a second portion on the first dielectric film, the second portion of the second dielectric film being integral with the first portion of said second dielectric film, an upper electrode on a portion of the second dielectric film, and a reinforcing film disposed on the second dielectric film and in contact with a side of the upper electrode.

Abstract: Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation structure is formed in a substrate to define a boundary for a device region. A collector is formed in the device region, and a second isolation structure is formed in the device region. The second isolation structure defines a boundary for the collector. The second isolation structure is laterally positioned relative to the first isolation structure to define a section of the device region between the first and second isolation structures.

Abstract: A variable capacitance device includes a fixed substrate, a movable portion, driving electrodes, an RF capacitance electrode and an insulating film. The movable portion faces the fixed substrate and can change a gap between the movable portion and the fixed substrate. The driving electrodes are formed on the fixed substrate so as to face the movable portion. The RF capacitance electrode is formed on the fixed substrate so as to face the movable portion and be spaced apart from the driving electrodes. The insulating film is formed between the movable portion and the driving electrodes. The level of a voltage applied to the driving electrodes and the level of a voltage applied to the movable portion are periodically switched and the level of a voltage applied to the RF capacitance electrode and the level of a voltage applied to the movable portion are always the same.

Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.

Abstract: A crystal laminate structure, in which crystals can be epitaxially grown on a ?-Ga2O3-based substrate with high efficiency to produce a high-quality ?-Ga2O3-based crystal film on the substrate; and a method for producing the crystal laminate structure are provided. The crystal laminate structure includes: a ?-Ga2O3-based substrate, of which the major face is a face that is rotated by 50 to 90° inclusive with respect to face; and a ?-Ga2O3-based crystal film which is formed by the epitaxial crystal growth on the major face of the ?-Ga2O3-based substrate.

Abstract: A semiconductor device according to the present embodiment includes a semiconductor substrate. A plurality of line patterns are formed into stripes present above the semiconductor substrate. Each of the line patterns includes a narrow portion having a constricted width in a perpendicular direction to an extension direction of the line pattern.

Abstract: Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

Abstract: A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

Abstract: A semiconductor element includes a substrate and a semiconductor layer. The substrate has a first main face and a second main face. The semiconductor layer is formed on a side of one of the first main face and the second main face of the substrate. The substrate has a plurality of isolated processed portions and an irregularity face that runs from the processed portions at least to the first main face of the substrate and links adjacent ones of the processed portions.

Abstract: A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion.

Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.

Abstract: A power semiconductor device includes a semiconductor substrate, an active device region disposed in the semiconductor substrate, an edge termination region spaced laterally outward from the active device region in the semiconductor substrate, and first and second trenches. The first trench is disposed in the edge termination region and has an inner sidewall, an outer sidewall and a bottom, the inner sidewall being spaced closer to the active device region than the outer sidewall. The second trench is spaced laterally outward from the first trench in the edge termination region, and extends further into the semiconductor substrate than the first trench and has a sidewall which outwardly faces the outer sidewall of the first trench and is doped opposite as the inner sidewall and bottom of the first trench.

Abstract: A multifunction semiconductor package structure includes a substrate unit, a circuit unit, a support unit, a semiconductor unit, a package unit and an electrode unit. The substrate unit includes a substrate body and a first electronic element having a plurality of conductive contact portions. The circuit unit includes a plurality of first conductive layers disposed on the substrate body. The semiconductor unit includes a plurality of second electronic elements. Each second electronic element is electrically connected between two corresponding first conductive layers. The package unit includes a package body disposed on the substrate body to enclose the second electronic elements. The electrode unit includes a plurality of top electrodes, a plurality of bottom electrodes, and a plurality of lateral electrodes electrically connected between the top electrodes and the bottom electrodes.

Abstract: There is disclosed a package comprising at least an integrated circuit embedded in an electrically non-conductive moulded material. The moulded material includes at least one moulded pattern on at least one surface thereof, and at least one electrically conductive track in the pattern. There is further provided at least one capacitive, inductive or galvanic component electrically connecting between at least two parts of the at least one electrically conductive track. The conductive track can be configured as antenna, and the capacitive, inductive or galvanic component is used to adjust tuning and other characteristics of the antenna.

Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.

Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.

Abstract: A semiconductor package includes a semiconductor chip, a protruding pillar electrode provided on the semiconductor chip, and resin covering the semiconductor chip and the pillar electrode. The resin has a concave part and exposes a front edge portion of the pillar electrode from the resin at the bottom face of the concave part. The front edge portion of the pillar electrode is exposed from the concave part of the resin, which makes it possible to suppress increase in the height of the pillar electrode and to form the pillar electrodes having fine patterns or a narrow pitch.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: A semiconductor device according to the present invention includes a plurality of semiconductor chips, a plate electrode disposed on the plurality of semiconductor chips for connecting the plurality of semiconductor chips, and an electrode disposed on the plate electrode. The electrode has a plurality of intermittent bonding portions to be bonded to the plate electrode and a protruded portion which is protruded erectly from the bonding portions. The protruded portion has an ultrasonic bonding portion which is parallel with the bonding portion and is ultrasonic bonded to an external electrode.

Abstract: A transistor outline housing is provided that has bonding wires on an upper surface. The bonding wires are reduced in length and have connection leads with an excess length at an end opposite the bonding end.

Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract: Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Abstract: A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.