Abstract: Methods of forming a material include exposing a substrate to a first germanium-containing compound and a second, different germanium-containing compound; exposing the substrate to a first antimony-containing compound and a second, different antimony-containing compound; and exposing the substrate to a first tellurium-containing compound and a second, different tellurium-containing compound. Methods of forming chalcogenide materials include exposing a substrate to a first precursor comprising a reactive precursor of a first metal and a co-reactive precursor of the first metal, the reactive precursor and the co-reactive precursor each having at least one ligand coordinated to an atom of the first metal, wherein the at least one ligand of the co-reactive precursor is different from the at least one ligand of the reactive precursor. The substrate is also exposed to a reactive antimony precursor and a co-reactive antimony precursor and to a reactive tellurium precursor and a co-reactive tellurium precursor.

Abstract: Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.

Abstract: The present invention provides a polishing slurry capable of polishing even high-hardness materials such as silicon carbide and gallium nitride at a high polishing speed. The present invention is a polishing slurry including a slurry containing a manganese oxide particle and a manganate ion for polishing high-hardness materials having a Mohs hardness of 8 or higher. In the present invention, the manganese oxide particle in the slurry is preferably 1.0 mass % or more; the manganese oxide is preferably manganese dioxide; and the manganate ion is preferably permanganate ion. The polishing slurry according to the present invention enables even high-hardness hardly-machinable materials such as silicon carbide and gallium nitride to be polished smoothly at a high speed.

Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

Abstract: A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Abstract: Flip chip packaging methods, and flux head manufacturing methods used in the flip chip packaging methods may be provided. In particular, a flip chip packaging method including printing flux on a pad of a printed circuit board (PCB), mounting the die in a flip chip manner on the PCB such that a bump of the die faces the pad of the PCB, and bonding the bump of the die to the pad of the PCB using the flux may be provided.

Abstract: A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.

Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract: An adhesive composition for a pre-applied underfill sealant comprising: (a) a radical polymerizable monomer having one or more functional groups selected from the group consisting of vinyl group, maleimide group, acryloyl group, methacryloyl group and allyl group, (b) a polymer having a polar group, (c) a filler, and (d) a thermal radical initiator.

Abstract: A wafer and a method for forming the same are disclosed. The wafer forming method can separate respective chips from others by performing a Deep Reactive Ion Etching (DRIE) process on a wafer including a plurality of chips. The wafer includes a plurality of chips configured to be arranged in row and column directions on the wafer, a scribe line configured to be formed among the plurality of chips so as to separate each chip, and an align key line configured to be formed in one side of the wafer so as to form an align key pattern.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

Abstract: The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Abstract: A method of forming a semiconductor structure, the method includes epitaxially growing a second III-V compound layer on a first III-V compound layer. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. The method further includes forming a source feature and a drain feature on the second III-V compound layer, forming a third III-V compound layer on the second III-V compound layer, depositing a gate dielectric layer on a portion of the second III-V compound layer and a top surface of the third III-V compound layer, treating the gate dielectric layer on the portion of the second III-V compound layer with fluorine and forming a gate electrode on the treated gate dielectric layer between the source feature and the drain feature.

Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

Abstract: A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed.

Abstract: A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

Abstract: After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

Abstract: A method of manufacturing a super-junction semiconductor device is disclosed that allows forming a high concentration layer with high precision and improves the trade-off relationship between the Eoff and the dV/dt using a trench embedding method. The method comprises a step of forming a parallel pn layer using a trench embedding method and a step of forming a proton irradiated layer in the upper region of the pn layer. Then, heat treatment is conducted on the proton irradiated layer for transforming the protons into donors to form a high concentration n type semiconductor layer. Forming the high concentration n type semiconductor layer by means of proton irradiation allows forming a high concentration n type semiconductor layer with an impurity concentration and thickness with high precision as compared with forming the layer by means of an epitaxial growth process.

Abstract: A semiconductor process includes the following step. A stacked structure is formed on a substrate. A contact etch stop layer is formed to cover the stacked structure and the substrate. A material layer is formed on the substrate and exposes a top part of the contact etch stop layer covering the stacked structure. The top part is redressed.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: A metal-insulator-metal (MIM) capacitor and a method for forming the same are provided. The MIM capacitor includes an insulator on a bottom metal plate, a top metal plate on the insulator, a dielectric layer on the top metal plate and on at least sidewalls of the top metal plate and the insulator, and an anti-reflective coating (ARC) layer over the top metal plate and the bottom metal plate. The dielectric layer preferably extends on an exposed portion of the bottom metal plate not covered by the top metal plate and the insulator.

Abstract: The disclosure relates to a method of fabricating a semiconductor device including forming a patterned hardmask layer over a substrate comprising a major surface. The method further includes forming a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate. The plurality of first trenches have a first width and extend downward from the substrate major surface to a first height, and the plurality of second trenches have a second width less than first width and extend downward from the substrate major surface to a second height greater than the first height.

Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Abstract: A method of attaching first and second semiconductor devices to one another includes applying plating gel over a surface of a first semiconductor device, positioning bonding regions of a second semiconductor device in contact with the plating gel on corresponding bonding regions on the first semiconductor device, and reacting at least some the plating gel to bond the second semiconductor device to the first semiconductor device.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising: providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate on a carrier support to form a work piece; providing an intermediate ring interposed between the substrate and the frame; loading the work piece onto the work piece support; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step.

Abstract: The present disclosure relates to a method of transferring semiconductor elements from a non-flexible substrate to a flexible substrate. The present disclosure also relates to a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. The semiconductor elements grown or formed on a non-flexible substrate may be effectively transferred to a resin layer while maintaining an arrangement of the semiconductor elements. The resin layer may function as a flexible substrate for supporting the vertical semiconductor elements.

Abstract: The invention provides a reactor for the manufacture of silicon by chemical vapour deposition (CVD), the reactor comprises a reactor body that can rotate around an axis with the help of a rotation device operatively arranged to the reactor, at least one sidewall that surrounds the reactor body, at least one inlet for reaction gas, at least one outlet for residual gas and at least one heat appliance operatively arranged to the reactor. The reactor is characterised in that during operation for the manufacture of silicon by CVD, the reactor comprises a layer of particles on the inside of at least, one sidewall.

Abstract: The invention relates to a method for forming a graphene layer (105) on the surface of a substrate (100) including a silicon layer (101), the method comprising the consecutive steps of: forming (1) a silicon-carbide film (103) on a free surface of the silicon layer and gradually heating the substrate until the silicon of at least the first row of atoms of the silicon-carbide film is sublimated so as to form the graphene layer on the silicon-carbide film. According to the invention, a silicon layer, the free surface of which is stepped, is used.

Abstract: A method is disclosed for growing large grain to single crystalline semiconductor films on inexpensive glass substrates.

Abstract: According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.

Abstract: Disclosed is a photosensitive resin composition which exhibits positive or negative photosensitivity and is used as a mask in an ion implantation step, the photosensitive resin composition including, as a resin, (A) a polysiloxane. The photosensitive resin composition of the present invention has high heat resistance and is capable of controlling a pattern shape, and also has excellent ion implantation mask performance, thus enabling application to a low-cost high-temperature ion implantation process.

Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.

Abstract: A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; performing a heat treatment on the dielectric film; forming an electrode on a first region of the dielectric film; irradiating an ionized gas cluster to a second region of the dielectric film where the electrode is not formed; and removing the second region of the dielectric film where the ionized gas cluster is irradiated by a wet etching after the irradiating of the ionized gas cluster.

Abstract: A metal-containing film capable of adjusting a work function is formed. A first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and an amino group are alternately supplied onto a substrate having a high-k dielectric film to form a composite metal nitride film on the high-k dielectric film.

Abstract: A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer.

Abstract: A method for forming a semiconductor device is provided, which may include: providing an interlayer dielectric layer, a metal layer formed on the interlayer dielectric layer, an etch stop layer formed on the metal layer, and a first opening extending through the etch stop layer and the metal layer, wherein the interlayer dielectric layer is exposed from the first opening; forming a protecting layer on the sidewall of the first opening to cover the metal layer; after forming the protecting layer, forming a second opening by etching a portion of the interlayer dielectric layer; and forming an isolating layer by filling up the second opening, wherein the isolating layer includes an air gap. The semiconductor device is more stable in performance.

Abstract: According to one embodiment, a core material is ejected onto an object using an inkjet method to form a core pattern on the object, a mask pattern is formed on the object so as to embed the core pattern, and the core pattern which is embedded in the mask pattern is removed.

Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

Abstract: Sterically hindered imidazolate ligands are described, along with their synthesis, which are capable of coordinating to Group 2 metals, such as: calcium, magnesium, strontium, in an eta-5 coordination mode which permits the formation of monomeric or dimeric volatile complexes. A compound comprising one or more polysubstituted imidazolate anions coordinated to a metal selected from the group consisting of barium, strontium, magnesium, radium or calcium or mixtures thereof. Alternatively, one anion can be substituted with and a second non-imidazolate anion.

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract: A method of making a semiconductor assembly including the steps of: (i) providing an initial-state assembly including: (a) a fin layer, and (b) a hard mask layer located on top of at least a portion of the fin layer; (ii) performing a first material removal on the initial-state assembly, by CMP, to yield a second-state assembly; and (iii) performing a second material removal on the second-state assembly to yield a third-state assembly. In the first material-removal step: (i) any remaining portion of the soft sacrificial layer is removed, (ii) a portion of the fin layer is removed, and (iii) the lower portion of the hard mask layer is used as a stop layer for the second material removal.