Abstract: A converter includes an active stage for converting an AC input voltage at an AC input into an intermediate DC voltage, and a DC/DC converter for transforming the intermediate DC voltage into an output DC voltage at a DC output. The DC/DC converter has a resonant transformer formed by a resonant circuit and a transformer. The converter also includes control unit configured to actively operate the active stage only based on an output DC voltage of the DC/DC converter, an input voltage, and an input current of the converter, and to operate the DC/DC converter in an open loop mode. A method for operating such a converter is also provided.

Abstract: A matrix converter includes input terminals, output terminals, a power conversion circuit, and a snubber circuit. The power conversion circuit includes bidirectional switches of which each includes antiparallel connection circuits connected serially. The snubber circuit is connected to the bidirectional switches. The snubber circuit includes first diodes, a capacitor, a second diode, and third diodes. The first diodes are respectively corresponded to the bidirectional switches. A first connecting point of each the first diode is connected to a connection point between the two unidirectional switching elements constituting the bidirectional switch. A first connecting point of the capacitor is connected to a second connecting point of each the first diode. First and second connecting points of the second diode are connected to a second connecting point of the capacitor and the corresponding output terminal. The bidirectional switches, the first diodes, and the second diode are arranged in one power module.

Abstract: A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors can thus be eliminated, reducing the area and power consumption of the CAM cell. Sharing of the single pair of pull-down transistors is enabled by time-staggered pre-charge and compare operations such that the pre-charge interval of the first stack corresponds to the compare interval of the second stack, and vice versa.

Abstract: A ternary content addressable memory (TCAM) has at least one TCAM cell comprising first and second memory bitcells for storing first and second bit values representing a cell state comprising one of a first cell state, a second cell state and a mask cell state. The first and second memory bitcells share a pair of bitlines for accessing the first and second bit values. Access control circuitry is provided for triggering, in response to a clock signal, a read or write access to the first memory bitcell during a first portion of a clock cycle and triggering a read access or write access to the second read bitcell during a second portion of the clock cycle.

Abstract: Described is an apparatus which comprises: a memory cell with a data port; and a logic gate, coupled to the data port of the memory cell, to generate a data word-line signal according to data on the data port and an asynchronous word-line signal, wherein the logic gate is operable to gate data on the data port during low power mode.

Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A semiconductor storage device has a great number of logic circuits and fuse blocks with its space-saving design. In the semiconductor storage device, a plurality of fuse blocks is arranged in a line or row in the vicinity of a gate array. Each fuse block includes a plurality of fuse pieces arranged in a juxtaposed manner and exposed to the exterior through a fuse window. A power-supply wire and a ground wire extend along the juxtaposed direction of the fuse pieces. Spacing in the vicinity of the gate array is used for arrangement of the fuse blocks.

Abstract: A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.

Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract: A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

Abstract: A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

Abstract: A variable resistance nonvolatile memory device includes a memory cell array, a memory cell selection circuit, a write circuit, and a read circuit. The read circuit determines that a selected memory cell has a short-circuit fault when a current higher than or equal to a predetermined current passes through the selected memory cell. The write circuit sets another memory cell different from the faulty memory cell and located on at least a bit or word line including the faulty memory cell to a second high resistance state where a resistance value is higher than a resistance value in the first high resistance state, by applying a second high-resistance write pulse to the other memory cell.

Abstract: Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period P1 among the period P1, a period P2, and a period S that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods P1 and P2 and sets the selected word line to a third voltage different from the first voltage in the period S; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods P2 and S; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period S.

Abstract: A semiconductor integrated circuit includes a variable resistive element, a current supply unit and a control signal generating unit. The resistance of the variable resistive element is changed depending on current flowing therethrough. The current supply unit controls the current in response to a control signal. The control signal generating unit generates the control signal by sensing the change in the resistance of the variable resistive element.

Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract: A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.

Abstract: A magnetic field sensing system includes one or more magnetoresistive random access memory (MRAM) cells, and may be configured to determine one or more of a presence, a magnitude, and a polarity of an external magnetic field incident upon an MRAM cell. In some examples, a control module of the system controls a write current source, or another device, to provide a write current through a write line associated with the MRAM cell to induce a magnetic field proximate to the MRAM cell. The magnetic field may be less than a magnetic switching threshold of the MRAM cell. After initiating the provision of the write current through the write line, the control module may determine a magnetic state of the MRAM cell, and determine a presence of an external magnetic field incident upon the MRAM cell based at least in part on the magnetic state of the MRAM cell.

Abstract: Magnetoresistive elements, and memory devices including the same, include a free layer having a changeable magnetization direction, a pinned layer facing the free layer and having a fixed magnetization direction, and an auxiliary element on a surface of the pinned layer. The auxiliary element has a width smaller than a width of the pinned layer, and a magnetization direction fixed to a direction the same as a direction of the fixed magnetization direction of the pinned layer.

Abstract: According to one embodiment, a nonvolatile memory device includes: a magnetic memory element and a control unit. The magnetic memory element includes a stacked body, and a first and a second stacked units. The first stacked unit includes a first and second ferromagnetic layers and a first nonmagnetic layer provided between the first and the second ferromagnetic layers. The second stacked unit includes a third ferromagnetic layer and a nonmagnetic tunneling barrier layer stacked with the third ferromagnetic layer. The control unit is configured to implement a first operation of setting the magnetic memory element to be in a first state. The first operation includes a first preliminary operation of applying a first pulse voltage; and a first setting operation of applying a second pulse voltage having a second rising time to the magnetic memory element after the first preliminary operation.

Abstract: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.

Abstract: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.

Abstract: A temperature dependent electric element includes a phase change portion including at least one conductive phase change material having a predetermined phase transition temperature, a detector portion configured to detect a change in conductivity of the phase change material caused by a temperature change to a detect phase transition of the phase change material based on the detected change in conductivity of the phase change material, a temperature calibration part configured to conduct temperature calibration by adjusting a temperature at which the phase change material exhibits the phase transition detected by the detector portion based on the change in the conductivity of the phase change material to the predetermined phase transition temperature of the phase change material, and a substrate on which the phase change portion, the detector portion, and the temperature calibration part are integrally arranged.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: Disclosed is an system and method for reading a flash memory cell with an adjusted read level. A current read level is adjusted to a new read level associated with increasing a first error rate to decrease a second error rate. The first error rate is associated with determining that the most significant bit of the flash memory cell is a binary 1 and the second error rate is associated with determining that the most significant bit is a binary 0. On reading the memory cell, a probability value is generated for the most significant bit, the probability being higher if the bit is equivalent to a binary 0 than if the bit is equivalent to a binary 1.

Abstract: Described embodiments provide enhanced read accuracy of a multi-level cell (MLC) flash memory. A read request for desired cells is received by a media controller of the memory. The media controller sets m thresholds to initial values, each threshold corresponding to a cell voltage level of the memory, and measures the cell voltage level of a given cell. For each of the desired cells of the memory, the media controller iteratively, until the measured cell voltage level converges on one of the thresholds, compares the measured cell voltage level to the thresholds. If the measured cell voltage level does not converge on one of the thresholds, the media controller updates the thresholds, remeasures the cell voltage level and compares the remeasured cell voltage level to the updated thresholds. Once the measured cell voltage level converges on a threshold, the media controller determines a binary level of the cell.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array including memory cell transistors configured to store information in accordance with n (n is an integer larger than 2) threshold voltage levels, and a control circuit configured to control the memory cell array. In a write operation, the control circuit shifts a threshold voltage level of a write target memory cell transistor to a base threshold level of the n threshold levels, except for a threshold level having a highest voltage and a threshold level having a lowest voltage. Then the control circuit shifts the threshold voltage level of the write target memory cell transistor from the base threshold level to one of the n threshold levels.

Abstract: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor.

Abstract: To store input data in a plurality of memory cells, a mapping function of bit sequences to physical parameter states of the cells is provided. The cells are programmed, in accordance with the mapping function, to store the input data, in a way that would store uniformly distributed data with a programming state distribution other than any native state distribution of the mapping function. To store input data in a single memory cell, a mapping function of bit sequences to states of a physical parameter of the cell, such that if uniformly distributed data were stored in a plurality of such memory cells then the states of the physical parameter of the cells would be distributed non-uniformly, is provided. The memory cell is programmed to store the input data in accordance with the mapping function.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: A signal transmission system is provided which connects a memory controller and a plurality of semiconductor memories. The signal transmission system comprises a semiconductor device arranged between the memory controller and the plurality of memories, in which: the semi-conductor device comprises a control circuit; and the control circuit receives a signal from the semiconductor memory and outputs a control signal to the memory controller in response to the signal from the semiconductor memory.

Abstract: A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.

Abstract: A nonvolatile semiconductor memory device includes bit lines, word lines, NAND strings, source lines, first and second select gate transistors, and a controller. After giving a first potential to the second select gate transistors, the controller gives a second potential lower than the first potential to the second select gate transistors, gives a third potential to the memory cells which are insufficient in the writing, gives a fourth potential higher than the third potential to the memory cells which are just before completion of the writing, and gives a fifth potential higher than the fourth potential to the memory cells which are completed in the writing. The first potential is capable of turning on the second select gate transistors. The second potential is capable of turning off the second select gate transistors.

Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.

Abstract: A semiconductor memory device and a method of operating same includes reading a number of program/erase operations stored in a program/erase number storage unit, setting a pulse width of a program voltage based on the read number of program/erase operations, and performing a program operation on memory cells using the program voltage having the set pulse width. Setting of the pulse width of the program voltage includes decreasing the pulse width of the program voltage as the number of program/erase operations increases.

Abstract: A memory device capable of being operated with a single potential uses capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor.

Abstract: A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time.

Abstract: A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled.

Abstract: Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.

Abstract: An apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The method can include forming a second stacked body, removing the second stacked body formed in a region where a first memory unit will be formed, forming a first stacked body, and removing the first stacked body formed in a region where a second memory unit will be formed. The method can include simultaneously processing the first stacked body formed in a region where the first memory unit will be formed and the second stacked body formed in a region where the second memory unit will be formed to form a memory cell of the first memory unit from the first stacked body and form a memory cell of the second memory unit from the second stacked body.

Abstract: Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

Abstract: A semiconductor storage device according to the present embodiment includes local word lines and bit lines intersecting the local word lines. Each memory segment includes nonvolatile memory cells. Each memory segment corresponds to a plurality of the local word lines. A sense amplifier corresponds to a plurality of the bit lines. A global word line corresponds to a plurality of the local word lines, and is commonly driven in the memory segments. A decoder is connected between the global word line and the local word lines corresponding to the global word line, and selectively drives a certain local word line from the local word lines. A segment controller is provided in each memory segment, and selects one of the memory segments to be driven. An input/output part outputs read data from the memory segments or receives write data to the memory segments.

Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.