Patents Issued in September 30, 2014
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Patent number: 8848459Abstract: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.Type: GrantFiled: March 13, 2012Date of Patent: September 30, 2014Assignee: Renesas Electronics CorporationInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Patent number: 8848460Abstract: A plurality of buffer circuits and data buses coupled to the buffer circuits are included in a device. Each of the data buses includes first and second portions. The first portions of the data buses are arranged at a first pitch in the second direction, and the second portions of the data buses are arranged at a second pitch in the second direction, the second pitch being smaller than the first pitch.Type: GrantFiled: March 14, 2012Date of Patent: September 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Koji Yasumori, Hisayuki Nagamine
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Patent number: 8848461Abstract: A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.Type: GrantFiled: May 4, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jonathan Tsung-Yung Chang, Kun-Hsi Li, Chiting Cheng
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Patent number: 8848462Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.Type: GrantFiled: September 14, 2012Date of Patent: September 30, 2014Assignee: Mediatek Inc.Inventors: Yan-Bin Luo, Chih-Chien Hung, Qui-Ting Chen, Shang-Ping Chen
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Patent number: 8848463Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.Type: GrantFiled: December 3, 2013Date of Patent: September 30, 2014Assignee: Apple Inc.Inventors: Brian J. Campbell, Vincent R. von Kaenel, Daniel C. Murray, Gregory S. Scott, Sribalan Santhanam
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Patent number: 8848464Abstract: A semiconductor device which is capable of high-speed writing with less power consumption and suitable for multi-leveled memory, and verifying operation. A memory cell included in the semiconductor device included a transistor formed using an oxide semiconductor and a transistor formed using a material other than an oxide semiconductor. A variation in threshold value of the memory cells is derived before data of a data buffer is written by using a writing circuit. Data in which the variation in threshold value is compensated with respect to the data of the data buffer is written to the memory cell.Type: GrantFiled: April 25, 2012Date of Patent: September 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yusuke Sekine, Kiyoshi Kato
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Patent number: 8848465Abstract: A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword.Type: GrantFiled: June 26, 2012Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Seo-Hee Kim, Seong-Hyun Jeon, Hoi-Ju Chung, Sung-Hoon Kim
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Patent number: 8848467Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.Type: GrantFiled: April 30, 2013Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsien Hua, Yu-Hao Hsu, Chen-Li Yang, Cheng Hung Lee
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Patent number: 8848468Abstract: A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state.Type: GrantFiled: August 19, 2011Date of Patent: September 30, 2014Assignee: PS4 Luxco S.a.r.l.Inventors: Katsuhiro Kitagawa, Shotaro Kobayashi
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Patent number: 8848469Abstract: A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.Type: GrantFiled: December 21, 2011Date of Patent: September 30, 2014Assignee: Hynix Semiconductor Inc.Inventors: Bo-Yeun Kim, Ji-Eun Jang
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Patent number: 8848470Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.Type: GrantFiled: August 29, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
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Patent number: 8848471Abstract: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.Type: GrantFiled: August 8, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras, Moinuddin K. Qureshi
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Patent number: 8848472Abstract: A plurality of master chips are arranged in a row on the wafer, each master chip including a power supply circuit providing a power supply voltage, and a plurality of slave chips are arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.Type: GrantFiled: December 12, 2012Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Hiroshi Sugawara
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Patent number: 8848473Abstract: A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data.Type: GrantFiled: November 22, 2013Date of Patent: September 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Naohisa Nishioka
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Patent number: 8848474Abstract: A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first transmission gate switch coupled between the first input node and the second input node, a second transmission gate switch coupled between a first common node of the first and second inverters and a second common node of the first and second inverters. The sense amplifier is maintained at a maximum gain point in a read cycle.Type: GrantFiled: January 22, 2013Date of Patent: September 30, 2014Assignee: LSI CorporationInventor: Sahilpreet Singh
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Patent number: 8848475Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.Type: GrantFiled: August 29, 2011Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Son, Seong-Jin Jang, Byung-Sik Moon, Hyuck-Chai Jung, Ju-Seop Park
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Patent number: 8848476Abstract: A charge pump circuit comprises a first booster set, a second booster group, and a detecting circuit. The first booster set receives a supply voltage and generates a first output voltage. The detecting circuit generates a detecting signal depending on the voltage level of the first output voltage. The second booster group receives the supply voltage and generates the first output voltage or a second output voltage according to the detecting signal. The second booster group is composed of a plurality of booster sets connected in parallel, wherein each booster set comprises a plurality of charge pump stages and a plurality of switch units. The number of serially-connected charge pump stages of each booster set in the second booster group is controlled by the plurality of switch units according to the stable voltage levels of the first and second output voltages.Type: GrantFiled: May 11, 2011Date of Patent: September 30, 2014Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Chung Shan Kuo
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Patent number: 8848477Abstract: An electric physical unclonable function (PUF) (100) is provided comprising a semiconductor memory element (110) connectable to a PUF control means for reading content from the memory element and for deriving at least in part from said content a digital identifier, such as a secret key. Upon powering the memory element it settles into one of at least two different stable states. The particular stable state into which the memory element settles is dependent at least in part upon random physical characteristics of the memory element introduced during manufacture of the memory element. Settling of the memory element is further dependent upon a control input (112) of the memory element.Type: GrantFiled: September 28, 2011Date of Patent: September 30, 2014Assignee: Intrinsic ID B.V.Inventors: Geert Jan Schrijen, Petrus Wijnandus Simons, Erik Van Der Sluis, Pim Theo Tuyls
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Patent number: 8848478Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.Type: GrantFiled: September 24, 2012Date of Patent: September 30, 2014Assignee: Micron Technology, Inc.Inventors: Krishnam R. Datla, William H. Radke, Robin Sarno, Laszlo Borbely-Bartis, Ken Kannampuzha
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Patent number: 8848479Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.Type: GrantFiled: March 24, 2011Date of Patent: September 30, 2014Assignee: eASIC CorporationInventors: Hui H. Ngu, Bruce Gieseke
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Patent number: 8848480Abstract: A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.Type: GrantFiled: April 30, 2013Date of Patent: September 30, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Perry H. Pelley
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Patent number: 8848481Abstract: Disclosed is a method of reconstructing a sound field. The method comprises receiving measured values of a first acoustic quantity measured at a set of measurement locations; computing a second acoustic quantity for a target location from a superposition of plane waves. The method comprises storing a set of representations of interpolations of respective functions, each function being a function of two or less input parameters; and computing comprises computing each of a set of correlation functions, each correlation function being indicative of a correlation of the plane waves at a first one of said measurement locations with the plane waves at a second location, as a linear combination of values obtained from the set of representations of interpolations.Type: GrantFiled: June 26, 2009Date of Patent: September 30, 2014Assignee: Bruel & Kjaer Sound & Vibration Measurement A/SInventor: Jørgen Hald
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Patent number: 8848482Abstract: An ultrasound probe connected to an ultrasound diagnostic apparatus configured to transmit an ultrasound beam to a target object is provided. The ultrasound probe includes a switching unit including N/2 channels, each channel configured to switch between a first pole and a second pole, wherein N is a natural number, N/2 first transducer elements connected to the first pole and placed in two-dimensions, wherein a placement is defined in an x-axis direction and a y-axis direction, and N/2 second transducer elements connected to the second pole and placed in two-dimensions, wherein the placement is defined in the x-axis and y-axis directions, wherein a placement of a channel number of the first transducer elements and a placement of a channel number of the second transducer elements differ in the x-axis and y-axis directions.Type: GrantFiled: December 6, 2011Date of Patent: September 30, 2014Assignee: GE Medical Systems Global Technology Company, LLCInventor: Shinichi Amemiya
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Patent number: 8848483Abstract: Method and system for improving offset/azimuth distribution. The system includes plural streamers towed by a streamer vessel; a central source towed by the streamer vessel; first and second front sources located in front of the plural streamers along a traveling direction of the streamer vessel; and first and second large offset front sources located in front of the first and second front sources along the traveling direction. The offset distance between the first and second large offset front sources, along a cross-line direction, is larger than an offset distance between the first and second front sources.Type: GrantFiled: May 11, 2012Date of Patent: September 30, 2014Assignee: Cggveritas Services SAInventors: Fabrice Mandroux, Jean-Pierre Degez
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Patent number: 8848484Abstract: Methods and apparatus to filter acoustic waveforms in downhole environments are described. An example method involves receiving acoustic waveform data representing acoustic signals traversing at least a portion of a borehole adjacent a subterranean formation and performing a direct transform operation on the acoustic waveform data to generate wavelet map data. The wavelet map data comprises a time-frequency representation of the acoustic waveform data.Type: GrantFiled: December 4, 2011Date of Patent: September 30, 2014Assignee: Schlumberger Technology CorporationInventors: Henri-Pierre Valero, Shinichi Sunaga, Takeshi Endo
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Patent number: 8848485Abstract: Methods and apparatus for performing sonic well logging within a wellbore based on optical Distributed Acoustic Sensing (DAS) are provided. A sonic well logging system based on DAS may be capable of producing the functional equivalent of tens, hundreds, or even thousands of acoustic sensors. In this manner, the emplacement of the sonic well logging system based on DAS may not be nearly as complex or expensive as emplacing a sonic well logging system based on traditional methods. Furthermore, multiplexing may be simpler, downhole electronics need not be used, and the sonic well logging system may be used in extreme, high temperature environments.Type: GrantFiled: May 12, 2011Date of Patent: September 30, 2014Assignee: Weatherford/Lamb, Inc.Inventor: Francis X. Bostick, III
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Patent number: 8848486Abstract: An ultrasonic transmitter of an ultrasonic occupancy sensing device has adjustable ultrasonic signal output amplitude to prevent overload of an ultrasonic sensor associated with the ultrasonic occupancy sensing device. A circuit for controlling the operating voltage to a power driver of the ultrasonic transmitter allows field adjustment of the output thereof so that an optimal level (amplitude) for the transmitted ultrasonic signal may be found in an area of actual use (e.g., field adjustable).Type: GrantFiled: May 13, 2011Date of Patent: September 30, 2014Assignee: Cooper Technologies CompanyInventor: Brian E. Elwell
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Patent number: 8848487Abstract: A Nonlinear Timer apparatus characterized by having a display indicator (e.g. hands) with a large plurality of respectively contiguous perceived velocities, said indicator being configured to include predetermined non-zero acceleration for substantially any contiguous intermediate plurality of said respective indicator velocities. The apparatus is for portraying substantially nonlinear temporal frames of reference that are more honestly scaled to the individuals' respective circumstance than to the metronome mechanical tempos of industrial world time-clocks. However, the Nonlinear Timer apparatus is preferably represented according to classical concentrically rotating clock hands; digital or analog.Type: GrantFiled: June 30, 2009Date of Patent: September 30, 2014Inventor: Tidhar Eylon-Azoulay
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Patent number: 8848488Abstract: A timepiece mechanism for a secondary display of a first physical quantity, wherein a push-button activates first mechanism for the coupling/uncoupling of the secondary display to or from a movement including a first display, and a pivoting first physical quantity cannon-pinion heart, wherein the first mechanism controls the coupling/uncoupling to or from the movement. A second push-button controls the zero reset of the secondary display, by uncoupling the first coupling/uncoupling mechanism, and returning the heart-piece to the original position thereof. A second coupling/uncoupling control mechanism includes either a pivoting time zone wheel set including a friction wheel, meshing with the movement, and a time zone wheel which, when the wheel set is in the coupling position, drives a second physical quantity cannon-pinion heart and/or a third physical quantity cannon-pinion heart, the friction wheel and time zone wheel being coaxial and cooperating via friction; or an inter-time zone mechanism.Type: GrantFiled: July 20, 2011Date of Patent: September 30, 2014Assignee: Blancpain S.A.Inventor: Vincent Calabrese
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Patent number: 8848489Abstract: A calendar mechanism of a timepiece includes a month cam having a cam surface distinguishing between a long month (31 days) and a short month (30 days or less) and makes one rotation a year. A date indicator driving wheel has a date finger that makes one rotation every 24 hours and engages with a date wheel of a date indicator to rotate the date indicator. An operating lever structure has a proximal portion friction-engaged with an offset shaft to rotate around the offset shaft offset with respect to the rotation center of the date indicator driving wheel. The operating lever structure has a first distal end portion engaged with the month cam and a second distal end portion engaged with a month end tooth of the date indicator to effect additional date feeding by one day with respect to the date indicator at the end of a short month.Type: GrantFiled: November 29, 2012Date of Patent: September 30, 2014Assignee: Seiko Instruments Inc.Inventor: Shigeo Suzuki
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Patent number: 8848490Abstract: A reception apparatus includes a first determination unit to determine whether a state exists in which timing information and six orbital elements information can be obtained from GPS signals transmitted by only two GPS satellites. When the state exists, a calculation unit calculates a trajectory line having a predetermined width on a surface of the earth, based on the GPS signals transmitted by the two satellites. A second determination unit determines whether the trajectory line traverses a district of use stored by the apparatus. A time correcting unit obtains a current time using the obtained timing information, by correcting the timing information based on a time zone corresponding to the district of use, when the trajectory line traverses the district of use. The time correcting unit does not obtain the current time using the obtained timing information when the trajectory line does not traverse the district of use.Type: GrantFiled: December 7, 2012Date of Patent: September 30, 2014Assignee: Casio Computer Co., Ltd.Inventor: Toshio Hanabusa
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Patent number: 8848491Abstract: An analog electronic timepiece includes a plurality of hands; a dial plate having scales for time display; a driving unit that drives the hands so that the hands are driven independently of each other; and a control unit that transmits a drive signal to the driving unit and moves the hands to allow the hands to point to positions set for the respective hands. The control unit (i) allows each hand to point to one of positions of one o'clock to nine o'clock and twelve o'clock among the scales to indicate that a digit in a predetermined place represented by each hand is one of “1” to “9” and “0”; and (ii) expresses a numerical value by a combination of digits corresponding to the respective positions pointed by the respective hands.Type: GrantFiled: July 31, 2012Date of Patent: September 30, 2014Assignee: Casio Computer Co., Ltd.Inventor: Takeshi Miyake
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Patent number: 8848492Abstract: When recovering power from a motor driver, a forward voltage across a parasitic diode can reduce the recovery efficiency, and control of a power recovery operation can take an unnecessarily long time. In order to address this problem, the power recovery operation is performed as follows without being affected by a parasitic diode: near a peak position of a waveform of an induced current resulting from free oscillation of a rotor after a drive pulse is output, a recovery pulse having such a level that the rotor does not rotate is output from a terminal different from a motor driver terminal to which the drive pulse was output. Also, by adjusting the width and output timing of the recovery pulse based on a power supply voltage, the power recovery can be optimized for the power supply voltage.Type: GrantFiled: February 9, 2011Date of Patent: September 30, 2014Assignees: Citizen Holdings Co., Ltd., Citizen Watch Co., LtdInventors: Masaaki Namekawa, Yu Takyo
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Patent number: 8848493Abstract: In a method for controlling an alarm function of an electronic device, an alarm time, an alarm mode, a plurality of control modes of the alarm function and a shaking frequency and an audio file corresponding to each of the control modes are set. If a current time matches the alarm time, the alarm function is started by activating the alarm mode and a monitor unit is enabled to monitor acceleration values of the electronic device. A first shaking frequency in a first predetermined time limit is recorded according to the acceleration values. The control mode corresponding to the first shaking frequency is confirmed, and the audio file corresponding to the confirmed control mode is output. The method further controls the alarm function according to the confirmed control mode.Type: GrantFiled: April 26, 2012Date of Patent: September 30, 2014Assignees: Shenzhen Futaihong Precision Industry Co., Ltd., Chi Mei Communications Systems, Inc.Inventor: Cheng-Ping Dai
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Patent number: 8848494Abstract: A plasmon generator has a front end face located in a medium facing surface of a magnetic head. The plasmon generator includes a first portion formed of a first metal material and a second portion formed of a second metal material. The first portion has an inclined surface facing toward the front end face. The second portion is located between the inclined surface and the front end face, and includes a first end face located in the front end face and a second end face in contact with the inclined surface. The second metal material is higher in Vickers hardness than the first metal material. The first portion has a plasmon exciting part. The front end face generates near-field light.Type: GrantFiled: March 4, 2013Date of Patent: September 30, 2014Assignees: Headway Technologies Inc., Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Hironori Araki, Seiichiro Tomita, Ryuji Fujii
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Patent number: 8848495Abstract: A dual plasmon generator (PG) mirror image structure is used during fabrication of a TAMR head to locally anneal the PGs without substantially elevating the temperature in adjacent layers. Two PGs have narrow peg portions aligned head to head, and larger back end portions with a back side facing away from the eventual ABS. A first lead is attached to a back side of a first PG while a second lead is connected to a back side of a second PG. A 10 mA current is injected into a first PG and exits from the second PG and causes resistive heating in the rod-like portions where the temperature may be raised by 250° C. or more. A temporary overcoat layer may be formed over the PGs to dissipate heat and to keep the PGs from deforming during the annealing step.Type: GrantFiled: December 2, 2013Date of Patent: September 30, 2014Assignee: Headway Technologies, Inc.Inventors: Yan Wu, Kowang Liu
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Patent number: 8848496Abstract: A recording medium comprises an IC chip including circuitry configured to record data of one or more kinds of software, transmit and receive information to and from an external apparatus without contacting the external apparatus, and communicate with the external apparatus and execute mutual authentication processing for permitting access to the recorded information. The data recorded on the circuitry includes identification information for respective kinds of software recorded on a recording surface of the recording medium, key information necessary for installation of the respective kinds of software, and usage control information indicating a number of installations available for installation of the respective kinds of software. The key information is readout to the external apparatus and the usage information is rewritten by the external apparatus only when mutual authentication is correctly performed between the IC chip and the external apparatus.Type: GrantFiled: January 31, 2011Date of Patent: September 30, 2014Assignee: Sony CorporationInventor: Susumu Senshu
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Patent number: 8848497Abstract: A recording management apparatus includes: a control unit configured to perform track setting processing arranged to set a fixed management information track where management information to be fixedly disposed with a data structure conforming to the UDF, in a layer on the front-most side as viewed from a laser entry face side, to a recording medium having a plurality of layers serving as recording layers where recording of information is performed by laser irradiation on which a track serving as a continuous recording area is formed in which recording of data is performed, closing track processing arranged to set the fixed management information track to a consecutive recording completed state immediately after setting, and writing request processing arranged to record, by performing management information writing request for the fixed management track which has been closed, management information relating to this writing request in another track by sparing processing.Type: GrantFiled: June 14, 2013Date of Patent: September 30, 2014Assignee: Sony CorporationInventor: Tomotaka Kuraoka
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Patent number: 8848498Abstract: A start-up method of an optical disk drive, comprising: starting to accelerate a spindle motor after initializing a digital signal processor; starting an laser diode driver of an optical pickup head after the spindle motor starts accelerating; and starting a servo control of the optical pickup head. During the step of starting the laser diode driver, the spindle motor is accelerating.Type: GrantFiled: May 1, 2013Date of Patent: September 30, 2014Assignee: Lite-On Technology CorporationInventor: Chih-Yuan Hu
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Patent number: 8848499Abstract: In a multilayer optical disc having information layers conforming to a plurality of different optical disc standards, because the type of each information layer is not recorded in the other information layers, in read and write operations by a compatible optical disc device conforming to a plurality of optical disc standards, every time the information layer being accessed changes, it has been necessary to read the type of the information layer and select a method of generating a tracking error signal adapted to the type of information layer, so access has taken time. In order to solve the above problem, in the optical multilayer disc according to the present invention, having information layers conforming to a plurality of different optical disc standards, in an area in one of the information layers, information about the other information layers is recorded. The time required to access the other information layers can be reduced by using this information to select a tracking error signal generating method.Type: GrantFiled: October 25, 2013Date of Patent: September 30, 2014Assignee: Mitsubishi Electric CorporationInventors: Hironori Nakahara, Nobuo Takeshita, Masaharu Ogawa
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Patent number: 8848500Abstract: This optical read/write apparatus has first and second optical heads 2a, 2b and includes location control sections 4a, 4b which make the relative arrangement of the first and second optical heads 2a, 2b variable according to either the environmental temperature or from one medium to another. The first optical head 2a performs a write operation to record a mark on an optical storage medium 1, and the second optical head 2b reads the information that has been written by scanning the recorded mark. The apparatus further includes a nonvolatile memory which saves the relative arrangement of the first and second optical heads 2a and 2b either on an environmental temperature basis or on a medium by medium basis.Type: GrantFiled: July 20, 2012Date of Patent: September 30, 2014Assignee: Panasonic CorporationInventors: Emi Kitano, Harumitsu Miyashita, Ryoji Hirose
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Patent number: 8848501Abstract: The present application discloses detection lens provided with lens portion and flange portion including first surface connected to lens portion and second surface opposite to first surface. Flange portion includes base along optical axis of lens portion, and first to fourth projections projecting from base. First and second projections are point-symmetric around optical axis. Third and fourth projections are point-symmetric around optical axis. Flange portion excludes projection extending beyond second surface. First projection includes first intersecting surface which intersects with first axis. Second projection includes second intersecting surface which intersects with first axis. Third projection includes third intersecting surface which intersects with second axis. Fourth projection includes fourth intersecting surface which intersects with second axis. First distance between first and second intersecting surfaces is longer than second distance between third and fourth intersecting surfaces.Type: GrantFiled: December 20, 2012Date of Patent: September 30, 2014Assignee: Panasonic CorporationInventors: Toshiyasu Tanaka, Noriaki Terahara, Takeshi Ohta, Shinsuke Hatanaka, Fumitomo Yamasaki
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Patent number: 8848502Abstract: A recording/reproducing apparatus having an optical pickup device which is efficient in light use having little spherical aberration.Type: GrantFiled: May 20, 2003Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-woo Lee, Jang-hoon Yoo
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Patent number: 8848504Abstract: Alien noise is removed from one or more receptor DSL lines after self-FEXT has been eliminated or reduced. Information about the alien noise in the form of slicer errors can be obtained from one or more donor DSL lines that may or may not be in the same domain (e.g., a vectored DSL system).Type: GrantFiled: October 14, 2011Date of Patent: September 30, 2014Assignee: Ikanos Communications, Inc.Inventors: Shailendra K. Singh, Kevin D. Fisher
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Patent number: 8848505Abstract: A method for optimizing resource allocation for signal conditioning of DSL or other signal lines includes developing a signal quality metric using crosstalk interference and, optionally, signal to noise level. Use of existing pilot tone training selectively assigned to signal lines allows determination of the signal quality metric. A threshold level is selected and all signal lines having a signal quality metric above the threshold level are assigned crosstalk cancellation resources. Because the total number of signal lines requiring crosstalk cancellation is not known at the beginning, a particular threshold level may result in allocation of more than the available resources or allocation of significantly less than the available resources. When this happens the threshold level may be adjusted and the process repeated until crosstalk cancellation resources are assigned up to a usable limit.Type: GrantFiled: May 6, 2013Date of Patent: September 30, 2014Assignee: Marvell International Ltd.Inventors: Pak Hei Matthew Leung, Raphael Jean Cendrillon
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Patent number: 8848506Abstract: An orthogonal frequency division multiplexing (OFDM) transmission device transmits OFDM symbols to at least one reception device and includes an OFDM transmission processing unit which generates a plurality of OFDM symbols; a pilot insertion unit which inserts pilot tones into each of the plurality of OFDM symbols; and a control unit which controls the pilot insertion unit to insert the pilot tones according to a pilot insertion pattern which is selected to correspond to a communication environment from among a plurality of pilot insertion patterns.Type: GrantFiled: April 30, 2008Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-bo Kim, June-hee Lee
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Patent number: 8848507Abstract: A computer readable storage medium includes a set of instructions executable by a processor. The instructions are operable to receive a node indication for each of a plurality of undamaged backbone nodes of a communication network; receive a link indication for each of a plurality of backbone links connected between undamaged backbone nodes of the communication network; and assign a fragment identifier to each of a plurality of backbone fragments, each of the backbone fragments comprising one or more of the backbone nodes, wherein the one or more backbone nodes comprising each backbone fragment indicates connectivity between the one or more backbone nodes.Type: GrantFiled: December 19, 2008Date of Patent: September 30, 2014Assignee: AT&T Intellectual Property I, LPInventor: Yury Bakshi
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Patent number: 8848508Abstract: A method and apparatus is disclosed for providing gateway anycast virtual MAC reachability in extended subnets. When an extended L2 subnet spans more than one geographical location, it is desirable that the gateway MAC addresses learned in each location be the same across all IP hosts. Accordingly, the gateway MAC address may be preserved (i.e., programmed) in more than one port on a bridge, such as both a local port and a LAN extension port. The bridge may forward traffic having the anycast MAC address to the closest instance of the MAC address, rather than replicating the traffic to the multiple ports on which the anycast MAC address is programmed. If the gateway reachable on the local port goes down, the frame may be forwarded to the local gateway in the second layer 2 subnet over the LAN extension port.Type: GrantFiled: November 16, 2009Date of Patent: September 30, 2014Assignee: Cisco Technology, Inc.Inventors: Victor M. Moreno, Robert Starmer, Sanjay Sane
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Patent number: 8848509Abstract: A three stage folded Clos network is used for Ethernet routing with improved efficiency for computational complexity, network administration, multicast addressing and load redistribution upon failure. The network includes an array of root nodes coupled to an array of edge nodes. Forwarding states are computed and installed for spanning trees rooted on the root nodes. When an edge node is identified as having a failed connection to a root node, a shortest path first (SPF) tree rooted on that edge node is constructed for each Backbone VLAN identifier (B-VID) for the spanning trees rooted on that root node and use the failed connection. A filtering database in each node is populated for edge node pairs having a common service identifier, and unicast and multicast data are forwarded between the edge node pairs according to the filtering database via the SPF trees using a hybrid multicast addressing.Type: GrantFiled: April 27, 2012Date of Patent: September 30, 2014Assignee: Telefonaktiebolaget L M Ericsson (Publ)Inventor: David Ian Allan
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Patent number: 8848510Abstract: The present invention relates to a wireless communication system, and provides an efficient control information transmission method and apparatus for supporting a multiple antenna transmission technique. According to one embodiment of the present invention, a method for transmitting downlink hybrid automatic repeat request (HARQ) information on a uplink multiple codeword transmission comprises the steps of: receiving the uplink multiple codeword transmission; generating HARQ information on each of multiple codewords, on the basis of the result of decoding each of the multiple codewords; modulating the HARQ information; and transmitting the modulated HARQ information through one or more physical HARQ indicator channels (PHICHs).Type: GrantFiled: November 9, 2010Date of Patent: September 30, 2014Assignee: LG Electronics Inc.Inventors: Hyun Soo Ko, Jae Hoon Chung, Bin Chul Ihm, Moon Il Lee