Abstract: The present invention relates to a package structure of an optical module. The light emitting chip and the light receiving chip are disposed on the light emitting region and the light receiving region of the substrate, respectively. Two encapsulating gels are coated on the light emitting chip and the light receiving chip to form a first and a second hemispherical lens portions thereon, respectively. A cover is affixed on the substrate and each of the encapsulating gels and has a light emitting hole and a light receiving hole, where the first and second lens portions are accommodated, respectively. In this way, the package structure of an optical module of the present invention can be made with the encapsulating gels of different curvatures according to different needs to improve the luminous efficiency of the light emitting chip effectively and to improve the reception efficiency of the light receiving chip.

Abstract: This invention relates to an optical module package structure. A substrate is defined with a light receiving region and a light emitting region. A light receiving chip and a light emitting chip are disposed on the light receiving region and the light emitting region of the substrate, respectively. An electronic unit is disposed on the substrate and electrically connected to the light emitting chip. Two encapsulating gels are coated on each of the chips and the electronic unit. A cover is disposed on the substrate and has a light emitting hole and a light receiving hole, located above the light emitting chip and the light receiving chip, respectively. In this way, the package structure of the optical module of the present invention integrates passive components, functional ICs or dies into a module, and the optical module provides the functions of current limiting or function adjustment.

Abstract: A package structure of an optical module includes: a substrate defined with a light-emitting region and a light-admitting region; a light-emitting chip disposed at the light-emitting region of the substrate; a light-admitting chip disposed at the light-admitting region of the substrate; two encapsulants for enclosing the light-emitting chip and the light-admitting chip, respectively; and a shielding layer formed on the substrate and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively. Accordingly, the optical module package structure simplifies a packaging process and cuts manufacturing costs.

Abstract: An optoelectronic semiconductor device includes at least one radiation-emitting and/or radiation-receiving semiconductor chip including a radiation passage surface and a mounting surface opposite the radiation passage surface, wherein the mounting surface includes a first electrical contact structure and a second electrical contact structure electrically insulated from the first electrical contact structure, and wherein the radiation passage surface is free of contact structures, a reflective sheath surrounding the at least one semiconductor chip at least in sections, and a protective sheath surrounding the at least one semiconductor chip and/or the reflective sheath at least in sections.

Abstract: A method and structure for forming an array of micro devices is disclosed. An array of micro devices is formed over an array of stabilization posts included in a stabilization layer. The stabilization layer is bonded to a spacer side of a carrier substrate. The spacer side of the carrier substrate includes raised spacers extending from a spacer-side surface of the carrier substrate.

Abstract: A chip-on-film package includes a base film including a bending area, an integrated circuit chip at an upper surface of the base film, a first line at the upper surface of the base film and overlapping the bending area, a second line at a lower surface of the base film and overlapping the bending area, a via pattern penetrating the base film to electrically couple the first line and the second line, and a common line coupled to the first line and to the integrated circuit chip, wherein at least a portion of the first line does not overlap at least a portion of the second line in a plan view.

Abstract: A pixel structure includes an active switching device, a patterned common electrode layer, an insulation layer, a patterned oxide electrode layer and a patterned passivation layer. The insulation layer covers the patterned common electrode layer. The patterned oxide electrode layer is disposed on the insulation layer and electrically connected to the active switching device. The patterned oxide electrode layer includes a semiconductor part and a conductive part. The semiconductor part and the patterned common electrode layer substantially overlap to each other in a vertical projection direction. The conductive part and the semiconductor part are connected to each other, the conductive part and the patterned common electrode layer do not overlap to each other in the vertical projective direction, and the conductive part is a pixel electrode. The patterned passivation layer covers the semiconductor part, and the patterned passivation layer has an opening exposing the conductive part.

Abstract: A lighting apparatus includes a light source and a light conversion layer disposed proximate the light source, the light conversion layer comprising a plurality of quantum dots (QDs) or phosphors, and a plurality of transparent thermally conductive particles, embedded in a matrix material to improve heat dissipation.

Abstract: An LED chip for use in an LED chip array forming a continuous array of LEDs. The LED chip comprises an array of LEDs on a substrate. LEDs in a row of the array are longitudinally offset from corresponding LEDs in another row. Adjacent LEDs in each row of the array are separated by a longitudinal pitch. At least part of an end face of the substrate is angled with respect to a transverse axis of the LED chip such that the LED chip is positionable adjacent another LED chip to maintain the longitudinal pitch between adjacent LEDs on different chips.

Abstract: An optoelectronic module (100) is defined, comprising at least one semiconductor chip (10) provided for emitting electromagnetic radiation and at least one holding device (20) which is adapted to fix in place a device (50) for encoding at least one optical or electronic parameter of the optoelectronic module (100). Furthermore, a process for the production of the optoelectronic module (100) is defined.

Abstract: Disclosed herein is a light emitting module. The light emitting module according to an exemplary embodiment includes a circuit board having a cavity and including a circuit pattern at a region which does not have the cavity, an insulation substrate disposed in the cavity while being formed, at an upper portion thereof, with at least one pad, and at least one light emitting device disposed on the pad, wherein a joining structure is disposed between a bottom surface of the cavity and a bottom surface of the insulation substrate.

Abstract: A light-emitting diode device having two electrode pads for connecting to an external power comprises a substrate; a plurality of light-emitting diode units on the substrate; and a plurality of conductive connecting structures electrically connecting the plurality of light-emitting diode units; wherein the two electrode pads are encircled by the plurality of light-emitting diode units.

Abstract: In one embodiment, a light source comprising a substrate, a die, a liquid encapsulant, an attachment member and a resilient cover configured to hold the liquid encapsulant is disclosed. At least a portion of the resilient cover is easily stretchable so as to absorb size increment of the liquid encapsulant due to thermal expansion. One other embodiment discloses a light-emitting device comprising a die, a liquid encapsulant and the resilient cover. The resilient cover may comprise a dome shaped portion, a vertical portion and a thermal joint portion. In another embodiment, a lighting apparatus having similar resilient cover is disclosed. The resilient cover may further comprise a thermal joint portion having first and second indentations for absorbing thermal expansion.

Abstract: A package structure of an optical module is provided and includes: a light-emitting chip and a light-admitting chip which are disposed at a light-emitting region and a light-admitting region of a substrate, respectively; two encapsulants for enclosing the light-emitting chip and the light-admitting chip, respectively, and forming hemispherical first and second lens portions above the light-emitting chip and the light-admitting chip, respectively; a cover disposed on the substrate and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively, and the first and second lens portions are received in the light-emitting hole and the light-admitting hole, respectively.

Abstract: A package for mounting a light emitting device thereon. The package includes a substrate, a light emitting device mounting part including a wiring formed on one surface of the substrate, the wiring including two areas that are arranged facing each other and being separated a predetermined interval apart from each other in a plan view, first and second through-wirings that penetrate the substrate and are provided on the two areas, respectively, each of the first and second through-wirings including one end electrically connected to the light emitting device mounting part and another end exposed from another surface of the substrate. A part of each of the first and second through-wirings includes a maximum part having a plan-view shape that is larger than a plan-view shape of the one end of each of the first and second through-wirings.

Abstract: A light emitting device includes a light emitting element configured to emit visible light; a fluorescent substance excited by light from the light emitting element and configured to emit visible light; a translucent member containing a translucent base material, which provided on the fluorescent substance or configured to contain the fluorescent substance, and provided on the light emitting element; and a film provided on an upper surface of the translucent member, and configured as an agglutination of nanoparticles having a different refractive index from the base material.

Abstract: The present application discloses a light-emitting element comprising a semiconductor light-emitting stack emitting a first light which has a first color coordinate, a first wavelength conversion material on the semiconductor light-emitting stack converting the first light to emit a second light, and a second wavelength conversion material on the first wavelength conversion material converting the second light to emit a third light. The first light and the second light are mixed to be a fourth light having a second color coordinate. The third light and the fourth light are mixed to be a fifth light having a third color coordinate, and the second color coordinate locates at the top right of the first color coordinate and the third color coordinate locates at the top right of the second color coordinate.

Abstract: The present invention relates to a light-emitting device that is capable of preventing an increase in forward voltage while improving optical output characteristics, and to a method for manufacturing same.

Abstract: A flexible lighting element is provided, comprising: a first substrate; first and second conductive elements over the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first and second contacts being electrically connected to the first and second conductive elements, respectively, and the light-emitting element emitting light from a second surface opposite the first surface; a transparent layer located adjacent to the second surface; and a transparent affixing layer located between the first substrate and the transparent layer, wherein the transparent layer and the transparent affixing layer are both sufficiently transparent to visible light that they will not decrease light transmittance below 70%, and the first and second conductive layers are at least partially transparent to visible light, or are 300 ?m or smaller in width, or are concealed by a design feature from a viewing direction.

Abstract: A lighting element is provided, comprising: a substrate; a first conductive element on the substrate; a light-emitting element having first and second contacts on top and bottom surfaces, respectively; a transparent layer adjacent to the top surface; an affixing layer between the substrate and the transparent layer, affixing the transparent layer to the substrate; and a second conductive element beneath the transparent layer and proximate to the top surface, wherein the first and second contacts are electrically connected to the first and second conductive elements, respectively, the light-emitting element emits light in a range of wavelengths between 10 nm and 100,000 nm, the transparent and affixing layer's will not decrease light transmittance below 70%, and the first and second conductive elements are at least partially transparent to visible light, or are 300 ?m or smaller in width, or are concealed by a design feature from a viewing direction.

Abstract: A package structure of an optical module includes: a substrate having a frame defined with a light-emitting region and a light-admitting region; a light-emitting chip disposed at the light-emitting region of the substrate; a light-admitting chip disposed at the light-admitting region of the substrate; two encapsulants formed in the frame and enclosing the light-emitting chip and the light-admitting chip, respectively; and a shielding layer formed on the frame and the encapsulants and having a light-emitting hole and a light-admitting hole, wherein the light-emitting hole and the light-admitting hole are positioned above the light-emitting chip and the light-admitting chip, respectively. The optical module package structure uses an opaque glue to reduce costs and total thickness of the package structure.

Abstract: A light emitting diode includes a semiconductor epitaxial stack structure, a first transparent conductive layer and at least one second transparent conductive layer. The semiconductor epitaxial stack structure includes a first semiconductor layer, an active layer and a second semiconductor layer. The active layer is disposed on a portion of the second semiconductor layer. The first semiconductor layer is disposed on the active layer. The first transparent conductive layer is disposed on the first semiconductor layer, and includes plural first crystalline particles, wherein the average size thereof is d1. The second transparent conductive layer is disposed on the first transparent conductive layer, and includes plural second crystalline particles, wherein the average size thereof is d2, and d1 is greater than d2.

Abstract: A wiring substrate includes a wiring pattern that is formed on a surface of a conductive board via an insulation layer and an extension part that is extended from the wiring pattern. The extension part is disposed in a portion located immediately below a detachable connector. The detachable connector is connected to a fixed connector mounted on the wiring substrate and connected and fixed to the wiring pattern.

Abstract: A light emitting device uses an Ag wire and exhibits excellent light extraction efficiency. In the light emitting device, a pad electrode of a light emitting element and a mount electrode are connected to each other using an Ag wire. The pad electrode contains Pt in a region where the Ag wire is bonded.

Abstract: An IGBT is disclosed with a high emitter-gate capacitance, wherein an active cell region can include plural emitter and gate regions. A termination edge region can include a varied lateral doping region VLD. Each gate polysilicon layer can be arranged at a surface of the semiconductor substrate in the gate regions, separated from the semiconductor substrate by a first insulating layer. A first SIPOS layer and a covering second insulating layer overlie at least portions of the gate polysilicon layer. In a central area, the gate polysilicon layer is in electrical contact with the overlying first SIPOS layer whereas, in a peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer. A substrate surface at the VLD region is in electrical contact with a second SIPOS layer, and an increased gate-emitter capacitance may be achieved by slightly modifying etch masks during manufacturing.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Abstract: The disclosed lateral bipolar transistor is manufactured by a manufacturing process of self-alignedly implanting an impurity to a gate electrode and thermally diffusing the impurity to form a base layer and an emitter layer. The gate electrode is utilized as an independent fourth terminal in addition to base, emitter, and collector terminals, whereby hfe can be controlled and enhanced by a gate potential. Accordingly, the present invention can provide a bipolar transistor that is hardly affected by a manufacturing variation, or that can be corrected by the gate terminal, and that has a high gain.

Abstract: Various embodiments of a germanium-on-silicon (Ge—Si) photodiode are provided along with the fabrication method thereof. In one aspect, a Ge—Si photodiode includes a doped bottom region at the bottom of a germanium layer, formed by thermal diffusion of donors implanted into a silicon layer. The Ge—Si photodiode further includes a doped sidewall region of Ge mesa formed by ion implantation. Thus, the electric field is distributed in the intrinsic region of the Ge—Si photodiode where there is low dislocation density. The doped bottom region and sidewall region of the Ge layer prevent electric field from penetrating into the Ge—Si interface and Ge mesa sidewall region, where a large amount of dislocations are distributed. This design significantly suppresses dark current.

Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one layer; forming a doped contact layer on the III-V compound semiconductor-containing heterostructure; and forming a gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the doped contact layer. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

Abstract: A semiconductor device may include a fin disposed over a workpiece. The fin may include: a first semiconductive material disposed over the workpiece; an oxide of the first semiconductive material disposed over the first semiconductive material; a second conductive material disposed over and spaced apart from the oxide of the first semiconductive material; a first insulating material disposed around and lining the second semiconductive material; a conductive material disposed around the first insulating material; and a second insulating material disposed between the oxide of the first semiconductive material and a portion of the conductive material facing the workpiece, the second insulating material further lining sidewalls of the conductive material.

Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

Abstract: A compound semiconductor device includes a substrate, a p-type first semiconductor layer over the substrate and contains antimony, a p-type second semiconductor layer over the first semiconductor layer and contains antimony, an n-type third semiconductor layer over the second semiconductor layer, a fourth semiconductor layer between the first semiconductor layer and the second semiconductor layer, the fourth semiconductor layer containing phosphorus and having a thickness in which electrons tunnel between the first semiconductor layer and the second semiconductor layer, a first electrode in ohmic contact with the first semiconductor layer, and a second electrode in ohmic contact with the third semiconductor layer. The first semiconductor layer is made from a material whose contact resistance with the first electrode is lower than contact resistance of the second semiconductor layer.

Abstract: Certain embodiments provide a solid-state imaging device including a pixel portion, a charge storage portion, a first transfer gate portion, a charge detecting portion, a second transfer gate portion, and an offset gate portion. The charge storage portion stores the electrical charges generated in the pixel portion. The first transfer gate portion transfers electrical charges from the pixel portion to the charge storage portion, and the second transfer gate portion transfers the electrical charges from the charge storage portion to the charge detecting portion. The offset gate portion is provided between the second transfer gate portion and the charge detecting portion and is applied with a predetermined constant voltage. This offset gate portion includes an offset gate layer that has a plurality of projections formed at positions adjacent to the second transfer gate portion and an offset gate electrode.

Abstract: Certain embodiments provide a solid-state imaging device including a pixel portion, a charge storage portion, a first transfer gate portion transferring charge from the pixel portion to the charge storage portion, and a second transfer gate portion transferring the charge from the charge storage portion to the charge detection portion. The pixel portion includes a light sensing layer and a shield layer shielding the light sensing layer. The charge storage portion includes a charge storage layer shielding the charge storage layer. At least one of the shield layer for light sensing layer and the shield layer for charge storage layer includes a concave part to expose a part of the light sensing layer adjacent to the first transfer gate portion or a part of the charge storage layer adjacent to the second transfer gate portion.

Abstract: Certain embodiments provide a solid-state imaging device including a pixel portion including a first light receiving layer, a charge accumulation portion including a first charge accumulation layer which accumulates a charge, a first transfer gate portion, a charge detection portion and a second transfer gate portion. The first transfer gate portion transfers the charge from the pixel portion to the charge accumulation portion, and the second transfer gate portion transfers the charge from the charge accumulation portion to the charge detection portion. The charge detection portion causes a voltage drop corresponding to an amount of the charge transferred to this region. An impurity layer of a ring shape which includes an opening portion is provided on a surface of at least one of the first light reception layer of the pixel portion and the first charge accumulation layer of the charge accumulation portion.

Abstract: Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

Abstract: Embodiments described herein provide for a pH sensor that is configured for use over a pressure and temperature range. The ISFET die of the pH sensor is bonded to the substrate of the pH sensor with a bonding layer that is disposed between the substrate and the ISFET die. The pressure and temperature change across the pressure and temperature range generates an environmental force in the pH sensor. Further, the substrate or the bonding layer or both change volume over the pressure and temperature range, and the substrate or the bonding layer or both are configured such that the volume change induces a counteracting force that opposes at least a portion of the environmental force. The counteracting force is configured to maintain the change in piezoresistance of the ISFET die from the drain to the source to less than 0.5% over the pressure and temperature range.

Abstract: Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G1 formed along a periphery of the chip region CA and a gate finger portion G2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

Abstract: A photoelectric conversion device including a photoelectric conversion element including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type provided in contact with the first semiconductor region, a third semiconductor region of the first conductivity type provided apart from the second semiconductor region, a fourth semiconductor region of a second conductivity type provided between the second and the third semiconductor region, and a fifth semiconductor region of the first conductivity type provided apart from the third semiconductor region, wherein an impurity concentration of the third semiconductor region is lower than that of the fifth semiconductor region, and a depth of a lower-edge of the third semiconductor region from a surface of the semiconductor substrate is larger than that of a lower-edge of the fifth semiconductor region.

Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer. At least part of the area around the photoelectric transducer in a plan view contains an air gap and also has an isolation insulating layer for electrically insulating the photoelectric transducer and a photoelectric transducer adjacent to it from each other. The isolation insulating layer abuts on the top surface of the first conductivity type impurity layer.

Abstract: A solid-state imaging device includes a semiconductor layer, a reflector, and a plurality of element separating regions. In the semiconductor layer, a plurality of photoelectric conversion elements is arranged in a two-dimensional array. The reflector covers a surface of the semiconductor layer on a side opposite to a surface of the semiconductor layer on which alight is incident, and reflects the light. The element separating regions are formed in the semiconductor layer to physically and electrically separate the plurality of photoelectric conversion elements. Each of the element separating regions extend from the surface of the semiconductor layer on which the light is incident to the reflector and has a reflection surface for reflecting light.

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first C2 plates and second group serves as second.